KR20010063426A - Semiconductor device and method of manufacturing thereof - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to guarantee a design rule margin by forming a bit line in the first wafer and forming a transistor and a capacitor in the second wafer wherein a memory cell is formed as a buried bit line structure in which the bit line is connected to a drain of the transistor. CONSTITUTION: A transistor is composed of a word line(42), a drain(43) and a source(44). A bit line(33) is electrically connected to the drain, located in a lower portion of the transistor. A capacitor is electrically connected to the source, located in an upper portion of the transistor. The bit line is formed between the first interlayer dielectric(32) and the second interlayer dielectric(34) of the first wafer(31), electrically connected to the drain by a bit line contact plug(35).

Description

Semiconductor device and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, while achieving a design rule margin of a semiconductor device, it is possible to reduce the step between the cell region and the peripheral circuit region, thereby facilitating high integration and processing of the semiconductor device. The semiconductor element which can be performed, and its manufacturing method are related.

In general, as semiconductor devices become highly integrated and miniaturized, the area occupied per unit cell is also scaled in proportion to this, resulting in a lack of design rule margin between the contact plug for the charge storage electrode and the storage node. . In order to solve this problem, an inner cylinder structure combining a contact plug for a charge storage electrode and a charge storage electrode has been proposed. However, the inner cylinder structure has a disadvantage in that a short problem occurs between the charge storage electrode and the contact plug for the charge storage electrode when the structure of the active region is “I” type. there was. In addition, as the degree of integration increases, the step between the cell area and the peripheral circuit area becomes deeper, which makes it difficult to proceed with the subsequent process.

1 is a cross-sectional view of a conventional semiconductor device and a device for explaining the manufacturing method thereof.

Referring to FIG. 1, a method of manufacturing a conventional semiconductor device is as follows.

A trench isolation 12 is formed in the wafer 11 to define the active region. A transistor composed of a plurality of word lines 13, a drain 14, and a source 15 is formed on the wafer 11 in the active region. The word line 13 is covered by the first top insulating film 16 at the upper side and the word line spacer insulating film 17 at the side. After forming the first interlayer insulating film 18 on the entire structure including the transistor, the first interlayer insulating film 18 is etched by a self-aligned etching method to form contact holes in the drain and the source 14 and 15, respectively, A conductive material is embedded in the hole to form a bit line contact plug 19 in the drain 14 and a first contact plug 20 for the charge storage electrode in the source 15. The bit line 21 is connected to the bit line contact plug 19. The bit line 21 is covered by the second top insulating film 22 on the upper side and the bit line spacer insulating film 23 on the side. After forming the second interlayer insulating film 24 on the entire structure including the bit line 21, the second interlayer insulating film 24 is etched to expose the first contact plug 20 for the charge storage electrode to form a hole. . A conductive material is embedded in the hole to form a second contact plug 25 for a charge storage electrode connected to the first contact plug 20 for a charge storage electrode. The charge storage electrode 26 connected to the second contact plug 25 is formed. The capacitor 27 is formed on the charge storage electrode 26 by forming the dielectric film 27 and the plate electrode 28. The third interlayer insulating film 29 is formed over the entire structure including the capacitor.

The semiconductor device formed by the conventional method has a vertical structure in which a transistor is formed on a wafer, a bit line is formed on the transistor, and a capacitor is formed on the bit line. The structure of the conventional semiconductor device is misaligned during the etching process for forming the charge storage electrode because the margin between the second contact plug for the charge storage electrode and the charge storage electrode is insufficient when the process margin decreases as the semiconductor device is highly integrated and miniaturized. If (misalign) occurs, the contact is attacked and the device is not working. In this structure, if the second contact plug process for the charge storage electrode is omitted and an inner cylinder structure is formed, a short may occur between the contact plug and the charge storage electrode when misaligned. In addition, this structure is a structure that is continuously stacked from the wafer to deepen the step with the peripheral circuit area, making the subsequent process difficult.

Therefore, the present invention eliminates the contact plug process for the charge storage electrode and secures the design rule margin of the semiconductor device, while forming a bit line in a buried structure to reduce the step between the cell region and the peripheral circuit region to reduce the step of the semiconductor device. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can realize high integration and facilitate a process.

The semiconductor device of the present invention for achieving this object comprises a transistor consisting of a word line, a drain and a source; A bit line positioned below the transistor and electrically connected to the drain; And a capacitor positioned above the transistor and electrically connected to the source.

In addition, the semiconductor device manufacturing method according to the present invention comprises the steps of sequentially forming a first interlayer insulating film, a bit line and a second interlayer insulating film on the first wafer; Forming a contact plug for a bit line on the second interlayer insulating film; Bonding a second wafer to a surface of a second interlayer insulating film including the contact plug, and then thinning the film; Forming an isolation region on the thinned second wafer to define an active region, and then forming a transistor including a word line, a drain, and a source; Sequentially forming a nitride film and a third interlayer insulating film on the entire structure including the transistor; Sequentially etching the third interlayer insulating film and the nitride film by an etching process using a mask for charge storage electrodes to form holes for the charge storage electrodes to which the source is exposed; And forming a charge storage electrode connected to the source in the hole for the charge storage electrode, and sequentially forming a dielectric film and a plate electrode on the charge storage electrode.

1 is a cross-sectional view of a conventional semiconductor device and a device for explaining the manufacturing method thereof.

2A to 2F are cross-sectional views of a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: wafer 12: trench element separator

13: wordline 14: drain

15: source 16: first top insulating film

17 word line spacer insulating film 18 first interlayer insulating film

19: contact plug for bit line 20: first contact plug for charge storage electrode

21: bit line 22: second top insulating film

23: bit line spacer insulating film 24: second interlayer insulating film

25: second contact plug for the charge storage electrode

26: charge storage electrode 27: dielectric film

28 plate electrode 29 third interlayer insulating film

31: first wafer 32: first interlayer insulating film

33: bit line 34: second interlayer insulating film

35: contact plug for bit line 41: second wafer

41a: active region 41b: device isolation film

42: wordline 43: drain

44: source 45: top insulating film

46: nitride film 46a: spacer nitride film

47: third interlayer insulating film 48: hole for charge storage electrode

49: charge storage electrode 50: dielectric film

51: plate electrode

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 2A, after the first interlayer insulating layer 32 is formed on the first wafer 31, a bit line 33 is formed on the first interlayer insulating layer 32. After the second interlayer insulating film 34 is formed on the entire structure including the bit line 33, a portion of the second interlayer insulating film 34 is etched to form a contact hole through which the bit line 33 is exposed. After depositing a conductive material on the entire structure, including, planarization is performed by a chemical mechanical polishing (CMP) process, thereby forming a contact plug 35 for a bit line in the contact hole.

Referring to FIG. 2B, the second wafer 41 is adhered to the surface of the second interlayer insulating film 34 including the bit line contact plug 35 by using a bonding technique, and then, the chemical mechanical polishing process is performed. The wafer 41 is polished and thinned. In this case, the thickness of the thinned second wafer 41 may be a thickness that can be electrically connected to the bit line contact plug 35 by ion implantation. An isolation layer 41b is formed on the thinned second wafer 41 to define the active region 41a.

Referring to FIG. 2C, a transistor including a plurality of word lines 42, a drain 43, and a source 44 is formed on the second wafer 41 on which the active region 41a and the device isolation layer 41b are formed. . The top insulating layer 45 is formed on the word line 42.

In the above, the drain 43 and the source 44 are formed in the active region 41a of the second wafer 41 by performing a source / drain ion implantation process without a separate mask process. The drain 43 formed by the source / drain ion implantation process is electrically connected to the lower bit line contact plug 35 by self alignment by the word line 42 and the active region 41a. .

Referring to FIG. 2D, a nitride nitride film 46 for spacers is formed on the entire structure including the transistor, and a third interlayer insulating film 47 is thickly formed on the nitride film 46.

In the above, the thickness of the third interlayer insulating film 47 determines the height of the charge storage electrode to be formed later.

Referring to FIG. 2E, the third interlayer insulating film 47 is first etched by an etching process using a mask for the charge storage electrode, and then the nitride film 46 which is subsequently exposed is etched, thereby exposing the source 44. The spacer nitride film 46a is formed at the side of the charge storage electrode hole 48 and the word line 42. The drain 43 is covered by the spacer nitride film 46a and the third interlayer insulating film 47.

Referring to FIG. 2F, after depositing a conductive material for the charge storage electrode on the entire structure including the hole 48 for the charge storage electrode, a sacrificial film (not shown) such as a photoresist is deposited to completely fill the hole 48. In addition, the upper portion of the third interlayer insulating layer 47 is exposed by a chemical mechanical polishing process to form a separate charge storage electrode 49, and the sacrificial layer remaining in the hole 48 is removed. The dielectric film 50 and the plate electrode 51 are sequentially formed on the charge storage electrode 49 to complete the capacitor.

In the semiconductor device manufactured by the method of the present invention described above, two wafers are bonded to form a memory cell. A bit line is formed on a first wafer, and a transistor and a capacitor are formed on a second wafer. As described above, the semiconductor device of the present invention has a vertical structure in which a bit line is formed in a buried structure, a transistor is formed on the buried bit line, and a capacitor is formed on the transistor. Since the capacitor is formed on the transistor, the step difference between the portion where the source and the charge storage electrode are contacted is low, and thus the contact plug process for the charge storage electrode can be omitted. In addition, since the bit lines are formed in a buried structure, the step difference between the peripheral circuit region and the cell region is alleviated to facilitate the subsequent process.

As described above, the present invention forms a bit line on a first wafer, and a transistor and a capacitor on a second wafer, and configures a memory cell in a buried bit line structure in which a bit line and a drain of the transistor are connected. Not only solves the design rule margin between the charge storage electrode and the contact plug, which is one of the problems due to the shrinking of semiconductor devices, but also reduces the gap between the cell area and the peripheral circuit area, thereby realizing the manufacture of memory devices of 4G or more. To be able.

Claims (7)

A transistor consisting of a word line, a drain and a source; A bit line positioned below the transistor and electrically connected to the drain; And And a capacitor positioned on the transistor and electrically connected to the source. The method of claim 1, And the bit line is formed between the first interlayer insulating film and the second interlayer insulating film in the first wafer, and the drain is electrically connected by a bit line contact plug. The method of claim 1, And the transistor and the capacitor are formed on the thinned second wafer. Sequentially forming a first interlayer insulating film, a bit line, and a second interlayer insulating film on the first wafer; Forming a contact plug for a bit line on the second interlayer insulating film; Bonding a second wafer to a surface of a second interlayer insulating film including the contact plug, and then thinning the film; Forming an isolation region on the thinned second wafer to define an active region, and then forming a transistor including a word line, a drain, and a source; Sequentially forming a nitride film and a third interlayer insulating film on the entire structure including the transistor; Sequentially etching the third interlayer insulating film and the nitride film by an etching process using a charge storage electrode mask to form holes for the charge storage electrode to which the source is exposed; And Forming a charge storage electrode connected to the source in a hole for a charge storage electrode, and sequentially forming a dielectric film and a plate electrode on the charge storage electrode. The method of claim 4, wherein The bit line contact plug is formed by forming a contact hole in which the bit line is exposed in the second interlayer insulating layer, and then forming the contact hole by a conductive material deposition and a chemical mechanical polishing process. The method of claim 4, wherein The second wafer is bonded to the first wafer using a bonding technique, and is thinned by polishing by a chemical mechanical polishing process so as to have a thickness electrically connectable with the contact plug by ion implantation for forming the drain. Method of manufacturing a semiconductor device. The method of claim 4, wherein And the drain is electrically connected to a lower contact plug by self alignment by the word line and an active region.