KR20000003928A - Method for manufacturing semiconductor devices - Google Patents
Method for manufacturing semiconductor devices Download PDFInfo
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- KR20000003928A KR20000003928A KR1019980025236A KR19980025236A KR20000003928A KR 20000003928 A KR20000003928 A KR 20000003928A KR 1019980025236 A KR1019980025236 A KR 1019980025236A KR 19980025236 A KR19980025236 A KR 19980025236A KR 20000003928 A KR20000003928 A KR 20000003928A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
Abstract
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 금속배선 형성을 위한 마스크 공정에서 사용된 반사방지막이 금속배선과 턱을 이루며 금속배선 상에 잔류하여 이후의 층간절연막 형성 과정에서 금속배선 측벽에 보이드를 유발하는 문제점을 해결할 수 있는, 반도체 장치 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to the field of semiconductor device manufacturing. In particular, an anti-reflection film used in a mask process for forming metal wires is formed on the metal wires while forming a jaw with the metal wires. The present invention relates to a semiconductor device manufacturing method capable of solving the problem caused.
외부 입자(particle) 또는 수분 등의 침투를 막기 위하여, 금속배선 형성이 완료된 구조 상에 절연막을 형성한다. 상기 절연막으로, 플라즈마 화학기상증착법(plasma enhanced chemical vapor deposition, 이하 PECVD라 함)으로 형성된 산화막 및 질화막을 이용하였으나 매립(gap filling) 특성이 좋지 않아, 최근에는 고밀도 플라즈마 화학기상증착법(high density PECVD, 이하 HDP라 함)으로 형성된 산화막을 이용하고 있다.In order to prevent penetration of external particles or moisture, an insulating film is formed on the structure where the metal wiring is completed. As the insulating film, an oxide film and a nitride film formed by plasma enhanced chemical vapor deposition (PECVD) were used, but the filling property was not good, and recently, high density PECVD, An oxide film formed of HDP hereinafter) is used.
도1은 금속배선 형성이 완료된 기판 상에 PECVD법으로 산화막 및 질화막을 형성한 것을 보이는 종래의 반도체 장치 제조 공정 단면도로서, 반도체 기판(10) 상에 확산방지막인 Ti/TiN막(11), Al막(12) 및 반사방지막인 TiN막(13)을 차례로 증착하고, 상기 TiN막(13), Al막(12) 및 Ti/TiN막(11)을 패터닝하여 금속배선을 형성한 후, 금속배선 형성이 완료된 구조 상에 PECVD법으로 산화막(14) 및 질화막(15)을 형성한 것을 나타내고 있다. 도1에 도시한 바와 같이 PECVD법으로 형성된 산화막(14)은 매립 특성이 좋지 않아 금속배선 사이에 보이드(void)(V1)가 발생하는 문제점이 있다.1 is a cross sectional view of a conventional semiconductor device manufacturing process showing that an oxide film and a nitride film are formed by a PECVD method on a substrate on which metal wiring is completed. The film 12 and the TiN film 13, which is an antireflection film, are sequentially deposited, and the TiN film 13, the Al film 12, and the Ti / TiN film 11 are patterned to form metal wiring, and then metal wiring. The oxide film 14 and the nitride film 15 are formed on the completed structure by PECVD. As shown in FIG. 1, the oxide film 14 formed by PECVD has a problem of voids (V 1 ) occurring between metal wires due to poor embedding characteristics.
도2는 상기와 같은 보이드 발생 문제를 해결하기 위하여, 금속배선 형성이 완료된 기판 상에 고밀도 플라즈마 화학기상증착법(HDP)으로 산화막 및 질화막을 형성한 것을 보이는 종래의 반도체 장치 제조 공정 단면도로서, 반도체 기판(10) 상에 확산방지막인 Ti/TiN막(11), Al막(12) 및 반사방지막인 TiN막(13)을 차례로 증착하고, 상기 TiN막(13), Al막(12) 및 Ti/TiN막(11)을 패터닝하여 금속배선을 형성한 후, 금속배선 형성이 완료된 구조 상에 HDP법으로 산화막(16)을 형성한 것을 나타내고 있다. 도2에 도시한 바와 같이 HDP법으로 형성된 산화막(16)은, PECVD 형성되는 산화막보다 매립 특성이 뛰어나다.FIG. 2 is a cross-sectional view of a conventional semiconductor device manufacturing process showing that an oxide film and a nitride film are formed by high density plasma chemical vapor deposition (HDP) on a substrate on which metal wiring is formed to solve the void generation problem as described above. Ti / TiN film 11 as an anti-diffusion film, an Al film 12 and a TiN film 13 as an anti-reflective film were deposited on (10) in sequence, and the TiN film 13, Al film 12 and Ti / The TiN film 11 is patterned to form metal wiring, and then the oxide film 16 is formed by the HDP method on the structure where the metal wiring is completed. As shown in Fig. 2, the oxide film 16 formed by the HDP method has better embedding characteristics than the oxide film formed by PECVD.
그러나, 반도체 장치의 집적도가 향상됨에 따라, 이웃하는 금속배선간의 공간 또한 감소하여 비교적 집적도가 낮은 반도체 장치 제조 공정에서 발생하지 않았던 문제점이 대두된다. 도3은 그 예를 보이는 종래의 반도체 장치 제조 공정 단면도로서, 반도체 기판(10) 상에 확산방지막인 Ti/TiN막(11), Al막(12) 및 반사방지막인 TiN막(13)을 차례로 증착하고, 상기 TiN막(13), Al막(12) 및 Ti/TiN막(11)을 패터닝하여 금속배선을 형성한 후, 금속배선 형성이 완료된 구조 상에 HDP법으로 산화막(17)을 형성한 것을 나타내고 있다.However, as the degree of integration of semiconductor devices is improved, the space between neighboring metal wirings is also reduced, resulting in a problem that does not occur in a process of manufacturing a semiconductor device having a relatively low degree of integration. 3 is a cross-sectional view of a conventional semiconductor device manufacturing process showing an example, in which a Ti / TiN film 11, a diffusion barrier film, an Al film 12, and a TiN film 13, an antireflection film, are sequentially formed on a semiconductor substrate 10. FIG. After the deposition, the TiN film 13, the Al film 12, and the Ti / TiN film 11 are patterned to form metal wiring, and then the oxide film 17 is formed on the structure where the metal wiring is completed by the HDP method. It is shown.
금속배선 형성을 위한 패터닝 과정에서, Cl2, BCl3및 N2를 사용하여 Al을 식각하기 위한 주식각(main etch) 공정을 실시하고, 금속 잔여물(residue) 및 브릿지(bridge)를 제거하기 위하여 주식각 공정에서 사용된 가스와 동일한 가스로 과도식각(over etch)을 실시한다. Al은 Cl 등의 가스에 의한 화학적인 반응으로 제거되고, TiN은 물리적인 반응에 의해 제거된다. 식각 과정에서 식각마스크로 사용된 감광막 패턴의 가장 자리가 손상되어 드러나 TiN막(13) 측벽에 중합체(polymer)가 증착되어 TiN막(13)이 Al막(12) 상에 탁자의 윗면(table top) 형태로 남게 된다. 즉, Al막(12)의 양단에 돌출된 형태로 TiN막(13)이 잔류하여 턱진 부분(T)이 발생되는데, 이후의 HDP법으로 산화막을 형성하는 과정에서 Al막(12) 패턴의 측벽과 턱진 부분(T)이 이루는 공간에 효과적으로 산화막(17)이 매립되지 못하여 보이드(V2)가 발생한다.In the patterning process for metallization, performing a main etch process for etching Al using Cl 2 , BCl 3 and N 2 , and removing metal residues and bridges In order to overetch the same gas used in the stock angle process. Al is removed by a chemical reaction with a gas such as Cl, and TiN is removed by a physical reaction. The edge of the photoresist pattern used as an etch mask is damaged during the etching process, and polymer is deposited on the sidewall of the TiN film 13 so that the TiN film 13 is placed on the table 12 on the Al film 12. ) Will remain. That is, the TiN film 13 remains in a form protruding at both ends of the Al film 12, so that a jaw portion T is generated. In the process of forming an oxide film by the HDP method, the sidewalls of the Al film 12 pattern And the oxide film 17 may not be effectively buried in the space formed by the jaw portion T and voids V 2 are generated.
상기와 같이 Al막(12) 패턴의 측벽에 보이드(V2)의 발생으로, 이후 수분 등이 침투하게 되어 소자의 특성이 저하되는 문제점이 있다.As described above, due to the generation of voids V 2 on the sidewalls of the Al film 12 pattern, moisture and the like penetrate therein, thereby deteriorating the characteristics of the device.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 금속배선 측벽에 보이드의 발생을 방지할 수 있는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the generation of voids in the metal wiring sidewall.
도1은 금속배선 형성이 완료된 기판 상에 PECVD법으로 산화막 및 질화막을 형성한 것을 보이는 종래의 반도체 장치 제조 공정 단면도1 is a cross-sectional view of a conventional semiconductor device manufacturing process showing that an oxide film and a nitride film are formed on a substrate on which metal wiring formation is completed by PECVD.
도2는 금속배선 형성이 완료된 기판 상에 고밀도 PECVD법으로 산화막을 형성한 것을 보이는 종래의 반도체 장치 제조 공정 단면도2 is a cross-sectional view of a conventional semiconductor device fabrication process showing that an oxide film is formed on a substrate on which metal wiring formation is completed by high density PECVD;
도3은 종래 기술에 따른 고집적 반도체 장치 제조 공정 단면도Figure 3 is a cross-sectional view of the manufacturing process of the highly integrated semiconductor device according to the prior art
도4a 내지 도4d는 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도4A to 4D are cross-sectional views of a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
20: 반도체 기판 21: Ti/TiN막20: semiconductor substrate 21: Ti / TiN film
22: Al막 23: TiN막22: Al film 23: TiN film
24: 질화막 24A: 질화막 스페이서24: nitride film 24A: nitride film spacer
상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 확산방지막, 금속막 및 반사방지막을 차례로 형성하는 제1 단계; 상기 반사방지막, 금속막 및 확산방지막을 선택적으로 식각하여 금속배선을 형성하는 제2 단계; 및 상기 제2 단계에서 상기 금속배선 상부 측면에 발생한 돌출부를 제거하기 위하여, 상기 제2 단계가 완료된 전체 구조 상에 절연막을 형성하고 상기 절연막을 전면식각하여 상기 금속배선 측벽에 절연막 스페이서를 형성하는 제3 단계를 포함하는 반도체 장치 제조 방법을 제공한다.The present invention for achieving the above object is a first step of sequentially forming a diffusion barrier film, a metal film and an antireflection film on a semiconductor substrate; A second step of selectively etching the antireflection film, the metal film, and the diffusion barrier film to form metal wirings; And forming an insulating film on the entire structure in which the second step is completed and forming an insulating film spacer on the sidewall of the metal wire by etching the entire surface of the insulating film to remove the protrusion formed on the upper side of the metal wire in the second step. A semiconductor device manufacturing method comprising three steps is provided.
본 발명은 금속배선을 형성한 후, 금속막 및 반사방지막 측벽에 절연막 스페이서를 형성함으로써, 고집적 반도체 장치 제조 공정의 층간절연막 형성시 금속배선 측벽에 보이드가 발생하는 것을 방지하는 방법이다.The present invention is a method of preventing voids from occurring in the sidewalls of a metal wiring during the formation of an interlayer insulating film in the process of manufacturing a highly integrated semiconductor device by forming the metal wiring and then forming an insulating film spacer on the sidewalls of the metal film and the anti-reflection film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면 도4a 내지 도4d를 참조하여 설명한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Will be explained.
도4a는 반도체 기판(20) 상에 확산방지막인 Ti/TiN막(21), Al막(22) 및 반사방지막인 TiN막(23)을 차례로 증착하고, 상기 TiN막(23), Al막(22) 및 Ti/TiN막(21)을 패터닝하여 금속배선을 형성한 상태를 보이고 있다. 상기 TiN막(23), Al막(22) 및 Ti/TiN막(21)을 TCP(transmission coupled plasma) 또는 ICP(inductively coupled plasma) 방법으로 식각한다.4A shows a Ti / TiN film 21, a diffusion barrier film, an Al film 22, and a TiN film 23, an antireflection film, are sequentially deposited on the semiconductor substrate 20, and the TiN film 23 and the Al film ( 22) and the Ti / TiN film 21 are patterned to form a metal wiring. The TiN film 23, the Al film 22, and the Ti / TiN film 21 are etched by a transmission coupled plasma (TCP) or inductively coupled plasma (ICP) method.
TCP 방식을 이용할 경우 주식각(main etch) 단계에서 200 W 이상의 소오스 전력(source power), 100 W 이상의 바이어스 전력(bias power)을 인가하며, 과도식각(over etch) 단계에서는 250 W 이하의 소오스 전력, 80 W 이상의 바이어스 전력을 인가하고, 주식각 단계 및 과도식각 단계 모두 식각 가스로는 20 sccm 내지 80 sccm의 BCl3및 40 sccm 내지 120 sccm의 Cl2를 공급한다.In the TCP method, a source power of 200 W or more and a bias power of 100 W or more are applied in a main etch step, and a source power of 250 W or less in an over etch step. , A bias power of 80 W or more is applied, and both the stock and transient etching stages supply 20 sccm to 80 sccm of BCl 3 and 40 sccm to 120 sccm of Cl 2 as an etching gas.
도4b는 금속배선 형성이 완료된 반도체 기판(20) 상에 질화막(24)을 증착한 상태를 보이고 있다. 상기 질화막(24)을 대신하여 SiO2막, PSG(phosphosilicate glass)막, SiOxNy막 등의 산화막을 형성할 수도 있다.FIG. 4B shows a state in which the nitride film 24 is deposited on the semiconductor substrate 20 on which metal wiring formation is completed. Instead of the nitride film 24, an oxide film such as a SiO 2 film, a PSG (phosphosilicate glass) film, or a SiO x N y film may be formed.
도4c는 금속배선 측벽에 질화막 스페이서를 형성하기 위하여 질화막(24)을 전면식각하는 상태를 나타내고 있다.FIG. 4C shows a state in which the nitride film 24 is etched entirely to form nitride film spacers on the metal wiring sidewalls.
상기 질화막 전면식각은 Ar 또는 N2를 이용한 스퍼터링(sputtering) 방법으로 실시하며, 스퍼터링시 CHF3가스를 첨가하기도 한다. 또한, 질화막 전면식각은 MERIE(magnetically enhanced reactive ion etching) 방법으로도 이루어질 수도 있다. MERIE 방법을 사용할 경우 주식각 단계에서는 자기장을 50 G 내지 70 G, 전력을 400 W 내지 600 W 인가하고, 주식각 가스로는 70 sccm 내지 80 sccm의 Ar 가스와 10 sccm 내지 20 sccm의 CHF3가스를 사용하며, 과도식각 단계에서는 자기장을 주식각 단계와 동일하게 유지하고, 전력을 700 W 내지 900 W 인가하고, 식각 가스로는 90 sccm 내지 100 sccm의 Ar 가스와 0 sccm 내지 5 sccm의 CHF3가스를 사용한다.The nitride layer front surface etching is performed by a sputtering method using Ar or N 2 , and CHF 3 gas may be added during sputtering. In addition, the nitride film front surface etching may also be performed by a magnetically enhanced reactive ion etching (MERIE) method. In the case of the MERIE method, the magnetic field is applied at 50 G to 70 G and the electric power is 400 W to 600 W at the stock angle, and the stock gas has 70 to 60 sccm of Ar gas and 10 to 20 sccm of CHF 3 In the transient etching step, the magnetic field is kept the same as the stock angle step, and the power is applied to 700 W to 900 W, and the etching gas is 90 sccm to 100 sccm Ar gas and 0 sccm to 5 sccm CHF 3 gas. use.
도4d는 상기와 같은 전면식각으로 금속배선 측벽에 질화막 스페이서(24A)를 형성함으로써 금속배선 상부 측벽에 발생한 돌출부가 제거된 상태를 보이고 있다.FIG. 4D shows a state in which the protrusions formed on the upper sidewalls of the metal wirings are removed by forming the nitride film spacers 24A on the sidewalls of the metal wirings by the above etching.
이후, 층간절연막 형성시 상기 질화막 스페이서(24A)에 의해 금속배선 측벽에 보이드가 발생하지 않는다.Thereafter, voids are not generated in the metal wiring sidewalls by the nitride film spacer 24A when the interlayer insulating film is formed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 고집적 반도체 장치 제조 공정에서 금속배선 측벽에 발생하는 보이드의 발생을 억제하여 보이드로 인한 소자 특성 저하를 방지할 수 있다.According to the present invention as described above, it is possible to suppress the generation of voids generated in the sidewall of the metal wiring in the manufacturing process of the highly integrated semiconductor device, thereby preventing deterioration of device characteristics due to the voids.
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