US20010009248A1 - Metal etching process - Google Patents

Metal etching process Download PDF

Info

Publication number
US20010009248A1
US20010009248A1 US09/815,752 US81575201A US2001009248A1 US 20010009248 A1 US20010009248 A1 US 20010009248A1 US 81575201 A US81575201 A US 81575201A US 2001009248 A1 US2001009248 A1 US 2001009248A1
Authority
US
United States
Prior art keywords
layer
metal
etching
etching process
process according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/815,752
Inventor
Wen-Pin Kuo
Yueh-Feng Ho
Jy-Hwang Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/815,752 priority Critical patent/US20010009248A1/en
Publication of US20010009248A1 publication Critical patent/US20010009248A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B44—DECORATIVE ARTS
    • B44C—PRODUCING DECORATIVE EFFECTS; MOSAICS; TARSIA WORK; PAPERHANGING
    • B44C1/00—Processes, not specifically provided for elsewhere, for producing decorative surface effects
    • B44C1/22—Removing surface-material, e.g. by engraving, by etching
    • B44C1/227—Removing surface-material, e.g. by engraving, by etching by etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Definitions

  • the present invention relates to a method of metal etching process. More particularly, the present invention relates to a method of preventing from resulting an I-shape profile of a metal after being etched.
  • Another conventional to resolve the problem of the increased contact resistance described as above includes using performing a high density plasma (HDP) etching step on the oxide layer to form the opening for the via or contact.
  • HDP high density plasma
  • the high density plasma etching step has a corner cutting function whenever a corner of the anti-reflection layer is formed.
  • the oxide layer deposited on the sidewall of the aluminum layer is easily removed.
  • a conductive material to fill the opening in the subsequent process is therefore highly conductive to the exposed aluminum layer.
  • the high density plasma etcher is very expensive, so that the cost of the etching process is high.
  • the invention provides a metal etching process.
  • a substrate comprising a glue/barrier layer, a metal layer and an anti-reflection layer is provided.
  • a three-stage etching step is performed. The first stage comprises a break through etching step to pattern the glue/barrier layer.
  • a main etching step is performed on the metal layer with chlorine (Cl 2 ), boron trichloride (BCl 3 ) and trifluoro-methane (CHF 3 ) as etching gases. The profile of the metal layer thus appears atilt.
  • an over etching step is performed.
  • the invention provides a method for etching a metal layer.
  • the metal layer may be formed of material such as aluminum or aluminum alloy.
  • the flow rate of chloride is controlled between about 70 to about 100 sccm, while the flow rates of boron trichloride and trifluoro-methane are at about 40 to about 60 sccm and no larger than 10 sccm. respectively.
  • the pressure, source power, bias of the main etching are controlled at about 10-15 mtorr, 800-1200 W and 100-200 W.
  • chlorine is used as the etching gas first with a flow rate of about 50-150 sccm.
  • the operating pressure, source power and bias are at about 12-18 mtorr, 1500-2000 W and within about 50 W, respectively.
  • the main etching step is then continued with chlorine, boron trichloride, trifluoro-methane as etching gases having flow rates of about 40-80 sccm, while the operating pressure, source power and bias are controlled at about 6-10 mtorr, 600-800 W and 100-200 W.
  • chlorine and boron trichloride are used as etching gases with flow rates controlled at about 50-70 sccm and 40-60 sccm.
  • the operation conditions of the over etching step comprise a pressure of about 10-15 mtorr, a power of about 800-1200 W and a bias of about 100-150 W.
  • polymer is produced during the etching step.
  • the polymer is adsorbed on a surface of the metal layer to avoid from inwardly recessing the metal layer during the over etching step.
  • a tilt sidewall of the metal layer is resulted after being etched.
  • the width of the metal layer is thus no narrower than the width of the anti-reflection layer.
  • the tilt profile of the metal layer is advantageous to the subsequent process for forming contact or via opening and plug.
  • FIG. 1A to FIG. 1C shows a preferred embodiment of etching a metal layer according to the invention.
  • a substrate 100 is provided.
  • the substrate 100 comprises, for example, a silicon substrate having devices such as a metal-oxide semiconductor transistor or components (not shown) formed thereon.
  • a glue/barrier layer 102 for example, a titanium nitride layer or a stack of titanium/titanium nitride, is formed on the substrate 100 .
  • a metal layer 104 such as a layer of aluminum or aluminum alloy is formed on the glue/barrier layer 102 .
  • An anti-reflection layer 106 for example, a silicon oxy-nitride layer/titanium nitride layer, is formed on the metal layer 104 .
  • a patterned photo-resist layer 108 is formed on the anti-reflection layer 106 .
  • a three-stage etching step is performed to for conductive wires.
  • a break through etching step is performed on the anti-reflection layer 106 .
  • a second stage includes a main etching step to strip off a part of the metal layer 104 .
  • a third stage includes an over etching step to remove a part of the glue/barrier layer 102 to ensure an isolation between neighboring conductive wires. After being etched, the remaining glue/barrier layer, metal layer and anti-reflection layer are denoted as 102 a , 104 a and 106 a.
  • the first stage of the etching step that is, the break through etching step
  • chlorine is used to etch silicon oxy-nitride if the anti-reflection layer 106 a is made of silicon oxy-nitride/titanium nitride.
  • the flow rate is controlled at about 50-150 sccm.
  • the pressure of reacting chamber is at about 12-18 mtorr. while a source power of about 1500-2000 W and a bias within about 50 W are applied.
  • the titanium nitride is then etched using a mixture of etching gases comprising chlorine boron chloride and trifluoro-methane with flow rates of about 40-80 sccm.
  • a source power of about 600-800 W and a bias of about 100-200 W are applied to the reaction chamber with a operating pressure of about 6-10 mtorr.
  • etching gases including chlorine, boron trichloride and trifluoro-methane are used with flow rates of about 70-100. 40-60 and within 10 sccm, respectively.
  • the reaction chamber is controlled to have an operating pressure, a source power and a bias power of about 10-15 mtorr, 800-1200 W and 100-200 W. respectively.
  • polymer is produced with the introduction of tri-fluoride methane.
  • the polymer is adsorbed on an exposed surface of the metal layer 104 a .
  • the recess caused by the conventional method on a sidewall of the metal layer is thus avoided.
  • the remaining metal layer 104 a has a sloped sidewall and a profile of gradually widening from a top surface to a bottom surface thereof. That is, the top surface adjacent to the remaining anti-reflection layer 102 a having a cross section smaller than the bottom surface adjacent to the glue/barrier layer 102 a .
  • the remaining metal layer 104 a thus has the sloped sidewall outstanding the anti-refelction layer laterally.
  • Chlorine and boron trichloride are used as etching gases in the third stage of the etching, that is, the over etching step.
  • the chlorine has a flow rate controlled at about 50 to about 70 sccm, while the boron trichloride has an etching rate of about 40 to about 60 sccm.
  • the reacting chamber to perform the over etching step is controlled with an operation pressure, a source power and a bias of about 10-15 mtorr, 800-1200 W and 100-150 W.
  • FIG. 1C the photo-resist layer 108 is removed.
  • An insulation layer 110 is formed to cover the substrate 100 and a conductive wire concluding the glue/barrier layer 102 a , the metal layer 104 a and the anti-reflection layer 106 a .
  • the formation of the insulation layer 110 is to ensure insulation from other conductive wire formed on the substrate 100 .
  • a contact opening 111 is formed in the insulation layer 110 to expose at least a part of the conductive wire.
  • the metal layer 104 a as well as the anti-reflection layer 104 a are to be exposed to achieve an electrical connection.
  • the metal layer 104 a can be exposed easily as required due to the sloped sidewall.

Abstract

A metal etching process. A glue/barrier layer, a metal layer and an anti-refeletion layer are formed on a substrate. A three-stage etching step is performed. A break through step of etching is performed to pattern the glue/barrier layer. A main etching step is performed on the metal layer with chlorine, boron trichloride, and trifluoro-methane as etching gases. The trifluoro-methane is advantageous to produce a polymer during etching, so that the profile of the metal layer appears atilt. An over-etching step is then performed to ensure an insulation between neighboring wiring lines.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention [0001]
  • The present invention relates to a method of metal etching process. More particularly, the present invention relates to a method of preventing from resulting an I-shape profile of a metal after being etched. [0002]
  • 2. Description of Related Art [0003]
  • In a conventional method for forming a wiring line, due to the different rates between an anti-reflection layer, aluminum layer and glue/barrier layer, a surface of the aluminum layer is often indented inwardly while the aluminum layer is etched after the anti-reflection layer. The inward indent result in an I-shape profile of the aluminum layer, that is, the resultant width of the anti-reflection layer is larger than that of the aluminum layer. In the subsequent etching process for forming an unlanded contact or via, an oxide layer deposited adjacent to a sidewall of the aluminum layer is difficult to remove, so as to induce a shield of the aluminum layer. The shield of the aluminum layer would further cause the formation of an oxide spacer between the glue/barrier layer and a metal layer formed afterwards. As a consequence, the contact resistance of the wiring line is greatly increase to affect the performance of the whole circuit seriously. [0004]
  • Another conventional to resolve the problem of the increased contact resistance described as above includes using performing a high density plasma (HDP) etching step on the oxide layer to form the opening for the via or contact. When the anti-reflection layer is exposed in the opening, the high density plasma etching step has a corner cutting function whenever a corner of the anti-reflection layer is formed. Thus, the oxide layer deposited on the sidewall of the aluminum layer is easily removed. A conductive material to fill the opening in the subsequent process is therefore highly conductive to the exposed aluminum layer. However, the high density plasma etcher is very expensive, so that the cost of the etching process is high. [0005]
    • SUMMARY OF THE INVENTION
  • The invention provides a metal etching process. A substrate comprising a glue/barrier layer, a metal layer and an anti-reflection layer is provided. A three-stage etching step is performed. The first stage comprises a break through etching step to pattern the glue/barrier layer. In the second stage, a main etching step is performed on the metal layer with chlorine (Cl[0006] 2), boron trichloride (BCl3) and trifluoro-methane (CHF3) as etching gases. The profile of the metal layer thus appears atilt. In the third stage, an over etching step is performed.
  • As embodied and broadly described herein, the invention provides a method for etching a metal layer. The metal layer may be formed of material such as aluminum or aluminum alloy. In the main etching step, the flow rate of chloride is controlled between about 70 to about 100 sccm, while the flow rates of boron trichloride and trifluoro-methane are at about 40 to about 60 sccm and no larger than 10 sccm. respectively. The pressure, source power, bias of the main etching are controlled at about 10-15 mtorr, 800-1200 W and 100-200 W. For the break through etching step, chlorine is used as the etching gas first with a flow rate of about 50-150 sccm. The operating pressure, source power and bias are at about 12-18 mtorr, 1500-2000 W and within about 50 W, respectively. The main etching step is then continued with chlorine, boron trichloride, trifluoro-methane as etching gases having flow rates of about 40-80 sccm, while the operating pressure, source power and bias are controlled at about 6-10 mtorr, 600-800 W and 100-200 W. In the over etching step, chlorine and boron trichloride are used as etching gases with flow rates controlled at about 50-70 sccm and 40-60 sccm. The operation conditions of the over etching step comprise a pressure of about 10-15 mtorr, a power of about 800-1200 W and a bias of about 100-150 W. [0007]
  • With the introduction of trifluoride methane, polymer is produced during the etching step. The polymer is adsorbed on a surface of the metal layer to avoid from inwardly recessing the metal layer during the over etching step. On the contrary, a tilt sidewall of the metal layer is resulted after being etched. The width of the metal layer is thus no narrower than the width of the anti-reflection layer. The tilt profile of the metal layer is advantageous to the subsequent process for forming contact or via opening and plug. [0008]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. [0009]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0010]
  • FIG. 1A to FIG. 1C shows a preferred embodiment of etching a metal layer according to the invention. [0011]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In FIG. 1C, a [0012] substrate 100 is provided. The substrate 100 comprises, for example, a silicon substrate having devices such as a metal-oxide semiconductor transistor or components (not shown) formed thereon. A glue/barrier layer 102, for example, a titanium nitride layer or a stack of titanium/titanium nitride, is formed on the substrate 100. A metal layer 104 such as a layer of aluminum or aluminum alloy is formed on the glue/barrier layer 102. An anti-reflection layer 106, for example, a silicon oxy-nitride layer/titanium nitride layer, is formed on the metal layer 104.
  • In FIG. 1B, a patterned photo-[0013] resist layer 108 is formed on the anti-reflection layer 106. Using the photo-resist layer 108 as a mask, a three-stage etching step is performed to for conductive wires. In a first stage, a break through etching step is performed on the anti-reflection layer 106. A second stage includes a main etching step to strip off a part of the metal layer 104. A third stage includes an over etching step to remove a part of the glue/barrier layer 102 to ensure an isolation between neighboring conductive wires. After being etched, the remaining glue/barrier layer, metal layer and anti-reflection layer are denoted as 102 a, 104 a and 106 a.
  • In the first stage of the etching step, that is, the break through etching step, chlorine is used to etch silicon oxy-nitride if the [0014] anti-reflection layer 106 a is made of silicon oxy-nitride/titanium nitride. The flow rate is controlled at about 50-150 sccm. The pressure of reacting chamber is at about 12-18 mtorr. while a source power of about 1500-2000 W and a bias within about 50 W are applied. The titanium nitride is then etched using a mixture of etching gases comprising chlorine boron chloride and trifluoro-methane with flow rates of about 40-80 sccm. A source power of about 600-800 W and a bias of about 100-200 W are applied to the reaction chamber with a operating pressure of about 6-10 mtorr.
  • In the second stage of the etching step, that is, the main etching step, to etch a metal layer made of aluminum or aluminum alloy, etching gases including chlorine, boron trichloride and trifluoro-methane are used with flow rates of about 70-100. 40-60 and within 10 sccm, respectively. The reaction chamber is controlled to have an operating pressure, a source power and a bias power of about 10-15 mtorr, 800-1200 W and 100-200 W. respectively. [0015]
  • In the main etching stage, polymer is produced with the introduction of tri-fluoride methane. The polymer is adsorbed on an exposed surface of the [0016] metal layer 104 a. The recess caused by the conventional method on a sidewall of the metal layer is thus avoided. In contrast, the remaining metal layer 104 a has a sloped sidewall and a profile of gradually widening from a top surface to a bottom surface thereof. That is, the top surface adjacent to the remaining anti-reflection layer 102 a having a cross section smaller than the bottom surface adjacent to the glue/barrier layer 102 a. The remaining metal layer 104 a thus has the sloped sidewall outstanding the anti-refelction layer laterally.
  • Chlorine and boron trichloride are used as etching gases in the third stage of the etching, that is, the over etching step. The chlorine has a flow rate controlled at about 50 to about 70 sccm, while the boron trichloride has an etching rate of about 40 to about 60 sccm. The reacting chamber to perform the over etching step is controlled with an operation pressure, a source power and a bias of about 10-15 mtorr, 800-1200 W and 100-150 W. [0017]
  • In FIG. 1C, the photo-resist [0018] layer 108 is removed. An insulation layer 110 is formed to cover the substrate 100 and a conductive wire concluding the glue/barrier layer 102 a, the metal layer 104 a and the anti-reflection layer 106 a. The formation of the insulation layer 110 is to ensure insulation from other conductive wire formed on the substrate 100. A contact opening 111 is formed in the insulation layer 110 to expose at least a part of the conductive wire. In certain circumstance, the metal layer 104 a as well as the anti-reflection layer 104 a are to be exposed to achieve an electrical connection. As shown in FIG. 1C, the metal layer 104 a can be exposed easily as required due to the sloped sidewall. Thus, in a subsequent process for filling the opening 112 with a plug, a good contact between the plug and the metal layer 104 a is achieved. Consequently, the conductive performance of the devices is highly upgraded.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0019]

Claims (21)

What is claimed is:
1. A metal etching process, comprising:
providing a substrate comprising a glue/barrier layer on the substrate, a metal layer on the glue/barrier layer and an anti-reflection layer on the metal layer: and
patterning the anti-reflection layer, the metal layer and the glue,/barrier layer to result in a sloped sidewall of the metal layer which has a larger top surface adjacent to the anti-reflection layer and a smaller bottom surface adjacent to the glue/barrier layer.
2. The metal etching process according to
claim 1
, wherein the anti-reflection layer comprises a silicon oxy-nitride/titanium nitride layer.
3. The metal etching process according to
claim 2
, wherein the anti-reflection layer is patterned by etching the silicon oxy-nitride with chlorine as an etching gas and etching the titanium nitride chlorine with a mixture of chlorine, boron trichloride and trifluoro-methane as etching gas.
4. The metal etching process according to
claim 3
, wherein the etching gas of chloride has a flow rate of about 50-150 sccm, while chlorine, boron trichloride and trifluoro-methane of the mixture each has a flow rate of about 40-80 sccm.
5. The metal etching process according to
claim 3
, wherein the silicon oxy-nitride is etched with conditions of an operation pressure at about 12-18 mtorr, a source power of about 1500-2000 W, and a bias within a range of 50 W.
6. The metal etching process according to
claim 3
, wherein the titanium nitride is etched with conditions of an operation pressure at about 6-10 mtorr, a source power of about 600-800 W, and a bias within at about 100-200 W.
7. The metal etching process according to
claim 1
, wherein the metal layer comprises a layer of aluminum or aluminum alloy.
8. The metal etching process according to
claim 7
, wherein the metal layer is patterned by an etching step with a mixture of chlorine, boron trichloride and trifluoromethane as an etching gas.
9. The metal etching process according to
claim 8
, wherein flow rates of chlorine, boron-trichloride and trifluoro-methane are controlled at about 70-100 sccm. 40-60 sccm and less than or equal to 10 sccm, respectively.
10. The metal etching process according to
claim 8
, wherein the etching step is controlled with a pressure of about 10-15 mtorr, a source power of about 800-1200 W and a bias of about 100-200 W.
11. The metal etching process according to
claim 8
, wherein an over etching step is further performed on the metal layer and the glue/barrier layer after the etching the metal layer with a mixture of chlorine and boron trichloride as an etching gas.
12. The metal etching process according to
claim 11
, wherein flow rates of chlorine and boron trichloride are controlled at about 50-70 sccm and 40-60 sccm, respectively.
13. The metal etching process according to
claim 11
, wherein the over etching step is performed in a reaction chamber having a pressure of about 10-15 mtorr and applied with a source power of about 800-1200 W and a bias of about 100-150 W.
14. The metal etching process according to
claim 1
, comprising further the steps of:
forming an insulation layer on the substrate and covering the anti-reflection layer, the metal layer and the glue/barrier layer; and
forming an opening in the insulation layer to expose at least a part of the anti-reflection layer and the metal layer.
15. A metal etching process, comprising:
providing a substrate having a metal layer covered by an anti-reflection layer thereon;
performing a break through etching step on the anti-reflection layer, performing a main etching step on the metal layer, wherein a polymer is produced and adsorbed by a surface of the metal layer wherever is exposed during the main etching step; and
performing an over etching step.
16. The metal etching process according to
claim 15
, wherein the metal layer is formed of aluminum or aluminum alloy.
17. The metal etching process according to
claim 16
, wherein trifluoromethane is used for the main etching step, so that the polymer is produced to cover the exposed surface of the metal layer during the main etching step.
18. The metal etching process according to
claim 15
, comprising further the steps of:
forming an insulation layer on the substrate and covering the anti-reflection layer, the metal layer; and
forming an opening in the insulation layer to expose at least a part of the anti-reflection layer and the metal layer.
19. A metal etching process, comprising:
providing a substrate having a metal layer thereon and an anti-reflection layer on the metal layer:
performing a three-stage etching process on the metal layer and the anti-reflection layer to form a conductive wire, the three-stage etching process further comprising:
performing a first etching step on the anti-reflection layer;
performing a main etching step on the metal layer with an etching gas which produces a polymer covering an exposed surface of the metal layer during the main etching step; and
performing an over etching step without using the etching gas which produces the polymer;
forming an insulation layer to cover the substrate and the conductive wire: and
forming an opening filled exposing a part of the conductive wire.
20. The metal etching process according to
claim 18
, wherein the conductive wire comprising the etched metal layer with a gradually widening profile from a top surface towards a bottom surface thereof.
21. The metal etching process according to
claim 18
, wherein the etched metal layer has a sloped sidewall outstanding the anti-reflection layer in lateral direction.
US09/815,752 1999-06-04 2001-03-23 Metal etching process Abandoned US20010009248A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/815,752 US20010009248A1 (en) 1999-06-04 2001-03-23 Metal etching process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32638099A 1999-06-04 1999-06-04
US09/815,752 US20010009248A1 (en) 1999-06-04 2001-03-23 Metal etching process

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US32638099A Division 1999-06-04 1999-06-04

Publications (1)

Publication Number Publication Date
US20010009248A1 true US20010009248A1 (en) 2001-07-26

Family

ID=23271964

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/815,801 Abandoned US20010009249A1 (en) 1999-06-04 2001-03-23 Metal etching process
US09/815,752 Abandoned US20010009248A1 (en) 1999-06-04 2001-03-23 Metal etching process

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/815,801 Abandoned US20010009249A1 (en) 1999-06-04 2001-03-23 Metal etching process

Country Status (1)

Country Link
US (2) US20010009249A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI243404B (en) * 2001-05-24 2005-11-11 Lam Res Corp Applications of oxide hardmasking in metal dry etch processors

Also Published As

Publication number Publication date
US20010009249A1 (en) 2001-07-26

Similar Documents

Publication Publication Date Title
US7615494B2 (en) Method for fabricating semiconductor device including plug
KR0126801B1 (en) Metalizing method of semiconductor device
US5990020A (en) Method for forming a conductive plug
CN113053805B (en) Semiconductor structure forming method and semiconductor structure
US7557038B2 (en) Method for fabricating self-aligned contact hole
US6399483B1 (en) Method for improving faceting effect in dual damascene process
JP2003197775A (en) Method for manufacturing semiconductor element
US20010009248A1 (en) Metal etching process
CN101295665A (en) Horn shaped contact production method
US6452277B1 (en) Semiconductor device and manufacturing method thereof
CN114446931A (en) Transistor structure with air gap and manufacturing method thereof
KR100681267B1 (en) Method for forming contact in semiconductor processing
US6586324B2 (en) Method of forming interconnects
KR20000002719A (en) Semiconductor device production method to improve contact resistance of silicide
KR100835506B1 (en) Manufacturing method of semiconductor device
KR20040038049A (en) Method of forming contact in semiconductor device
KR100643484B1 (en) method for manufacturing semiconductor devices
KR100245306B1 (en) Method for forming multi metal interconnection layer of semiconductor device
KR100338115B1 (en) Method for forming metal film in semiconductor device
KR100390815B1 (en) A forming method of gate electrode
KR100548564B1 (en) method for forming bit line
JP2003023075A (en) Manufacturing method for semiconductor device
KR100396697B1 (en) Method for Fabricating of Semiconductor Device
KR20040001478A (en) Method of forming metal wiring
KR20050023982A (en) Method of forming metal contact

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION