KR19990035304A - Manufacturing method of thin film type optical path control device - Google Patents

Abstract

Disclosed is a method of manufacturing a thin film type optical path control apparatus capable of improving the planarization rate of a sacrificial layer. After forming a second protective layer on top of an active matrix in which M x N (M, N is an integer) embedded therein, the second protective layer is planarized by a chemical mechanical polishing (CMP) method. After forming a sacrificial layer using polysilicon on the second protective layer, an actuator including a support layer, a lower electrode, a strain layer, and an upper electrode is formed on the sacrificial layer. After forming a mirror on top of the support layer, the sacrificial layer is removed using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ). By planarizing the surface of the second protective layer, it is possible to compensate for the step resulting from the active matrix to improve the planarization rate of the sacrificial layer removed in a subsequent process. In addition, it is possible to ensure the remaining thickness uniformity of the sacrificial layer formed on the active matrix as a whole.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control device using an Actuated Mirror Array (AMA), and more particularly, to a planarization rate of a thin film type optical path control device that can improve the planarization rate of a sacrificial layer by compensating for a step resulting from an active matrix. It relates to a manufacturing method.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode therein into an active matrix in which a transistor is built, and then processing by using a sawing method and installing a mirror on the top. . However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is a patent application No. 96-42197 filed by the applicant of the Korean Patent Office on September 24, 1996 (name of the invention: thin film type optical path control device that can control the stress of the membrane and its manufacturing method) Is disclosed.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the preceding application.

First, the structure of the thin film type optical path control device is as follows.

The thin film type optical path control device includes an active matrix 1 and an actuator 60. The active matrix 1 in which M x N (M, N is an integer) MOS transistors and a drain pad 5 extending from the drain region of the MOS transistor is formed in the active matrix 1 and the drain. The protective layer 10 is stacked on the pad 5 and the etch stop layer 15 is stacked on the protective layer.

The actuator 60 has a side in contact with a portion of the etch stop layer 15 in which the drain pad 5 is formed, and the other side is a membrane stacked horizontally with the lower portion of the active matrix 1 through the air gap 25. 30, the lower electrode 35 stacked on the membrane, the strained layer 40 stacked on the lower electrode, the upper electrode 45 stacked on the strained layer, and one side of the strained layer 40. The lower electrode 35 and the drain in the via hole 50 formed perpendicularly to the drain pad 5 through the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. The pad 5 includes a via contact 55 formed to be connected to each other.

A stripe 46 is formed on a part of the upper electrode 45. The stripe 46 operates the upper electrode 45 uniformly so that the light incident from the light source is diffusely reflected at the boundary between the portion of the upper electrode 45 which is deformed and the portion which is not deformed according to the deformation of the deforming layer 40. prevent.

Hereinafter, the manufacturing method of the said thin film type optical path control apparatus is demonstrated.

Referring to FIG. 1A, an active wafer is formed of an n-type doped silicon wafer, in which M × N (M, N is an integer) P-MOS transistors are formed and a drain pad 5 extending from the drain region of the transistor is formed. A protective layer 10 is formed on the matrix 1 using phosphorus silicate glass PSG. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded during subsequent processing.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched and damaged during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 µm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the MOS transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby forming a support of the actuator 60.

The membrane 30 is stacked on the exposed etch stop layer 15 and the sacrificial layer 20. The membrane 30 is formed by depositing nitride to a thickness of about 0.01 to 1.0 mu m using a low pressure chemical vapor deposition (LPCVD) method.

The lower electrode 35 is stacked on top of the membrane 30. The lower electrode 35 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). Subsequently, the lower electrode 35 is separated for each pixel through a photolithography process so that an independent first signal (image signal) is applied to each pixel (Iso-Cut process). The first signal is applied to the lower electrode 35 through a transistor built in the active matrix 1 from the outside.

A deformation layer 40 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode 35. The strained layer 40 is formed to have a thickness of 0.1 to 1.0 탆 using a sol-gel method, a sputtering method, or a chemical vapor deposition method. Preferably, the strained layer 40 is formed so that PZT has a thickness of about 0.4 µm using the sol-gel method. In addition, the piezoelectric material constituting the strained layer 40 is subjected to heat treatment by a rapid heat treatment (RTA) method to cause phase shift. In the strained layer 40, a second signal (bias signal) is applied to the upper electrode 45, and a first signal is applied to the lower electrode 35, according to a potential difference between the upper electrode 45 and the lower electrode 35. It is deformed by the generated electric field.

The upper electrode 45 is stacked on the deformation layer 40. The upper electrode 45 is formed so as to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. Since the upper electrode 45 has both electrical conductivity and reflectivity at the same time, the upper electrode 45 functions not only as a bias electrode for generating an electric field but also as a mirror for reflecting incident light.

Referring to FIG. 1B, the upper electrode 45, the deformation layer 40, and the lower electrode 35 are sequentially patterned from a top of the upper electrode 45 into a predetermined pixel shape. At this time, a portion of the upper electrode 45 is formed with a stripe 46 to uniformly operate the upper electrode 45 to prevent diffuse reflection of light incident from the light source.

Subsequently, the via hole 50 is etched by sequentially etching the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 from one side of the strained layer 40. Form. Thus, the via hole 50 is formed from one side of the strained layer 40 to the drain pad 5. Subsequently, a metal having electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form the via contact 55. The via contact 55 connects the drain pad 5 and the lower electrode 35. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. Then, the membrane 30 is patterned into a predetermined pixel shape.

Subsequently, the sacrificial layer 20 is etched using hydrogen fluoride (HF) vapor to form an air gap 25 at the position of the sacrificial layer 20, and then a rinse and dry treatment is performed. To complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. At the same time, a second signal is applied to the upper electrode 45 to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the electric field, and the actuator 60 including the strained layer 40 is bent upward at a predetermined angle. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

However, according to the manufacturing method of the thin film type optical path control apparatus described above, after the sacrificial layer is deposited to a sufficient thickness on the etch stop layer, the sacrificial layer is planarized by a chemical mechanical polishing (CMP) process. However, according to the above method, since it is difficult to accurately predict the remaining thickness of the sacrificial layer after performing the CMP process, it is difficult to accurately adjust the thickness of the sacrificial layer in the entire module. Furthermore, the sacrificial layer may not sufficiently achieve flattening of the uneven portion on the active matrix, and the unevenness of the lower layer may appear on the surface of the upper electrode serving as a mirror, resulting in an irregular surface or an inferior level of the upper electrode. There is this.

Accordingly, it is an object of the present invention to form a second protective layer, polish and planarize the surface of the second protective layer, and then form a sacrificial layer using polysilicon thereon to compensate for the steps resulting from the active matrix. The present invention provides a method for manufacturing a thin film type optical path control apparatus capable of improving the planarization rate of a sacrificial layer.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

2 is a plan view of a thin film type optical path control apparatus according to the present invention.

3 is a cross-sectional view of the device shown in FIG. 2 taken along line A′A ′.

4A and 4F are manufacturing process diagrams of the apparatus shown in FIG.

<Explanation of symbols for main parts of the drawings>

100: active matrix 105: first metal layer

110: first protective layer 115: second metal layer

120: second protective layer 125: antioxidant layer

130: sacrificial layer 135: support layer

140: lower electrode 150: strained layer

155: upper electrode 160: via hole

165: beer contact 170: mirror

175: air gap 200: actuator

In order to achieve the above object, the present invention provides a method comprising: providing an active matrix including a drain pad having M x N (M, N is an integer) embedded therein and extending from the drain of the MOS transistor; Forming a second passivation layer on the active matrix; Planarizing the second protective layer by a chemical mechanical polishing (CMP) method; Forming a sacrificial layer using polysilicon on the second protective layer; Forming an actuator on the sacrificial layer, the actuator including a support layer, a lower electrode, a strain layer, and an upper electrode; Forming a mirror on top of the support layer; And removing the sacrificial layer using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ).

According to the manufacturing method of the thin film type optical path control apparatus which concerns on this invention, the 2nd protective layer is formed in the thickness of the level which can planarize the level | step difference of an underlayer on the active matrix. The second protective layer may be polished by chemical mechanical polishing (CMP) to obtain a flat surface. After the planarization of the second protective layer is performed, a sacrificial layer is formed using polysilicon to form an air gap. Therefore, since the planarization process is performed in the second passivation layer, the process of planarizing the sacrificial layer is not necessary. In addition, since the sacrificial layer is formed on the planarized second protective layer, the remaining thickness of the sacrificial layer can be easily predicted, and the overall residual thickness uniformity of the sacrificial layer formed on the active matrix can be secured.

Furthermore, the second protective layer remaining after the planarization process simultaneously performs the function of the anti-etching layer protecting the lower layers during the subsequent etching process of the sacrificial layer, thereby shortening the manufacturing process.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

FIG. 2 is a plan view of a thin film type optical path adjusting device according to the present invention, and FIG. 3 is a cross-sectional view taken along line A′A ′ of the apparatus shown in FIG. 2.

2 and 3, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 200, and a mirror 170.

The active matrix 100 having M × N (M, N is an integer) embedded therein is formed on the first metal layer 105 and the first metal layer 105 extending from the source and drain of the MOS transistor. The first protective layer 110 is formed, the second metal layer 115 formed on the first protective layer 110, and the second protective layer 120 formed on the second metal layer 115 are included. Preferably, the antioxidant layer 125 may be formed on the second protective layer 120. The first metal layer 105 includes a drain pad extending from the drain of the MOS transistor, and the second metal layer 115 includes a titanium (Ti) layer and a titanium nitride (TiN) layer.

Referring to FIG. 3, one side of the actuator 200 is in contact with a portion in which the drain pad of the first metal layer 105 is formed, and the other side of the actuator 200 is disposed through the air gap 175. The support layer 135 formed horizontally below the active matrix 100, the lower electrode 140 formed on the support layer 135, the strained layer 150 formed on the lower electrode 140, and the strained layer 150. An upper electrode 155 formed on an upper portion of the upper electrode 155, and a strained layer 150, a lower electrode 140, a support layer 135, a second protective layer 120, and a first protective layer from one side of the strained layer 150. The via contact 160 includes a via contact 165 formed to connect the lower electrode 140 and the drain pad to the via hole 160 formed vertically through the 110 to the drain pad of the first metal layer 105. The support layer 135 functions as a membrane of the thin film type optical path adjusting device described in the previous application.

The support layer 135 has a shape in which a rectangular flat plate is integrally formed with the arms on the same plane between two rectangular arms formed in parallel from both support portions. The mirror 170 is formed on the rectangular flat plate of the support layer 135. Thus, the mirror 170 has the shape of a rectangular flat plate.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

4A to 4F show a manufacturing process diagram of the thin film type optical path control device according to the present invention.

Referring to FIG. 4A, after preparing an active matrix 100, which is an n-type doped silicon (Si) wafer, the active matrix 100 is prepared by using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). ) To form an isolation layer for dividing the active region and the field region. Subsequently, a gate made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source and drain are formed by an ion implantation process, thereby forming M x N (M and N are integers). MOS transistors are formed.

After forming an insulating film made of an oxide on the resultant formed MOS transistor, the openings for exposing the top of one side of the source and the drain are formed by a photolithography process. Subsequently, a first metal layer 105 made of a metal such as titanium, titanium nitride, or tungsten (W) is deposited to have a thickness of about 7000 to 8000 kPa on the upper portion of the resultant product in which the openings are formed, and then the first metal layer 105 is deposited. Is patterned by a photolithography process. The patterned first metal layer 105 includes a drain pad extending from the drain of the MOS transistor to one side of the support of the actuator 200.

The first passivation layer 110 is formed on the first metal layer 105. The first passivation layer 110 is formed to have a thickness of about 8000 GPa by using the silicate glass (PSG) chemical vapor deposition (CVD) method. The first protective layer 110 prevents damage to the active matrix 100 in which the MOS transistor is embedded during a subsequent process.

The second metal layer 115 is formed on the first protective layer 110. In order to form the second metal layer 115, first, a titanium layer is formed by sputtering titanium (Ti). Subsequently, titanium nitride is deposited on the titanium layer using a physical vapor deposition (PVD) method to form a titanium nitride layer. The second metal layer 115 is formed to have a thickness of about 2000 to 3000 GPa. The second metal layer 115 prevents light leakage current from flowing through the active matrix 100 because the light incident from the light source is incident not only on the mirror 170 but also on a portion other than the portion where the mirror 170 is formed. . Subsequently, a portion of the second metal layer 115 in which the via contact 165 is to be formed in a subsequent process is etched through a photolithography process to form an opening in the second metal layer 115.

The second passivation layer 120 is formed on the second metal layer 115. The second protective layer 120 is formed to have a thickness of about 2.0 to 3.0 µm using phosphorus silicate glass (PSG). The second protective layer 120 also prevents damage to the active matrix 100 having the MOS transistor embedded therein and the results formed on the active matrix 100 during the subsequent process. In this case, since the second protective layer 120 covers the upper portion of the active matrix 100 in which the P-MOS transistor is embedded, the surface flatness is very poor. Therefore, the surface of the second protective layer 120 is planarized by using the chemical mechanical polishing (CMP) method by using the second metal layer 115 under the second protective layer 120 as the CMP termination layer.

After the CMP process is finished, when the second protective layer 120 remains, the second protective layer 120 functions as an etch stop layer during the subsequent removal process of the sacrificial layer, such as the active matrix 100 and The second metal layer 115 may function to prevent etching of the bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ). Therefore, there is no need to laminate a separate etch stop layer, there is an advantage that can shorten the manufacturing process of the present invention.

However, when the second metal layer 115 is partially exposed after the end of the CMP, as shown in FIG. 4B, the antioxidant layer 125 is disposed on the second protective layer and the exposed second metal layer 115. Can be formed. The antioxidant layer 125 is formed to have a thickness of about 1000 to 2000 kPa by depositing nitride (Si ₃ N ₄ ) by low pressure chemical vapor deposition (LPCVD). Preferably, it is formed using a nitride rich in silicon composition. In addition, the anti-oxidation layer 125 may be formed to have a thickness of about 1000 to 2000 Pa using an oxide such as phosphorus silicate glass (PSG) or low temperature oxide (LTO).

Referring to FIG. 4C, a sacrificial layer 130 is formed on the second passivation layer 120. The sacrificial layer 130 performs a function of facilitating the stacking of thin films for forming the actuator 200. The sacrificial layer 130 is formed by depositing polysilicon by low pressure chemical vapor deposition (LPCVD) at a temperature of about 600 ° C. Since the sacrificial layer 130 is formed on the already planarized second protective layer 120, the sacrificial layer 130 does not need a separate planarization process. The sacrificial layer 130 is formed to have a thickness of about 1.0 μm.

Conventionally, when the sacrificial layer is formed using polysilicon, the surface of the sacrificial layer is planarized by performing a separate CMP process because the polysilicon has irregular characteristics. However, in the present invention, the planarization of the second protective layer may be performed after the planarization process is performed on the surface of the second protective layer 120 without having to separately provide or satisfy the conditions for CMP of polysilicon constituting the sacrificial layer. Since the sacrificial layer is formed on the upper portion 120, the process efficiency may be increased.

Subsequently, a portion of the second passivation layer 120 is exposed by etching the portion of the sacrificial layer 130 having the opening of the second metal layer 115 formed therein and an adjacent portion thereof, thereby supporting the actuator 200. Make the position where the anchor will be formed.

Referring to FIG. 4D, a first layer 134 is formed on the exposed second passivation layer 120 and on the sacrificial layer 130. The first layer 134 is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD). The first layer 134 is later patterned into the support layer 135.

The lower electrode layer is formed on the first layer 134 using a metal such as platinum, tantalum, or platinum-tantalum (Pt-Ta), which is a metal having excellent electrical conductivity. The lower electrode layer is formed to have a thickness of about 0.01 to 1.0 탆 using the sputtering method. Subsequently, the lower electrode layer is separated for each pixel so that an independent first signal is applied to each pixel (Iso­Cut process). The lower electrode layer is later patterned into the lower electrode 140. The first signal transferred from the transistor embedded in the active matrix 100 is applied to the lower electrode 140.

A second layer made of PZT or PLZT is formed on the lower electrode layer. The second layer is formed to have a thickness of about 0.1 to 1.0 mu m, preferably about 0.4 mu m, using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the second layer is subjected to a heat treatment by a rapid heat treatment (RTA) method to cause phase shift. The second layer is later patterned into strained layer 150. The deformable layer 150 has an electric field generated by a second signal applied to the upper electrode 155 and a first signal applied to the lower electrode 140 according to a potential difference between the upper electrode 155 and the lower electrode 140. Causes deformation.

An upper electrode layer is stacked on the second layer. The upper electrode layer is formed of a metal having electrical conductivity and reflectivity, such as platinum, aluminum, or silver, to have a thickness of about 0.01 to 1.0 탆 using a sputtering method.

After applying a first photoresist (not shown) to the upper electrode layer by spin coating, patterning the upper electrode layer to have a mirror-shaped 'C' shape as shown in FIG. 2. The upper electrode 155 is formed. The second signal is applied to the upper electrode 155 through a common electrode line (not shown) from the outside. Subsequently, after removing the first photoresist, a second photoresist (not shown) is applied to the patterned upper electrode 155 and the second layer by spin coating, and then the second layer is The strained layer 150 is formed by patterning the electrode 155 to have a shape of a mirror image 'c' slightly wider than the electrode 155 (see FIG. 2).

After applying a third photoresist (not shown) on the upper electrode 155, the strained layer 150, and the lower electrode layer by spin coating, the lower electrode layer is a mirror image slightly wider than the strained layer 150. The lower electrode 140 is formed by patterning the shape of the letter 'c'.

Referring to FIG. 4E, the strained layer 150, the lower electrode 140, the first layer 134, and the second are formed from a portion of the strained layer 150 in which an opening of the second metal layer 115 is formed below. The protective layer 120 and the first protective layer 110 are sequentially etched to form the via hole 160 from one side of the strained layer 150 to the drain pad of the first metal layer 105. The via contact 165 is connected to the drain pad of the first metal layer 105 and the lower electrode 140 by sputtering a metal such as tungsten (W), platinum, aluminum, or titanium into the inside of the 160. Form. Therefore, the via contact 165 is formed from the lower electrode 140 to the top of the drain pad in the via hole 160. The first signal transmitted from the outside is applied to the lower electrode 140 through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 105, and the via contact 165.

Subsequently, a fourth photoresist (not shown) is applied to the patterned lower electrode 140 and the via hole 160 by spin coating, and then extended from both supporting portions of the first layer 134. The portion has a rectangular shape slightly wider than the lower electrode 140, and the central portion of the first layer 134 formed integrally with the lower electrode 140 is patterned to have a rectangular flat plate shape to form the support layer 135. That is, as shown in FIG. 2, the support layer 135 has a shape in which rectangular arms extend from both support portions, and a rectangular flat plate having a wider area between these arms is formed integrally with the arms on the same plane. Have Then, the fourth photoresist is removed. As a result of the patterning of the support layer 135 as described above, a portion of the sacrificial layer 130 is exposed.

After applying a fifth photoresist (not shown) on the exposed sacrificial layer 130 and the upper support layer 135 by a spin coating method, a rectangular flat plate, which is the center of the support layer 135, is exposed. Pattern as much as possible. In addition, a sputtering method or a chemical vapor deposition method is applied to the upper portion of the center portion of the rectangular exposed support layer 135 having a reflective metal such as silver, platinum, or aluminum to a thickness of about 0.3 to 2.0 μm. To be deposited. Subsequently, the deposited metal is patterned so that the deposited metal has the same shape as the central portion of the rectangular exposed support layer 135 to form a mirror 170, and then the fifth photoresist is removed.

Referring to FIG. 4F, the sacrificial layer 130 is etched using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ) to form an air gap 175 at a position of the sacrificial layer 130. Arin and dry treatments are performed to complete the AMA device.

In the above-described thin film type optical path control device according to the present invention, a second signal is applied to the upper electrode 155 through a common electrode line from the outside. At the same time, a first signal is applied to the lower electrode 140 from the outside through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 115, and the via contact 165. An electric field is generated between the electrodes 140 according to the potential difference. Due to this electric field, the deformation layer 150 formed between the upper electrode 155 and the lower electrode 140 causes deformation. The strained layer 150 contracts in a direction orthogonal to the electric field, and thus the actuator 200 including the strained layer 150 and the support layer 135 is bent at a predetermined angle. Since the mirror 170 reflecting the light incident from the light source is formed above the central portion of the support layer 135, the mirror 170 is bent at the same angle as the actuator 200. Accordingly, the mirror 170 reflects the incident light at a predetermined angle, and the reflected light passes through the slit to be projected onto the screen to form an image.

As described above, according to the present invention, a second protective layer is formed on the active matrix so that the thickness of the base layer can be flattened. The second protective layer may be polished by chemical mechanical polishing (CMP) to obtain a flat surface. After the planarization of the second protective layer is performed, a sacrificial layer is formed using polysilicon to form an air gap. Therefore, since the planarization process is performed in the second passivation layer, the process of planarizing the sacrificial layer is not necessary. In addition, since the sacrificial layer is formed on the planarized second protective layer, the remaining thickness of the sacrificial layer can be easily predicted, and the overall residual thickness uniformity of the sacrificial layer formed on the active matrix can be secured.

In addition, the second protective layer remaining after the planarization process simultaneously performs a function of an etch stop layer that protects lower layers during an etching process of a subsequent sacrificial layer, thereby shortening a manufacturing process.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

Providing an active matrix having M × N (M, N is an integer) embedded therein and including a drain pad extending from the drain of the MOS transistor; Forming a second passivation layer on the active matrix; Planarizing the second protective layer by a chemical mechanical polishing (CMP) method; Forming a sacrificial layer using polysilicon on the second protective layer; Forming an actuator on the sacrificial layer, the actuator including a support layer, a lower electrode, a strain layer, and an upper electrode; Forming a mirror on top of the support layer; And And removing the sacrificial layer using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ). The method of claim 1, wherein the forming of the sacrificial layer is performed after forming an antioxidant layer on the second passivation layer. The method of claim 2, wherein the forming of the antioxidant layer is performed using nitride or oxide. The method of claim 2, wherein the forming of the anti-oxidation layer is performed using phosphorus silicate glass (PSG), low temperature oxide (LTO), or silicon nitride rich in silicon composition. Manufacturing method.