KR19990012822A - Manufacturing method of thin film type optical path control device - Google Patents

Abstract

Disclosed is a method of manufacturing a thin film type optical path control device. Provided is an active matrix including an M × N MOS transistor embedded therein and including a first metal layer having a drain pad. An etch stop layer and a first sacrificial layer are sequentially formed on the active matrix. After planarizing the first sacrificial layer by chemical mechanical polishing (CMP) to expose a portion of the etch stop layer by using a difference in polishing rate from the etch stop layer, a second sacrificial layer is formed on the planarized first sacrificial layer. To form. An actuator having a support layer, a lower electrode, a strained layer, and an upper electrode is formed on the second sacrificial layer. By performing the planarization process by using the difference in polishing rate between the etch stop layer and the sacrificial layer, the leveling rate of the sacrificial layer may be improved by compensating for the step resulting from the active matrix. In addition, it is possible to ensure the overall residual thickness uniformity of the sacrificial layer formed on the active matrix.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using an Actuated Mirror Array (AMA), and more particularly, after forming a first sacrificial layer and polishing the first sacrificial layer to expose an etch stop layer below it. The present invention relates to a method of manufacturing a thin film type optical path control apparatus capable of improving the planarization rate of a sacrificial layer by compensating for a step resulting from an active matrix by forming a second sacrificial layer thereon.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, image processing apparatuses using such an optical modulator are classified into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen. do.

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator built into the AMA produces a variation in response to the electric field generated by the applied electrical image signal and bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode therein into an active matrix in which a transistor is built, and then processing by using a sawing method and installing a mirror on the top. . However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 96-42197 (name of the invention: a method of manufacturing a thin film type optical path control device that can control the stress of the membrane) filed by the applicant of the Korean Patent Office on September 24, 1996. It is.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the preceding application.

First, the structure of the thin film type optical path control device is as follows.

The thin film type optical path control device includes an active matrix 1 and an actuator 60. An active matrix 1 having M × N (M, N is an integer) MOS transistors and drain pads 5 formed therein is stacked on top of the active matrix 1 and drain pads 5. The protective layer 10 and the etch stop layer 15 stacked on the protective layer 10 is included.

The actuator 60 has one side in contact with a portion of the etch stop layer 15 in which the drain pad 5 is formed, and the other side has a membrane having a cross section formed horizontally through the air gap 25. , The lower electrode 35 stacked on the membrane 30, the strained layer 40 stacked on the lower electrode 35, the upper electrode 45 stacked on the strained layer 40, the strain Via holes vertically formed from one side of the layer 40 to the drain pad 5 through the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 ( 50, and a via contact 55 formed in the via hole 50 so that the lower electrode 35 and the drain pad 5 are electrically connected to each other.

A stripe 46 is formed on a portion of the upper electrode 45. The stripe 46 operates the upper electrode 45 uniformly to prevent diffuse reflection of light incident from the light source at the boundary between the deformed and undeformed portions of the upper electrode 45.

Hereinafter, the manufacturing method of the said thin film type optical path control apparatus is demonstrated.

Referring to FIG. 1A, an silicate is formed on an active matrix 1 formed of an n-type doped silicon wafer, in which M × N (M, N is an integer) P-MOS transistors are formed and a drain pad 5 is formed. A protective layer 10 made of glass PSG is formed. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded during subsequent processing.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 µm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby making the support 22 of the actuator 60.

Referring to FIG. 1B, the membrane 30 is stacked on the exposed etch stop layer 15 and the sacrificial layer 20. The membrane 30 is formed by depositing nitride to a thickness of about 0.01 to 1.0 mu m using a low pressure chemical vapor deposition (LPCVD) method.

Subsequently, a lower electrode 35 is stacked on top of the membrane 30. The lower electrode 35 is formed of a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) to have a thickness of about 0.01 to 1.0 탆 using a sputtering method. Subsequently, the lower electrode 35 is separated for each pixel through a photolithography process so that an independent first signal (image signal) is applied to each pixel (Iso-cutting process). The first electrode transmitted from the outside through the transistor built in the active matrix 1 is applied to the lower electrode 35.

A deformation layer 40 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode 35. The strained layer 40 is formed to have a thickness of about 0.1-1 .0 μm, preferably about 0.4 μm using a sol-gel method, a sputtering method, or a chemical vapor deposition method. do. In addition, the piezoelectric material constituting the strained layer 40 is subjected to heat treatment by a rapid heat treatment (RTA) method to cause phase shift. The deformable layer 40 is applied with a second signal (bias signal) to the upper electrode 45 and a first signal is applied to the lower electrode 35 so that a potential difference between the upper electrode 45 and the lower electrode 35 is applied. Deformation is caused by the electric field generated.

The upper electrode 45 is stacked on the deformation layer 40. The upper electrode 45 is formed so as to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. Since the upper electrode 45 has excellent electrical conductivity and reflection characteristics, the upper electrode 45 performs not only a function of a bias electrode generating an electric field but also a function of a mirror reflecting light incident from a light source.

Subsequently, the upper electrode 45, the strained layer 40, and the lower electrode 35 are sequentially patterned from a top of the upper electrode 45 into a predetermined pixel shape. At this time, one side of the upper electrode 45 uniformly operates the upper electrode 45 so that the deformation of the deformation layer 40 of the upper electrode 45 at the boundary between the portion that causes deformation and the undeformed portion Stripes 46 are formed to prevent diffuse reflection of light incident from the light source.

Subsequently, the via hole 50 is etched by sequentially etching the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 from one side of the strained layer 40. Form. Accordingly, the via hole 50 is vertically formed from one side of the strained layer 40 to the drain pad 5. Subsequently, a metal having electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form the via contact 55. The via contact 55 electrically connects the drain pad 5 and the lower electrode 35. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. Subsequently, the membrane 30 is patterned into a predetermined pixel shape.

In addition, the sacrificial layer 20 is etched using hydrogen fluoride (HF) vapor to form an air gap 25, followed by a rinse and dry treatment to complete an AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. In addition, a second signal is applied to the upper electrode 45 to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 formed between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in the direction orthogonal to the electric field, and the actuator 60 including the strained layer 40 is bent upwards in the opposite direction to the direction in which the membrane 30 is formed. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

According to the manufacturing method of the thin film type optical path control apparatus described in the above-described prior application, as shown in FIG. 1A, the sacrificial layer 20 on the etch stop layer 15 is thick enough to overcome the unevenness of the underlying layer, for example, 2. . After deposition to a thickness of 5 μm or more, the sacrificial layer 20 is planarized by a chemical mechanical polishing (CMP) process, and the sacrificial layer 20 is etched through a photolithography process. The support 22 is formed. However, according to the above-described method, the sacrificial layer does not sufficiently achieve flattening of the uneven portion on the active matrix, resulting in a problem of unevenness of the underlying layer appearing on the mirror surface. In addition, since the uniformity of the sacrificial layer thickness remaining after the CMP process as a whole of the module of the thin film type optical path control device is not secured, the outer side of the module may be excessively polished to cause defects. In addition, since the residual thickness of the sacrificial layer is difficult to accurately predict after performing the chemical mechanical polishing process (CMP), the thickness of the remaining sacrificial layer is insufficient or excessive in the entire module, thereby lowering the yield.

Accordingly, an object of the present invention is to compensate for the step resulting from the active matrix by forming the first sacrificial layer and polishing the first sacrificial layer to expose the underlying etch stop layer, and then forming a second sacrificial layer thereon. The present invention provides a method for manufacturing a thin film type optical path control apparatus capable of improving the planarization rate of a sacrificial layer.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

2 is a plan view of a thin film type optical path control apparatus according to the present invention.

3 is a cross-sectional view taken along line AA ′ of the apparatus of FIG. 2.

4A to 4E are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 3.

Explanation of symbols for the main parts of the drawings

100: active matrix 155: first metal layer

160: first protective layer 165: second metal layer

170: second protective layer 175: etch stop layer

178: first sacrificial layer 180: second sacrificial layer

185: support layer 190: lower electrode

195 strain layer 200 upper electrode

205 Actuator 210 Beer Hole

215: Beer contact 220: Stripe

225: air gap

In order to achieve the above object, the present invention provides an active matrix comprising a first metal layer having M x N (M, N is an integer) MOS transistor embedded therein and having a drain pad extending from the drain region of the transistor. step; Sequentially forming an etch stop layer and a first sacrificial layer on the active matrix; Planarizing the first sacrificial layer by a chemical mechanical polishing (CMP) method to expose a portion of the etch stop layer by using a difference in polishing rate from the etch stop layer; Forming a second sacrificial layer on the planarized first sacrificial layer; And i) forming a support layer on top of the second sacrificial layer, ii) forming a bottom electrode on top of the support layer, iii) forming a strained layer on top of the bottom electrode, and iv) It provides a method of manufacturing a thin film type optical path control device comprising the step of forming an actuator having a step of forming an upper electrode on top of the strained layer.

In the above-described thin film type optical path control device according to the present invention, the first signal (image signal) transmitted from the outside is applied to the lower electrode through the transistor, the drain pad, and the via contact embedded in the active matrix. At the same time, a second signal (bias signal) is applied to the upper electrode to generate an electric field between the upper electrode and the lower electrode. By this electric field, the strained layer between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction orthogonal to the generated electric field, and the actuator is bent at a predetermined angle. The upper electrode, which also functions as a mirror that reflects light, is formed on the actuator and is inclined with the actuator. Accordingly, the upper electrode reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming an etch stop layer made of silicon nitride (Si ₃ N ₄ ) on the active matrix, there is a stable (stable) step step coverage (step coverage) thereon The first sacrificial layer made of this excellent material, preferably silicon oxide (SiO ₂ ), polycrystalline silicon, phosphorus silicate glass (PSG) having a low concentration of phosphorus (P), or silicate glass containing no phosphorus, It is formed to a thickness that can level the level difference. Since the etch stop layer has a slow polishing rate, the first sacrificial layer may be polished by chemical mechanical polishing (CMP) until the surface of the etch stop layer is exposed to obtain a flat surface. After the first sacrificial layer is flattened as described above, a second sacrificial layer is formed as a sacrificial layer for forming an air gap.

Therefore, the planarization rate of the sacrificial layer can be improved by performing the planarization process by using the difference in polishing rate between the etch stop layer and the sacrificial layer. In addition, after performing a chemical mechanical polishing (CMP) process, it is possible to easily predict the residual thickness of the sacrificial layer, and to ensure the overall residual thickness uniformity of the sacrificial layer formed on the active matrix.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

Figure 2 shows a plan view of the thin film type optical path control apparatus according to the present invention, Figure 3 is a cross-sectional view of the thin film type optical path control apparatus along the line AA 'of FIG.

2 and 3, the thin film type optical path control apparatus includes an active matrix 100 and an actuator 205 formed on the active matrix 100.

The active matrix 100 includes an isolation layer 120 for dividing the active matrix 100 into an active region and a field region, and a gate 115, a source 110, and a drain 105 in the active region. The formed MxN (M, N is an integer) P-MOS transistors are included. In addition, the active matrix 100 is stacked on top of the first metal layer 155 and the first metal layer 155 that are stacked on top of the MOS transistor and patterned to be connected to the source 110 and the drain 105, respectively. First protective layer 160, second metal layer 165 stacked on top of first protective layer 160, second protective layer 170 stacked on top of second metal layer 165, and second The anti-etching layer 175 stacked on the protective layer 170 is included.

The first metal layer 155 includes a drain pad extending from the drain 105 of the MOS transistor, and the second metal layer 165 includes a first layer 165a made of titanium (Ti) and titanium nitride (TiN). It comprises a second layer 165b consisting of.

One side of the actuator 205 is in contact with a portion of the etch stop layer 175 where the drain pad of the first metal layer 155 is formed, and the other side thereof is horizontal with the etch stop layer 175 through the air gap 225. A support layer 185 having a cross section formed, a lower electrode 190 formed on the support layer 185, a strain layer 195 formed on the lower electrode 190, and an upper electrode formed on the strain layer 195 ( 200, and a strained layer 195, a lower electrode 190, a support layer 185, an etch stop layer 175, a second passivation layer 170, and a first passivation layer from one side of the strained layer 195 ( The via contact 215 may be formed to connect the drain pad and the lower electrode 190 to the via hole 210 formed vertically through the 160 to the drain pad of the first metal layer 155.

The support layer 185 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application. One side of the upper electrode 200 operates the upper electrode 200 uniformly so that when the strained layer 195 of the upper electrode 200 causes deformation, the light source is disposed at a boundary between a portion that is deformed together and a portion that is not deformed. Stripes 220 are formed to prevent the incident light from being diffusely reflected.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

4A to 4E are cross-sectional views for explaining the method for manufacturing the device shown in FIG. 3. 4A to 4E, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 4A, after preparing an active matrix 100 formed of, for example, an n-type doped silicon (Si) wafer, the active matrix (LOCOS) may be manufactured using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer 120 is formed in 100 to separate the active region and the field region. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then a p ⁺ source 110 and a drain 105 are formed by using an ion implantation process. M x N (M and N are integers) to form P-MOS transistors.

After forming the insulating layer 125 made of oxide on the top of the resultant MOS transistor is formed, openings for exposing the top of one side of the source 110 and the drain 105, respectively, using a photolithography process. Subsequently, after depositing a first metal layer 155 made of a metal such as tungsten (W) on the resultant formed opening, the first metal layer 155 is patterned by a photolithography process. The patterned first metal layer 155 includes a drain pad that extends from the drain 105 of the MOS transistor to a support of the actuator 205 that is subsequently formed. Therefore, the first signal (image signal) applied from the outside is transferred to the lower electrode 190 through the MOS transistor embedded in the active matrix 100 and the drain pad of the first metal layer 155.

Subsequently, a first protective layer 160 is formed on the active matrix 100 and the first metal layer 155 to protect the active matrix 100 having the MOS transistors embedded therein. The first passivation layer 160 is formed to have a thickness of about 8000 kPa using the silicate glass (PSG) method using a chemical vapor deposition (CVD) method. The first protective layer 160 prevents damage to the active matrix 100 in which the transistor is embedded during the subsequent process.

The second metal layer 165 is formed on the first passivation layer 160. In order to form the second metal layer 165, first, the first layer 165a is formed by sputtering titanium to a thickness of about 300 μs. Next, titanium nitride is deposited on the first layer 165a by using a physical vapor deposition (PVD) method to form a second layer 165b. Since the light incident from the light source is incident not only to the upper electrode 200, which is a reflective layer, but also to a portion other than the portion where the upper electrode 200 is formed, the second metal layer 165 may have a light leakage current in the active matrix 100. To prevent it from flowing. Subsequently, in the subsequent process of the second metal layer 165, the portion 166 on which the via contact 215 is to be formed is etched through a photolithography process.

The second passivation layer 170 is formed on the second metal layer 165. The second protective layer 170 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 170 also prevents damage to the active matrix 100 in which the transistor is embedded during subsequent processing.

Subsequently, an etch stop layer 175 is formed on the second passivation layer 170. The etch stop layer 175 prevents the active matrix 100 and the second passivation layer 170 from being etched due to the subsequent etching process. The etch stop layer 175 is formed by depositing silicon nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

The first sacrificial layer 178 is formed on the etch stop layer 175. Since the first sacrificial layer 178 serves to planarize the surface of the active matrix 100 in which the transistor is embedded, a thickness capable of flattening the level of the underlying layer of a material having excellent stability and high level coating property, preferably 1. It is formed by evaporating to a thickness of 5 to 2.0 mu m. Preferably, a silicon oxide film (SiO ₂ ) or a polycrystalline silicon (ploysilicon) film is easily deposited by chemical vapor deposition (CVD), or tetraethylorthosilicate (TEOS) is used for low pressure chemical vapor deposition (LPCVD). Deposition or PECVD (Plasma Enhanced Chemical Vapor Deposion) method. Also preferably, chemical vapor deposition (CVD) is performed on phosphorus silicate glass (PSG) having a low concentration of phosphorus (P), silicate glass containing no phosphorus, or silicate glass containing BP and phosphorus (BPSG). The first sacrificial layer 178 is formed by depositing in a method.

Referring to FIG. 4B, the surface of the first sacrificial layer 178 is polished and planarized using a chemical mechanical polishing (CMP) method. In this case, since the polishing rate of the LPCVD-silicon nitride film used as the etch stop layer 175 is only about 1/10 of the silicate glass used as the sacrificial layer, until the surface of the etch stop layer 175 is exposed. When the chemical mechanical polishing (CMP) process of the first sacrificial layer 178 is performed, the exposed etch stop layer 175 may not be further polished due to the slow polishing rate. Thus, as shown in FIG. 4B, a flat surface may be obtained by compensating for a step resulting from the active matrix 100.

Referring to FIG. 4C, the second sacrificial layer 180 is formed on the first sacrificial layer 178 planarized as described above. The second sacrificial layer 180 is provided to form an air gap 225 in a subsequent process, and the chemical vapor deposition (CVD) method of phosphorus silicate glass (PSG) having a high concentration of phosphorus (P) is preferably performed. It is formed by depositing to a thickness of about 1.0㎛. As described above, in the present invention, since the first sacrificial layer 178 is formed and the upper portion thereof is polished to overcome the step of the active matrix 100, the planarization is achieved and the air gap is formed from the second sacrificial layer 180. The materials of the first sacrificial layer 178 and the second sacrificial layer 180 may be appropriately selected and used to suit the purpose. Therefore, in the conventional method, the sacrificial layer may simultaneously perform two roles of the planarization layer and the sacrificial layer for forming the actuator 205, thereby overcoming the difficulty of material selection. As a result, even more stable thickness uniformity can be obtained compared to the uniformity of the sacrificial layer thickness obtained in the chemical mechanical polishing (CMP) process.

Referring to FIG. 4D, the support portion of the actuator 205 is exposed by etching a portion of the second sacrificial layer 180 in which the drain pad of the first metal layer 155 is formed to be etched to expose a portion of the etch stop layer 175. To form.

Subsequently, the support layer 185 is formed on the exposed etch stop layer 175 and on the sacrificial layer 180. The support layer 185 is formed to have a thickness of about 0.1 to 1.0 μm using low pressure chemical vapor deposition (LPCVD).

The lower electrode 190 is formed on the support layer 185. The lower electrode 190 has a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) by using a sputtering method or a chemical vapor deposition method. It is formed to have a thickness of about μm. At the same time, the lower electrode 190 is separated for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso-cutting process). The first electrode transmitted from the outside through the MOS transistor embedded in the active matrix 100 is applied to the lower electrode 190.

A strained layer 195 formed of a piezoelectric material such as PZT or PLZT is formed on the lower electrode 190. The strained layer 195 is formed to have a thickness of about 0.1 to 1.0 µm, preferably about 0.4 µm using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the piezoelectric material constituting the strained layer 190 is thermally transformed by a rapid heat treatment (RTA) method. The strained layer 190 is applied with a second signal (bias signal) to the upper electrode 200 and a first signal is applied to the lower electrode 190 so that a potential difference between the upper electrode 200 and the lower electrode 190 is applied. Deformation is caused by the electric field generated.

The upper electrode 200 is formed on the deformation layer 190. The upper electrode 200 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). The upper electrode 200 is applied with a second signal (bias signal) from the outside through a common electrode line (not shown). Since the upper electrode 200 has excellent electrical conductivity and reflectivity, the upper electrode 200 performs not only a function of a bias electrode generating an electric field but also a function of a mirror reflecting light incident from a light source.

Subsequently, the upper electrode 200, the deformation layer 195, and the lower electrode 190 are sequentially patterned in a predetermined pixel shape from the top of the upper electrode 200. At this time, one side of the upper electrode 200 uniformly operates the upper electrode 200 so that when the strained layer 195 causes deformation, the portion that causes deformation together with the upper electrode 200 and the portion that is not deformed. A stripe 220 is formed to prevent diffuse reflection of light incident from the light source at the boundary of.

Referring to FIG. 4E, the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first protection from one side of the strained layer 195. The layers 160 are sequentially etched to form via holes 210. Therefore, the via hole 210 is vertically formed from one side of the strained layer 195 to the drain pad of the first metal layer 155. Subsequently, a metal having electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 215. The via contact 215 electrically connects the drain pad of the first metal layer 155 and the lower electrode 190. Therefore, the first signal applied from the outside is applied to the lower electrode 190 through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 155, and the via contact 215.

Subsequently, the second sacrificial layer 180 is etched using hydrogen fluoride (HF) vapor to form an air gap 225, followed by a rinse and dry process to complete an AMA device. .

In the above-described thin film type optical path control device according to the present invention, the first signal transmitted from the outside is transferred through the MOS transistor embedded in the active matrix 100, the drain pad of the first metal layer 155, and the via contact 215. It is applied to the lower electrode 190. At the same time, a second signal is applied to the upper electrode 200 from the outside through a common electrode line, thereby generating an electric field according to a potential difference between the upper electrode 200 and the lower electrode 190. Due to this electric field, the deformation layer 195 formed between the upper electrode 200 and the lower electrode 190 causes deformation. The strained layer 195 contracts in a direction orthogonal to the electric field, whereby the actuator 205 including the strained layer 195 is bent at a predetermined angle. The upper electrode 200, which also functions as a mirror that reflects light, is formed on the actuator 205 and is inclined together with the actuator 205. Accordingly, the upper electrode 200 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

As described above, according to the manufacturing method of the thin film type optical path control device according to the present invention, the first sacrificial layer is formed on the upper portion of the etch stop layer to a thickness sufficient to flatten the step of the underlying layer, and then the surface of the etch stop layer Until this exposure, the first sacrificial layer may be polished by chemical mechanical polishing (CMP) to overcome the step resulting from the active matrix to obtain a flat surface. After the first sacrificial layer is flattened as described above, a second sacrificial layer is formed as a sacrificial layer for forming an actuator.

Accordingly, the planarization process may be performed by using a difference in polishing rate between the etch stop layer and the first sacrificial layer to compensate for the step difference resulting from the active matrix, thereby improving the planarization rate of the first sacrificial layer, and chemical mechanical polishing (CMP). After the process, the remaining thickness of the sacrificial layer can be easily estimated.

In addition, it is possible to ensure the remaining thickness uniformity of the sacrificial layer formed on the active matrix as a whole, and to reduce defects caused by excessive polishing of the sacrificial layer. Furthermore, by planarizing with the first sacrificial layer and forming an air gap with the second sacrificial layer, the materials of the first and second sacrificial layers can be appropriately selected and used to suit each purpose.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (5)

Providing an active matrix comprising a first metal layer having M × N (M, N is an integer) embedded therein and having drain pads extending from the drain region of the transistor; Sequentially forming an etch stop layer and a first sacrificial layer on the active matrix; Planarizing the first sacrificial layer by a chemical mechanical polishing (CMP) method to expose a portion of the etch stop layer by using a difference in polishing rate from the etch stop layer; Forming a second sacrificial layer on the planarized first sacrificial layer; And i) forming a support layer on top of the second sacrificial layer, ii) forming a bottom electrode on top of the support layer, iii) forming a strained layer on top of the bottom electrode, and iv) the deformation A method of manufacturing a thin film type optical path control device comprising the step of forming an actuator having a step of forming an upper electrode on top of a layer. The method of claim 1, wherein the forming of the first sacrificial layer is performed by chemical vapor deposition (CVD) of silicon oxide (SiO ₂ ) or polycrystalline silicon. The method of claim 1, wherein the forming of the first sacrificial layer comprises forming the first sacrificial layer to have a thickness of 1.5-5 μm. The method of claim 1, wherein the first sacrificial layer includes phosphorus silicate glass (PSG) having a low concentration of phosphorus (PG), silicate glass containing no phosphorus, and silicate glass containing bromine (Br) and phosphorus (BPSG). Any one selected from the group consisting of a method for manufacturing a thin film type optical path control apparatus, characterized in that performed using a chemical vapor deposition (CVD) method. The thin film type of claim 1, wherein the first sacrificial layer is performed by using tetraethylorthosilicate (TEOS) using a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method. Method of manufacturing the optical path control device.