KR19990034640A - Manufacturing method of thin film type optical path control device - Google Patents

Abstract

Disclosed is a method of manufacturing a thin film type optical path control apparatus that can improve the yield of the process by easily removing the sacrificial layer. After the first sacrificial layer is formed on the entire surface of the active matrix, the actuator is formed. The first sacrificial layer is maintained at a pressure of 3 to 5T in the expansion chamber and removed using BrF ₃ or XeF ₂ at about 5 pulses at a rate of 1 pulse every minute, and then a second sacrificial layer is formed on top of the actuator and a mirror is formed. . The second sacrificial layer is removed in the same manner as the first sacrificial layer. Although the silica layer is formed due to the processes subsequent to the surfaces of the first and second sacrificial layers made of polysilicon, the first sacrificial layer and the second sacrificial layer can be easily removed by adjusting the pressure in the expansion chamber. The yield can be improved.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using an Actuated Mirror Array (AMA), and more particularly, to easily remove the sacrificial layer by changing the pressure in the expansion chamber when the sacrificial layer is removed. The present invention relates to a method for manufacturing a thin film type optical path control device capable of improving yield.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode therein into an active matrix in which a transistor is built, and then processing by using a sawing method and installing a mirror on the top. . However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 96-64440 (name of the invention: a method of manufacturing a thin film type optical path control device) filed by the applicant of the Korean Patent Office on December 11, 1996.

Figure 1 shows a cross-sectional view of the thin film type optical path control device described in the preceding application.

Referring to FIG. 1, the thin film type optical path adjusting device includes an active matrix 1, an actuator 25, and a mirror 29. The active matrix 1 in which M x N (M, N is an integer) MOS transistors and a drain pad 7 extending from the drain of the transistor is formed. The active matrix 1 and the drain pad ( 7) a protective layer 3 stacked on top of the protective layer 3 and an etch stop layer 5 stacked on the protective layer 3.

The actuator 25 has a membrane 13 and a membrane 13 in which one side is in contact with a portion where the drain pad 7 is formed in the lower portion of the etch stop layer 5, and the other side is horizontally formed through the air gap 11. ), The lower electrode 15 stacked on top of the bottom electrode 15, the strained layer 17 stacked on top of the lower electrode 15, the upper electrode 19 stacked on top of the strained layer 17, and the strained layer 140. In the via hole 21 formed perpendicularly to the drain pad 7 through the strained layer 17, the lower electrode 15, the membrane 13, the etch stop layer 5, and the protective layer 3 from one side of the The lower electrode 15 and the drain pad 7 include a via contact 23 formed to be connected to each other. The mirror 29 has one side bent at a right angle to contact the upper electrode 19 and the other side is formed horizontally. The mirror 29 has the shape of a 'b'.

Hereinafter, the manufacturing method of the above-mentioned thin film type optical path control apparatus will be described. 2A to 2D are manufacturing process diagrams of the apparatus shown in FIG. 1. Referring to FIG. 2A, a protective layer 3 is formed by using silicate glass PSG on top of an active matrix 1 having M × N MOS transistors (not shown) and having a drain pad 7 formed therein. Laminated. The protective layer 3 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 3 protects the active matrix 1 in which the transistor is embedded during subsequent processing.

An etch stop layer 5 made of nitride is stacked on the passivation layer 3. The etch stop layer 5 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 5 prevents the protective layer 3, the active matrix 1, and the like from being etched during the subsequent etching process. The first sacrificial layer 9 is stacked on the etch stop layer 5. The first sacrificial layer 9 is formed of phosphorous silicate glass or poly silicon having a high concentration of phosphorus (P) so as to have a thickness of about 1.0 to 3.0 μm using an atmospheric chemical vapor deposition (APCVD) method. Form. In this case, since the first sacrificial layer 9 covers the upper portion of the active matrix 1 in which the transistor is embedded, the flatness of the surface thereof is very poor. Accordingly, the surface of the first sacrificial layer 9 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the first sacrificial layer 9 in which the drain pad 7 is formed is etched to expose a portion of the etch stop layer 5 to form a position where the support portion of the actuator 25 is to be formed.

Referring to FIG. 2B, the membrane 13 is laminated on the exposed etch stop layer 5 and the first sacrificial layer 9 to a thickness of about 0.1 μm to about 1.0 μm. The membrane 13 is formed using a low pressure chemical vapor deposition (LPCVD) method. At this time, the membrane 13 is formed while varying the ratio of the reaction gas in the low pressure reaction vessel to control the stress in the membrane 13.

The lower electrode 15 made of a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) is stacked on the membrane 13. The lower electrode 15 is formed to have a thickness of about 0.1 to 1.0 μm using a sputtering method. A first signal (image signal) is applied to the lower electrode 15 through a transistor built in the active matrix 1 from the outside.

A deformation layer 17 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode 15. The strained layer 17 is formed to have a thickness of about 0.1 μm to about 1.0 μm, preferably about 0.4 μm using the sol-gel method, and then subjected to a phase change by heat treatment using a rapid heat treatment (RTA) method. In the strained layer 17, a second signal (bias signal) is applied to the upper electrode 19, and a first signal is applied to the lower electrode 15, according to a potential difference between the upper electrode 19 and the lower electrode 15. It is deformed by the generated electric field.

The upper electrode 19 is stacked on top of the strained layer 17. The upper electrode 19 is formed of a metal having excellent electrical conductivity such as aluminum or platinum so as to have a thickness of about 0.1 to 1.0 μm using a sputtering method. The second signal is applied to the upper electrode 19 through a common electrode line (not shown) from the outside.

Referring to FIG. 2C, after patterning the upper electrode 19, the strained layer 17, and the lower electrode 15 to have a predetermined pixel shape, the drain pad 7 is formed from one side of the strained layer 17. The strained layer 17, the lower electrode 15, the membrane 13, the etch stop layer 5, and the protective layer 3 are sequentially etched so as to be perpendicular from the strained layer 17 to the drain pad 7. The via hole 21 is formed. Subsequently, a via contact 23 is formed in the via hole 21 so that the drain pad 7 and the lower electrode 15 are electrically connected by sputtering a metal such as tungsten, platinum, or titanium. Thus, the via contact 23 is vertically formed from the lower electrode 15 to the drain pad 7 in the via hole 21. Therefore, the first signal is applied from the outside to the lower electrode 15 through the transistor, the drain pad 7 and the via contact 23 embedded in the active matrix 1. Then, platinum-tantalum (Pt-Ta) is deposited on the bottom of the active matrix 1 using a sputtering method to form a backside metal layer (not shown). Subsequently, the actuator 25 is completed by etching the first sacrificial layer 9 with hydrogen fluoride (HF) vapor to form an air gap 11 at the position of the first sacrificial layer 9.

Referring to FIG. 2D, after forming the air gap 11 as described above, the second sacrificial layer 27 is formed on the entire surface of the resultant. The second sacrificial layer 27 is formed using polymer, polysilicon, or the like, and is formed to completely cover the actuator 25 while completely filling the air gap 11. Subsequently, the second sacrificial layer 27 is patterned to form a post in which the mirror 29 is formed on one side of the upper electrode 19. Thus, one side of the upper electrode 19 is exposed. Subsequently, aluminum (Al) or silver (Ag), which is a reflective metal, is formed on the upper portion of the second sacrificial layer 27 and the exposed upper electrode 19 on which the post is formed by using a sputtering method. The mirror 29 is formed by depositing to a thickness. Preferably, the mirror 29 has a '-' shape, one side is bent at a right angle to contact the upper electrode 19, the other side is formed horizontally with respect to the upper electrode 19. After forming the mirror 29 as described above, the second sacrificial layer 27 is removed using hydrogen fluoride vapor or oxygen plasma, and rinsed and dried to perform a thin film type AMA as shown in FIG. 1. Complete the device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 15 and the second signal is applied to the upper electrode 19, and according to the potential difference between the upper electrode 19 and the lower electrode 15. Electric field is generated. The deformed layer 17 formed between the upper electrode 19 and the lower electrode 15 causes deformation, and the deformed layer 17 contracts in a direction orthogonal to the electric field. Accordingly, the actuator 25 including the deformation layer 17 is bent at a predetermined angle, and the mirror 29 mounted on the upper electrode 19 of the actuator 25 is attached to the bent upper electrode 19. This causes the axis to move and incline to reflect light incident from the light source. The light reflected by the mirror 29 is projected onto the screen through the slit to form an image.

However, in the method of manufacturing the above-described thin film type optical path control apparatus, when the first sacrificial layer 9 and the second sacrificial layer 27 are deposited using polysilicon, the effects of the subsequent steps are shown in FIGS. 2B and 2D. As shown in FIG. 3, the silica (SiO ₂ ) layer 33 is formed on the surface of the deposited polysilicon to completely remove the first sacrificial layer 9 and the second sacrificial layer 27. A problem arises. That is, when the first sacrificial layer 9 and the second sacrificial layer 27 are removed in the expansion chamber, the silica layer 33 is not completely etched under a pressure of about 2T, which is a normal pressure, and thus, the lower sacrificial layer 9 is removed. The first sacrificial layer 9 and the second sacrificial layer 27 may not be removed, resulting in a decrease in the yield of the process.

Accordingly, it is an object of the present invention to provide a method of manufacturing a thin film type optical path control apparatus which can easily remove a sacrificial layer and improve the yield of the process by changing the pressure in the expansion chamber when the sacrificial layer is removed.

1 is a cross-sectional view of a thin film type optical path adjusting device described in the applicant's prior application.

2A to 2D are manufacturing process diagrams of the apparatus shown in FIG. 1.

3 is a plan view of a thin film type optical path control apparatus according to the present invention.

4 is an enlarged perspective view of the apparatus shown in FIG. 3.

FIG. 5 is a cross-sectional view of the apparatus shown in FIG. 4 taken along line C-C '.

6A to 6F are manufacturing process diagrams of the apparatus shown in FIG.

<Explanation of symbols for main parts of the drawings>

100: active matrix 130: first metal layer

135: first protective layer 140: second metal layer

145: second protective layer 150: etch stop layer

155: first sacrificial layer 160: first air gap

165 support layer 170 lower electrode

175 strain layer 180 upper electrode

185: Beer Hall 190: Beer Contact

195: lower electrode connecting member 200: common electrode line

205: upper electrode connecting member 210: actuator

215: second sacrificial layer 220: post

230: mirror 240: backside metal layer

250: second air gap

In order to achieve the above object, the present invention provides a method comprising: providing an active matrix containing M x N (M, N is an integer) MOS transistor; Forming a first metal layer on the active matrix, the first metal layer including a drain pad extending from the drain of the MOS transistor; Forming a first sacrificial layer using amorphous silicon or polysilicon on top of the active matrix; After patterning the first sacrificial layer, forming an actuator including a support layer, a lower electrode, a strain layer, and an upper electrode on the patterned first sacrificial layer; Forming a backside metal layer on a back surface of the active matrix; Maintaining the pressure in the expansion chamber at about ₃ to 5T and removing the first sacrificial layer using bromine fluoride (BF ₃ ) or xenon fluoride (XeF ₂ ) at a rate of 5 pulses at a rate of 1 pulse every minute; Forming a second sacrificial layer on the actuator by spin coating; Patterning the second sacrificial layer to expose a portion of the upper electrode; Forming a post and a mirror over the exposed top electrode and the second sacrificial layer; And maintaining the pressure in the expansion chamber at about 3 to 5T and removing the second sacrificial layer using bromine or fluoride xenon at a rate of 5 pulses at a rate of 1 pulse every minute. to provide.

According to the present invention, even if a silica layer is produced due to a process subsequent to the surfaces of the first sacrificial layer and the second sacrificial layer made of polysilicon or the like, the pressure in the expansion chamber is maintained at about 3 to 5T and at a rate of 1 pulse every minute. Bromine fluoride or xenon fluoride can be used to remove the first sacrificial layer and the second sacrificial layer easily to about 5 pulses to improve the yield of the process.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

Figure 3 is a plan view of a thin film type optical path control apparatus according to the present invention, Figure 4 is an enlarged perspective view of the device shown in Figure 3, Figure 5 shows a cross-sectional view of the device of Figure 4 cut along the line CC '. will be.

3 to 5, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 210 formed on the active matrix 100, and a mirror 230 formed on the actuator 210. ).

The active matrix 100 includes an isolation layer 120 for dividing the active matrix 100 into an active region and a field region on the front surface of the active matrix 100, a gate 115 in the active region, And M × N (M, where N is an integer) P-MOS transistors formed with source 110 and drain 105. In addition, the active matrix 100 is stacked on top of the first metal layer 130 and the first metal layer 155 that are stacked on top of the MOS transistor and patterned to be connected to the source 110 and the drain 105, respectively. The first protective layer 135, the second metal layer 140 stacked on the first protective layer 135, the second protective layer 145 stacked on the second metal layer 140, and the second The anti-etching layer 150 may be stacked on the passivation layer 145. The first metal layer 130 includes a drain pad extending from the drain 105 of the MOS transistor, and the second metal layer 140 includes a titanium (Ti) layer and a titanium nitride (TiN) layer.

The backside of the active matrix 100 has a backside metal layer 240 that applies a bias voltage to the MOS transistor embedded in the active matrix 100 to prevent current from flowing in the reverse direction in the transistor. Is formed. The backside metal layer 240 includes a tantalum layer 238 and a platinum layer 239, and the tantalum layer 238 facilitates adhesion of the active matrix 100 and the platinum layer 239 to the platinum layer 239. The bias voltage is applied to prevent reverse current from flowing through the transistor.

The actuator 210 has a support layer 165 in which one side is in contact with a portion in which the drain pad of the first metal layer 130 is formed below the etch stop layer 150, and the other side is horizontally formed through the air gap 160. , A lower electrode 170 stacked on the support layer 165, a strain layer 197 stacked on the lower electrode 170, an upper electrode 180 stacked on the strain layer 175, and the The first through the strained layer 175, the lower electrode 170, the support layer 165, the etch stop layer 150, the second protective layer 145, and the first protective layer 135 from one side of the strained layer 175. The via contact 190 is formed to connect the lower electrode 170 and the drain pad of the first metal layer 130 to each other in the via hole 185 vertically up to the drain pad of the first metal layer 130. The support layer 165 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application. Preferably, the support layer 165 has a 'T' shape, and the lower electrode 170 is formed on a central portion of the support layer 165 in a quadrangular shape. The strained layer 175 has a rectangular shape with a smaller area than the lower electrode 170, and the upper electrode 180 has a rectangular shape with a smaller area than the strained layer 175.

In addition, referring to FIG. 4, the actuator 210 is formed from the via contact 190 to the lower electrode 170 to connect the lower electrode connecting member 170 to the via contact 190 and the lower electrode 170. ), A common electrode line 200 formed on one side of the support layer 165, and an upper electrode connection member 205 connecting the upper electrode 180 and the common electrode line 200. A first signal (image signal) is applied to the lower electrode 170 through the transistor, the via contact 190, and the lower electrode connection member 195 embedded in the active matrix 100 from the outside. At the same time, when the second signal (bias signal) is applied to the upper electrode 180 through the common electrode line 200 and the upper electrode connecting member 205 from the outside, the deformation formed between the upper electrode 180 and the lower electrode 170. Layer 175 causes deformation.

The mirror 230 has a lower shape supported by a post 220 formed on one side of the upper electrode 200 and has a rectangular flat plate formed on both sides of the mirror 230.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

6A to 6E are manufacturing process diagrams of the apparatus shown in FIG.

Referring to FIG. 6A, after preparing an active matrix 100, which is an n-type doped silicon (Si) wafer, the active matrix 100 may be formed using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer 120 is formed in the active region and the field region. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source 110 and drain 105 are formed by an ion implantation process. N (M, N is an integer) P-MOS transistors are formed.

After forming the insulating layer 125 made of oxide on the top of the resultant P-MOS transistor is formed, openings for exposing the top of one side of the source 110 and the drain 105, respectively by a photolithography process. Subsequently, the first metal layer 130 is formed by depositing a metal such as titanium, titanium nitride, tungsten, or the like on the resultant material on which the openings are formed. The first metal layer 130 patterned as described above includes a drain pad extending from the drain 105 of the P-MOS transistor to an anchor 182 that is a support of the actuator 210.

A first protective layer 135 is formed on the first metal layer 130 to protect the active matrix 100 having the P-MOS transistor. The first passivation layer 135 is formed to have a thickness of about 8000 GPa by using the silicate glass (PSG) chemical vapor deposition (CVD) method.

A second metal layer 140 including a titanium layer and a titanium nitride layer is formed on the first passivation layer 135. In order to form the second metal layer 140, first, a titanium layer is formed by sputtering titanium (Ti) to a thickness of about 300 μm. Subsequently, titanium nitride is deposited on the titanium layer using physical vapor deposition (PVD) to form a titanium nitride layer. Since the second metal layer 140 is incident not only to the mirror 230 incident from the light source but also to a portion other than the portion where the mirror 230 is formed, a light leakage current flows into the active matrix 100 to cause the device to malfunction. prevent. In addition, a portion of the second metal layer 140 formed on the drain pad of the first metal layer 130 is etched through the photolithography process in consideration of the position where the via contact 190 is to be formed in the subsequent process. By forming a portion of the first protective layer 135.

The second passivation layer 145 is formed on the exposed first passivation layer 135 and the second metal layer 140. The second passivation layer 145 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 145 prevents damage to the active matrix 100 and the results formed on the active matrix 100 during subsequent processes.

An etch stop layer 150 is formed on the second passivation layer 145. The etch stop layer 150 prevents the second protective layer 145 and the like from being etched and damaged by the subsequent etching process. The etch stop layer 150 is formed by depositing nitride by low pressure chemical vapor deposition (LPCVD) to have a thickness of about 1000 to 2000 kPa.

The first sacrificial layer 155 is formed on the etch stop layer 150. The first sacrificial layer 155 serves to facilitate stacking of thin films for forming the actuator 210. The first sacrificial layer 155 is formed by depositing amorphous silicon or poly ploy silicon at a temperature of about 600 ° C. by low pressure chemical vapor deposition (LPCVD). In forming the first sacrificial layer 155, since amorphous silicon itself has a smooth surface, when the first sacrificial layer 155 is formed using amorphous silicon, a separate planarization process is not required. When amorphous silicon is deposited to a thickness of about 1.0 μm, formation of the first sacrificial layer 155 is completed. On the other hand, since polysilicon has irregular characteristics, when the first sacrificial layer 155 is formed using polysilicon, the polysilicon is deposited to a thickness of about 2.0 to 3.0 μm, and then spin on glass. (SOG) or chemical mechanical polishing (CMP) method using the first surface of the poly-silicon 155, the surface is polished and planarized so that the thickness of the first sacrificial layer 155 is about 1.0㎛ Do.

Subsequently, after applying and patterning a first photoresist (not shown) on the first sacrificial layer 155 made of amorphous silicon or polysilicon as described above, the first photoresist is used as a mask. The actuator 210 may be exposed by etching a portion of the first sacrificial layer 155 adjacent to a portion of the second metal layer 140 having the opening 143 formed therein (see FIG. 5) to expose a portion of the etch stop layer 150. Anchor 182 is formed to support the. In this case, the first sacrificial layer 155 is patterned so that the edge of the anchor portion has a gentle slope to prevent the actuator 210 from bending due to the concentration of strain stress at the edge of the anchor 182 portion. As such a method, a method of performing dry etching and wet etching in sequence, a method of using a gray mask, or a method of reflowing a photoresist may be mentioned.

Referring to FIG. 6B, a first layer 164 is formed on the exposed etch stop layer 175 and on the first sacrificial layer 180. The first layer 164 is formed to have a thickness of about 0.1 μm to about 1.0 μm, preferably about 0.4 μm, using a hard material such as nitride or metal. The first layer 164 is formed using a low pressure chemical vapor deposition (LPCVD) method. In this case, the stress inside the first layer 164 is controlled by forming the first layer 164 while changing the ratio of the reactive gas by time in the reaction vessel of low pressure. The first layer 164 is later patterned into a support layer 165 having the shape of a 'T'.

After applying the second photoresist 167 on the first layer 164 by using a spin coating method, the second photoresist 167 is patterned to form a lower portion of the first layer 164. The portion adjacent to the portion where the opening 143 of the second metal layer 140 is formed is exposed in a quadrangular shape along a direction orthogonal to the direction in which the drain pad of the first metal layer 130 is formed. A lower electrode layer is formed on the exposed first layer 164 and on the first photoresist 167 by using a sputtering method or a chemical vapor deposition method, and then a location where the common electrode line 200 is subsequently formed. In consideration of this, the lower electrode layer is patterned so that the lower electrode 170 having a rectangular shape is formed on the exposed first layer 164. Accordingly, the lower electrode 170 is formed only at the center upper portion of the first layer 164. The lower electrode layer 169 is formed to have a thickness of about 0.1 μm to about 1.0 μm using a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) having electrical conductivity. Preferably, the lower electrode 170 is formed by depositing platinum-tantalum to a thickness of about 0.15㎛ using a sputtering method.

A second layer 174 is formed on the lower electrode 170 and the second photoresist 167. The second layer 174 is formed to have a thickness of about 0.1 μm to 1.0 μm using piezoelectric material ZrO ₂ , PZT, or PLZT. Preferably, the second layer is formed of PZT by a sol-gel method, and then the lower electrode 170 having a thickness of about 0.4 μm using a sputtering method or a chemical vapor deposition (CVD) method. And formed by depositing on the second photoresist 170. Subsequently, the piezoelectric material constituting the second layer 174 is subjected to heat treatment using a rapid heat treatment (RTA) method to phase change. The second layer 174 is later patterned into the strained layer 175.

An upper electrode layer 179 is formed on the second layer 174. The upper electrode layer 179 is formed using platinum, tantalum, or platinum-tantalum, which is a metal having electrical conductivity. The upper electrode layer 179 is formed to have a thickness of about 0.1 to 1.0 μm using a sputtering method. The upper electrode layer 179 is later patterned with the upper electrode 180 to which a second signal (bias signal) is applied.

Referring to FIG. 6C, after applying and patterning a third photoresist (not shown) on the upper electrode layer 179 by a spin coating method, the upper electrode layer 179 using the third photoresist as an etching mask. Is patterned into an upper electrode 180 having a rectangular shape. As a result, the upper electrode 180 is formed on the center of the first layer 164.

The second layer 174 is patterned into a strained layer 175 having a rectangular shape that is wider than the upper electrode 180 and smaller than the lower electrode 170 using the same method as the patterning of the upper electrode layer 179. do. In this case, a portion of the upper electrode 180 and the deformation layer 175 formed on the anchor 182 may protrude slightly from the lower electrode 170. In addition, the second photoresist 167 is removed.

The first layer 164 is also patterned into the support layer 165 in the same manner as above. Unlike the shape of the lower electrode 170, the support layer 165 has a 'T' shape, and the lower electrode 170 is formed on a central portion of the support layer 165. Next, the common electrode line 200 is formed on one side of the support layer 165. That is, after the fourth photoresist (not shown) is coated on the support layer 165 by spin coating, the fourth photoresist is patterned to expose one side of the support layer 165, and then platinum, tantalum, The common electrode line 200 is formed by using platinum-tantalum, aluminum, or silver. The common electrode line 200 is formed to have a thickness of about 0.5 to 2.0 µm using a sputtering method or a chemical vapor deposition method. In this case, the common electrode line 200 is spaced apart from the lower electrode 170 by a predetermined distance. Subsequently, the upper electrode connecting member 205 connecting the protruding portion of the common electrode line 200 and the upper electrode 180 to the lower electrode 170 using the same material and the same method as that of the common electrode line 200 is formed. Form. Therefore, the upper electrode connecting member 205 is spaced apart from the lower electrode 170 by a predetermined distance and does not contact the lower electrode 205.

In addition, when the fourth photoresist is patterned, the support layer 165 is exposed from the top of the portion where the opening 143 of the second metal layer 140 is formed to the portion where the lower electrode 170 is formed. The etch stop layer 150, the second passivation layer 145, and the first passivation layer 135 are etched from the support layer 165 to the drain pad of the first metal layer 130 vertically. After forming the via contact 204, a via contact 190 is formed from the drain pad to the support layer 165 in the via hole 185. At the same time, the lower electrode connecting member 195 is formed to be connected to the via contact 190 from the lower electrode 170 to the via hole 185. Therefore, the via contact 190, the lower electrode connecting member 195, and the lower electrode 170 are connected to each other so that the upper electrode 180, the strain layer 175, and the lower electrode 170 as shown in FIG. 4. And an actuator 210 including a support layer 165 is formed on the front surface of the active matrix 100. The via contact 190 and the lower electrode connecting member 195 are formed using a sputtering method or a chemical vapor deposition method. The via contact 190 and the lower electrode connecting member 195 are formed using platinum, tantalum, or platinum-tantalum, which is a metal having electrical conductivity. In this case, the lower electrode connecting member 195 is formed to have a thickness of about 0.5 to 1.0㎛. Accordingly, the first signal is externally connected to the lower electrode 170 through the MOS transistor embedded in the active matrix 100, the drain pad of the first metal layer 130, the via contact 190, and the lower electrode connecting member 195. Is applied to.

Subsequently, the backside metal layer 240 including the tantalum layer 238 and the platinum layer 239 is formed on the rear surface of the active matrix 100 having the actuator 210 formed on the front surface as described above. The tantalum layer 238 is formed by depositing tantalum to a thickness of about 500 to 1000 Pa using a sputtering method or a chemical vapor deposition method. Next, platinum is deposited on the tantalum layer 238 to a thickness of about 1500 to 2000 mW using a sputtering method or a chemical vapor deposition method to form a platinum layer 239. The tantalum layer 238 serves to bond the active matrix 100, which is a silicon wafer, to the platinum layer 239, and a bias voltage is applied to the platinum layer 239 to the active matrix 100. It prevents reverse current from flowing into the built-in MOS transistor.

Next, a TCP (Tape Carrier Package) (not shown) bonding for applying a second signal (bias signal) to a subsequent upper electrode 180 while simultaneously applying a first signal (image signal) to the lower electrode 170. The active matrix 100 is diced in preparation for bonding. At this time, only the thickness of about 200 μm, which is about 의 of the thickness of the active matrix 100, is cut for the subsequent process. The pad portion of the AMA panel is etched to expose a pad (not shown) of the AMA panel required for TCP bonding. Subsequently, the first sacrificial layer 155 made of amorphous silicon or polysilicon is maintained at a pressure of 3 to 5T in the expansion chamber and bromine fluoride (BF ₃ ) or xenon fluoride (BF ₃ ) at a rate of 1 pulse every minute. By using XeF ₂ ), the first air gap 160 is formed at the position of the first sacrificial layer 155.

Conventionally, there is a problem that the first sacrificial layer may not be properly removed due to the silica layer generated on the surface of the first sacrificial layer made of polysilicon under the influence of the subsequent process. However, in the present invention, the first sacrificial layer 155 is maintained by using bromine fluoride (BF ₃ ) or xenon fluoride (XeF ₂ ) at about 5 pulses at a rate of 1 pulse every minute while maintaining the pressure in the expansion chamber at about ₃ to 5 T. Since the silica layer is formed on the surface of the first sacrificial layer 155, the first sacrificial layer 155 may be easily removed.

Referring to FIG. 6D, the second sacrificial layer 215 is formed on the actuator 210 formed on the entire surface of the active matrix 100 as described above. The second sacrificial layer 215 serves to facilitate lamination of the metal layer to form the mirror 230 and the post 220. The second sacrificial layer 215 is formed by depositing amorphous silicon or polysilicon at a temperature of about 600 ° C. by low pressure chemical vapor deposition (LPCVD). The process of forming the second sacrificial layer 155 is the same as that of the first sacrificial layer 155 described above. In this case, the second sacrificial layer 215 is formed to have a sufficient thickness so as to completely cover the upper electrode 180 while filling the first air gap 160.

Subsequently, the second sacrificial layer 215 is patterned in consideration of the position where the post 220 is to be formed to expose a portion of the upper electrode 180. In this case, like the anchor 182, the second sacrificial layer 215 pattern has a gentle slope.

Referring to FIG. 6F, a post 220 is formed of aluminum, platinum, or silver, preferably aluminum, which is a reflective metal on one side of the exposed upper electrode 180 and on the second sacrificial layer 215. ) And the mirror 230 are formed at the same time. Post 220 and mirror 230 are formed using a sputtering method or a chemical vapor deposition method. The mirror 230 reflecting light incident from a light source (not shown) has a thickness of about 0.7 to 1.5 μm. Since the post 220 also has a gentle slope along the pattern of the second sacrificial layer 215 having a gentle slope, stress is applied to the edges of the post 220 when the mirror 230 and the post 220 are formed. Concentration can prevent cracking from occurring at these corner portions. Subsequently, after the mirror 230 is patterned to have a rectangular shape, the second sacrificial layer 215 is removed. Since the second sacrificial layer 215 also maintains the pressure in the expansion chamber at about ₃ to 5T and is removed by using bromine fluoride (BF ₃ ) or xenon fluoride (XeF ₂ ) at about 5 pulses at a rate of 1 pulse every minute, Even if a silica layer is formed on the surface of the second sacrificial layer 215, the second sacrificial layer 215 may be easily removed.

As described above, when the second sacrificial layer 215 is removed, a second air gap 250 is formed between the actuator 210 and the mirror 230. In the above-described process, after the first sacrificial layer 155 is removed, the second sacrificial layer 215 is formed and removed, but the second sacrificial layer 155 is formed on the second sacrificial layer 155. After the 215 is formed, the second sacrificial layer 215 and the first sacrificial layer 155 may be simultaneously removed using bromine fluoride or xenon fluoride.

In addition, the active matrix 100 having the actuator 210 and the backside metal layer 240 is completely cut out, and then cleaned and dried to complete the AMA device.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal transmitted from the outside is lowered through the MOS transistor embedded in the active matrix 100, the drain pad of the first metal layer 130, and the via contact 190. Is applied to the electrode 170. At the same time, a second signal is applied to the upper electrode 180 from the outside to generate an electric field according to the potential difference between the upper electrode 180 and the lower electrode 170. Due to this electric field, the deformation layer 175 formed between the upper electrode 180 and the lower electrode 170 causes deformation. The strained layer 175 contracts in a direction orthogonal to the electric field, whereby the actuator 210 is bent at a predetermined angle. Since the mirror 230 is formed on the actuator 210, the mirror 230 is tilted at the same angle as the actuator 210. Therefore, the mirror 230 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit and is projected onto the screen to form an image.

As described above, according to the present invention, even if a silica layer is formed due to a process subsequent to the surfaces of the first sacrificial layer and the second sacrificial layer made of polysilicon or the like, the pressure in the expansion chamber is maintained at about 3 to 5T every minute. Bromine fluoride or xenon fluoride can be easily removed using bromine fluoride or xenon fluoride at a rate of about 1 pulse to improve the yield of the process.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (2)

Providing an active matrix with M × N (M, N is an integer) embedded therein; Forming a first metal layer on the active matrix, the first metal layer including a drain pad extending from the drain of the MOS transistor; Forming a first sacrificial layer using amorphous silicon or polysilicon on top of the active matrix; After patterning the first sacrificial layer, forming an actuator including a support layer, a lower electrode, a strain layer, and an upper electrode on the patterned first sacrificial layer; Forming a backside metal layer on a back surface of the active matrix; Maintaining the pressure in the expansion chamber at about ₃ to 5T and removing the first sacrificial layer using bromine fluoride (BF ₃ ) or xenon fluoride (XeF ₂ ) at a rate of 5 pulses at a rate of 1 pulse every minute; Forming a second sacrificial layer on the actuator by spin coating; Patterning the second sacrificial layer to expose a portion of the upper electrode; Forming a post and a mirror over the exposed top electrode and the second sacrificial layer; And And removing the second sacrificial layer. Providing an active matrix with M × N (M, N is an integer) embedded therein; Forming a first metal layer on the active matrix, the first metal layer including a drain pad extending from the drain of the MOS transistor; Forming a first sacrificial layer using amorphous silicon or polysilicon on top of the active matrix; After patterning the first sacrificial layer, forming an actuator including a support layer, a lower electrode, a strain layer, and an upper electrode on the patterned first sacrificial layer; Forming a backside metal layer on a back surface of the active matrix; Forming a second sacrificial layer on top of the actuator; Patterning the second sacrificial layer to expose a portion of the upper electrode; Forming a post and a mirror over the exposed top electrode and the second sacrificial layer; And The first sacrificial layer and the second sacrificial layer are removed using bromine fluoride (BF ₃ ) or xenon fluoride (XeF ₂ ) at about 5 pulses at a rate of 1 pulse every minute while maintaining the pressure in the expansion chamber at about ₃ to 5T. Method of manufacturing a thin film-type optical path control device comprising the step of.