KR100257605B1 - Method for manufacturing thin film actuated mirror array - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film actuated mirror array is to prevent the electrical short between an upper electrode and a lower electrode when forming an etching stop layer. CONSTITUTION: An active matrix(100) includes the first metallic layer(105) extended from a source and a drain of a transistor, the first passivation layer(110) formed on the first metallic layer, the second metallic layer(115) formed on the first passivation layer, the second passivation layer(120) formed on the second metallic layer, and an etching stop layer(125) formed on the second passivation layer. An actuator(200) includes a supporting layer(140) with one side contacted with a drain pad of the first metallic layer and an air gap(185) interposed between the other side and the first metallic layer, a lower electrode(145) formed on the supporting layer, a transformed layer(150) formed on the lower electrode, an upper electrode(155) formed on the transformed layer, and a via contact(165) formed in a via hole(160) vertically formed from one side of the transformed layer to a drain pad of the first metallic layer through the lower electrode, the supporting layer, the etching stop layer, and the second and first passivation layers.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using an Actuated Mirror Array (AMA), and more particularly, to an etching protective layer for preventing hydrogen fluoride (HF) vapor from penetrating the IsoCut portion of the lower electrode. In forming, the present invention relates to a method for manufacturing a thin film type optical path control device capable of preventing an electrical short between an upper electrode and a lower electrode.

Spatial light modulators, which are devices for projecting optical energy onto a screen, can be applied to various fields such as optical communication, image processing, and information display devices. An image processing apparatus using such an optical path adjusting device or a spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Examples of the projection image display apparatus include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. The AMA reflects the light incident from the light source at each angle installed in the mirrors, and the reflected light is projected on the screen through an aperture such as a slit or pinhole to be imaged. The device can adjust the luminous flux to bear. Therefore, its structure and operation principle are simple, and high light efficiency (10% or more) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted on top thereof is inclined. Thus, the inclined mirrors reflect the incident light at a predetermined angle to form an image on the screen. As an actuator for driving the respective mirrors, piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used. It is also possible to configure the actuator as electrostrictive material such as PMN (Pb (Mg, Nb) O 3).

These AMA devices are largely divided into bulk type and thin film type. Bulk light path control devices are disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode therein into an active matrix in which a transistor is built, and then processing by using a sawing method and installing a mirror on the top. . However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. Such a thin film type optical path control device is disclosed in Patent Application No. 96-42197 filed by the applicant of the Korean Patent Office on September 24, 1996 (name of the invention: thin film type optical path control device that can control the stress of the membrane and its manufacturing method). Is disclosed.

Figure 1b shows a cross-sectional view of the thin film type optical path control device described in the preceding application.

Referring to FIG. 1B, the thin film type optical path adjusting device includes an active matrix 1 and an actuator 60. The active matrix 1 in which M x N (M, N is an integer) MOS transistors and a drain pad 5 extending from the drain region of the transistor is formed in the active matrix 1 and the drain pad 5. The protective layer 10 stacked on top of the protective layer 10 and the etch stop layer 15 stacked on the protective layer 10 is included.

The actuator 60 has a membrane 30 and a membrane 30 horizontally formed at one side thereof in contact with a portion of the etch stop layer 15 in which the drain pad 5 is formed and the other side thereof horizontally through the air gap 25. Of the lower electrode 35 stacked on top of the lower electrode 35, the strained layer 40 stacked on top of the lower electrode 35, the upper electrode 45 stacked on top of the strained layer 40, and the strained layer 40. The lower electrode 35 and the drain pad in the via hole 50 vertically formed from one side to the drain pad 5 through the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. 5) comprises a via contact 55 formed to be electrically connected to each other.

A stripe 46 is formed on a part of the upper electrode 45. The stripe 46 operates the upper electrode 45 uniformly so that the light incident from the light source is diffusely reflected at the boundary between the portion of the upper electrode 45 which is deformed and the portion which is not deformed according to the deformation of the deforming layer 40. prevent.

Hereinafter, the manufacturing method of the above-mentioned thin film type optical path control apparatus is demonstrated with reference to FIGS. 1A-1B.

Referring to FIG. 1A, an silicate is formed on an active matrix 1 in which M x N (M, N is an integer) MOS transistors (not shown) are formed and a drain pad 5 extending from the drain region of the transistor is formed. A protective layer 10 made of glass PSG is formed. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded during the subsequent process.

An etch stop layer 15 made of nitride is formed on the passivation layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 μm by using an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby making a position where the support of the actuator 60 is to be formed.

The membrane 30 is formed on the exposed etch stop layer 15 and the sacrificial layer 20 to a thickness of about 0.1 to 1.0㎛. Membrane 30 is formed using low pressure chemical vapor deposition (LPCVD). At this time, the membrane 30 is formed while varying the ratio of the reaction gas in the reaction vessel at a low pressure to control the stress in the membrane 30.

On the membrane 30, a lower electrode 35 made of metal such as platinum (Pt), tantalum (Ta), platinum-tantalum, or the like is formed. The lower electrode 35 is formed to have a thickness of about 0.1 to 1.0 μm using a sputtering method. Subsequently, the lower electrode 35 is patterned to separate the lower electrode 35 for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso­Cut etching process).

On the lower electrode 35, a strained layer 40 made of a piezoelectric material such as PZT or PLZT is formed. The strained layer 40 is formed to have a thickness of about 0.1 μm to about 1.0 μm, preferably about 0.4 μm using a sol-gel method, and then phase-shifted by a rapid heat treatment (RTA) method. In the strained layer 40, a second signal (bias signal) is applied to the upper electrode 45, and a first signal is applied to the lower electrode 35, according to a potential difference between the upper electrode 45 and the lower electrode 35. It is deformed by the generated electric field.

The upper electrode 45 is formed on the strained layer 40. The upper electrode 45 is formed of a metal having electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 0.1 to 1.0 μm using a sputtering method. The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. In addition, the upper electrode 45 also functions as a mirror that reflects light incident from the light source.

Referring to FIG. 1B, the upper electrode 45, the strained layer 40, and the lower electrode 35 are each patterned into a predetermined pixel shape. At this time, a portion of the upper electrode 45 is patterned to form a stripe 46. Subsequently, the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 are sequentially formed from one side of the strained layer 40 to the top of the drain pad 5. The via hole 50 is formed by etching. Subsequently, a metal contact such as tungsten, platinum or titanium is sputtered into the via hole 50 to form a via contact 55 that electrically connects the drain pad 5 and the lower electrode 35. Thus, the via contact 55 is formed vertically from the lower electrode 35 to the drain pad 5 in the via hole 50. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1.

Subsequently, the membrane 30 is patterned to have a predetermined pixel shape. After the air gap 25 is formed at the position of the sacrificial layer 20 by etching the sacrificial layer 20 by 49% hydrogen fluoride vapor, a cleaning and drying process is performed to remove the remaining etching solution. This completes the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. At the same time, a second signal is applied to the upper electrode 45 through the common electrode line to generate an electric field between the upper electrode 45 and the lower electrode 35. By the electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the generated electric field, and the actuator 60 including the strained layer 40 is bent upward at a predetermined angle. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described thin film type optical path control apparatus, when the etching process for patterning the strained layer, the lower electrode, and the membrane into a pixel shape is performed, a problem occurs in that Iso­Cut portion of the lower electrode is damaged. This will be described in more detail with reference to the drawings.

2 is an enlarged plan view of an Iso­Cut part in the above-described thin film type optical path adjusting device. Referring to FIG. 2, in the above-described method for manufacturing a thin film type optical path control apparatus, an IsoCut part (eg, an IsoCut part) may be used to perform etching processes for patterning the deformable layer 40, the lower electrode 35, and the membrane 30 into a predetermined pixel shape. A) is exposed without being covered with a photoresist film. Therefore, during the etching processes described above, the membrane 30 of the Iso­Cut part A is over-etched and etched down to the lower etch stop layer. As a result, when etching the sacrificial layer using hydrogen fluoride vapor, hydrogen fluoride vapor penetrates through the etched portion of the etch stop layer, resulting in damage to the protective layer and the active matrix.

Recently, in order to prevent the Iso ICut portion from being damaged, a method of depositing an etch protective layer made of a material such as amorphous silicon after patterning the pixel shape to the membrane, leaving an etch protective layer of the Iso­Cut portion, and etching the rest has been proposed. Since the etch protection layer is made of a material (amorphous silicon) that is not etched during the subsequent etching process with hydrogen fluoride vapor, hydrogen fluoride vapor can be prevented from penetrating through the Iso­Cut part. The etch protective layer is removed by a blanket etch method after performing an etching process with hydrogen fluoride vapor. However, according to the above method, since the thickness of the etch protective layer formed on the stepped surface of the upper electrode and the lower electrode is relatively thicker than the thickness at other portions, the upper electrode and the lower electrode after removing the etch protective layer by the blanket etching method. An etching protection layer remains on the stepped surface of the electrode. Thus, a problem arises in which electrical short is caused between the upper electrode and the lower electrode.

Therefore, an object of the present invention, in forming an etch protective layer for preventing the penetration of hydrogen fluoride vapor in the IsoCut portion of the lower electrode, the thin film type optical path control that can prevent the electrical short between the upper electrode and the lower electrode It is to provide a method of manufacturing the device.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is an enlarged plan view illustrating an IsoutCut part in the thin film type optical path adjusting device described in the preceding application. FIG.

3 is a plan view of a thin film type optical path control apparatus according to the present invention.

4 is an enlarged perspective view of the apparatus shown in FIG. 3.

FIG. 5 is a cross-sectional view of the apparatus shown in FIG. 3 taken along line A′A ′.

6A to 6D are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 5.

<Explanation of symbols for main parts of the drawings>

100: active matrix 105: first metal layer

110: first protective layer 115: second metal layer

120: second protective layer 125: etch stop layer

135: sacrificial layer 140: support layer

145: lower electrode 150: strained layer

155: upper electrode 160: via hole

165: beer contact 170: short film

175: etching protection layer 180: mirror

185: air gap 200: actuator

In order to achieve the above object of the present invention, there is provided a method comprising: providing an active matrix including a drain pad in which M x N (M, N is an integer) embedded therein and extending from the drain of the transistor; Forming a sacrificial layer on top of the active matrix; Sequentially forming a first layer, a lower electrode layer, a second layer, and an upper electrode layer on the sacrificial layer; Iii) forming the upper electrode by patterning the upper electrode layer into a pixel shape, ii) patterning the second layer into a wider pixel shape than the upper electrode to form a strained layer, iii) making the lower electrode layer wider than the strained layer. Forming an actuator by patterning into a pixel shape to form a lower electrode, and iii) forming a support layer by patterning the first layer into a wider pixel shape than the lower electrode; Forming a mirror on top of the support layer; Patterning the anti-short film by forming a short anti-film on top of the actuator and the mirror, using a mask of a size used for patterning the lower electrode layer and a mask used for patterning the upper electrode layer; Forming an etch protective layer on the anti-short film; Patterning the etch protective layer using a blanket dry etching method so as to expose a portion of the anti-short film after removing the sacrificial layer; And it provides a method for manufacturing a thin film type optical path control device comprising the step of removing the short prevention film.

According to the present invention, after forming a mirror on top of the support layer, on the resultant, preferably, a shot prevention film is formed by using photoresist. After the anti-short film is patterned by using a mask of a middle size between the upper electrode and the lower electrode, an etch protective layer is deposited on the upper layer, and the etch protective layer is patterned by a photolithography process. The anti-short film is removed by an ashing method after the removal process of the sacrificial layer performed using hydrogen fluoride vapor. At this time, since the etching protection layer formed in the form of a spacer on the stepped surface of the strain layer between the upper electrode and the lower electrode is also removed, it is possible to prevent the electrical short between the upper electrode and the lower electrode caused by the etching protection layer. .

Moreover, the amorphous silicon constituting the etch protection layer of the present invention can be easily applied on top of the anti-short film by using a plasma enhanced chemical vapor deposition (PECVD) method at a low temperature of about 100 ° C, so that the method of the present invention is easy. Can be performed.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

Figure 3 is a plan view of a thin film type optical path control apparatus according to the present invention, Figure 4 shows an enlarged perspective view of the device shown in Figure 3, Figure 5 is a AA 'line of the device shown in Figure 3 It shows a cut section.

3, 4, and 5, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 200, and a mirror 180.

The active matrix 100 having M x N (M, N is an integer) embedded therein includes a first metal layer 105 and an upper portion of the first metal layer 105 extending from a source and a drain of the MOS transistor. The first protective layer 110, the second metal layer 115 formed on the first protective layer 110, the second protective layer 120 formed on the second metal layer 115, and the second protective layer 120. It includes an etch stop layer 125 formed on the top. The first metal layer 105 includes a drain pad extending from the drain of the MOS transistor, and the second metal layer 115 is formed of a titanium (Ti) layer and a titanium nitride (TiN) layer.

Referring to FIG. 4, the actuator 200 has one side in contact with a portion of the etch stop layer 125 in which a drain pad of the first metal layer 105 is formed and the other side is horizontally formed through the air gap 185. The support layer 140, the lower electrode 145 formed on the support layer 140, the strained layer 150 formed on the lower electrode 145, the upper electrode 155 formed on the strained layer 150, and From one side of the strained layer 150 through the strained layer 150, the lower electrode 145, the support layer 140, the etch stop layer 125, the second protective layer 120 and the first protective layer 110. The via contact 160 includes a via contact 165 formed to connect the lower electrode 145 and the drain pad to the via hole 160 vertically up to the drain pad of the metal layer 105. The support layer 140 performs the function of a membrane supporting the actuator of the thin film optical path control device described in the previous application.

The support layer 140 has a shape in which a rectangular flat plate is integrally formed with the arms on the same plane between two rectangular arms formed in parallel from both support portions. The mirror 180 is formed on the rectangular flat plate of the support layer 140. Thus, the mirror 180 has the shape of a rectangular flat plate.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

6a to 6d show a manufacturing process of the thin film type optical path control apparatus according to the present invention.

Referring to FIG. 6A, after preparing an active matrix 100, which is an n-type doped silicon (Si) wafer, the active matrix 100 is prepared using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer for forming an active region and a field region is formed on the substrate. Subsequently, after forming a gate made of a conductive material such as polysilicon doped with impurities on top of the active region, p ⁺ sources and drains are formed by an ion implantation process, thereby forming M x N (M and N are integers) MOS. Form a transistor.

After forming an insulating film made of an oxide on the resultant formed MOS transistor, the openings for exposing the top of one side of the source and the drain are formed by a photolithography process. Subsequently, a first metal layer 105 made of a metal such as titanium, titanium nitride, or tungsten (W) is deposited on the resultant, on which the openings are formed, and then the first metal layer 105 is patterned by a photolithography process. The first metal layer 105 patterned as described above includes a drain pad extending from the drain of the MOS transistor to one side of the support of the actuator 200.

The first passivation layer 110 is formed on the first metal layer 105. The first passivation layer 110 is formed to have a thickness of about 8000 GPa by using the silicate glass (PSG) chemical vapor deposition (CVD) method. The first protective layer 110 prevents damage to the active matrix 100 in which the MOS transistor is embedded during the subsequent process.

The second metal layer 115 is formed on the first protective layer 110. In order to form the second metal layer 115, first, a titanium layer is formed by sputtering titanium (Ti) to a thickness of about 300 μm. Subsequently, titanium nitride is deposited on top of the titanium layer using a physical vapor deposition (PVD) method to form a titanium nitride layer. The second metal layer 115 prevents light leakage current from flowing through the active matrix 100 because light incident from the light source is incident not only on the mirror 180 but also on a portion other than the portion where the mirror 180 is formed. . Subsequently, a portion of the second metal layer 115 in which the via contact 165 is to be formed in a subsequent process is etched through a photolithography process to form an opening in the second metal layer 115.

The second passivation layer 120 is formed on the second metal layer 115. The second protective layer 120 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 120 also prevents damage to the active matrix 100 in which the MOS transistor is embedded and the results formed on the active matrix 100 during the subsequent process.

An etch stop layer 125 is formed on the second passivation layer 120. The etch stop layer 125 prevents the active matrix 100 and the second passivation layer 120 from being etched due to the subsequent etching process. The etch stop layer 125 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

The sacrificial layer 135 is formed on the etch stop layer 125. The sacrificial layer 135 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to about 3.0 μm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 135 covers the upper portion of the active matrix 100 in which the MOS transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 135 is planarized by polishing the surface of the sacrificial layer 135 using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method so that the thickness of the sacrificial layer 135 is about 1 .mu.m. .

Subsequently, the portion of the sacrificial layer 135 having the opening of the second metal layer 115 formed thereon and an adjacent portion thereof are etched to expose a portion of the etch stop layer 125, thereby anchoring an anchor which is a support of the actuator 200. Make a position to form.

A first layer is formed on the exposed etch stop layer 125 and on the sacrificial layer 135. The first layer is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD). The first layer is later patterned into the support layer 140.

The lower electrode layer is formed on the first layer using a metal such as platinum, tantalum, or platinum-tantalum (Pt-Ta), which is a metal having excellent electrical conductivity. The lower electrode layer is formed to have a thickness of about 0.01 to 1.0 탆 using the sputtering method. Subsequently, the lower electrode layer is separated for each pixel so that an independent first signal is applied to each pixel (Iso­Cut process). The lower electrode layer is later patterned into the lower electrode 145. The first signal transferred from the transistor embedded in the active matrix 100 is applied to the lower electrode 145.

The second layer is stacked on the lower electrode layer. The second layer is formed using a piezoelectric material such as PZT or PLZT so as to have a thickness of 0.1 to 1.0 mu m, preferably about 0.4 mu m. The second layer is formed using a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method, and then subjected to a phase change by heat treatment using a rapid heat treatment (RTA) method. The second layer is later patterned into strained layer 150. The deforming layer 150 is applied to an electric field generated by a second signal applied to the upper electrode 155 and a first signal applied to the lower electrode 145 according to a potential difference between the upper electrode 155 and the lower electrode 145. Cause deformation.

An upper electrode layer is stacked on top of the second layer. The upper electrode layer is formed of a metal having electrical conductivity and reflectivity, such as platinum, aluminum, or silver, to have a thickness of about 0.01 to 1.0 탆 using a sputtering method.

After the first photoresist (not shown) is applied to the upper electrode layer by spin coating, the upper electrode layer is patterned to have a mirror-shaped 'c' shape as shown in FIG. An electrode 155 is formed. The second signal is applied to the upper electrode 155 through a common electrode line (not shown) from the outside. Subsequently, after the first photoresist is removed, a second photoresist (not shown) is applied to the patterned upper electrode 155 and the second layer by spin coating, and then the second layer is the upper electrode 155. The strained layer 150 is formed by patterning the substrate to have a shape of 'c' that is slightly larger than the mirror image (see FIG. 4). Subsequently, after removing the second photoresist and applying a third photoresist (not shown) on top of the upper electrode 155, the strained layer 150, and the lower electrode layer by spin coating, the lower electrode layer is strained. The lower electrode 145 is formed by patterning the shape to have a shape of a mirror image 'c' slightly wider than 150.

Next, the strained layer 150, the lower electrode 145, the first layer, the etch stop layer 125, and the second passivation layer are formed from a portion of the strained layer 150 in which the opening of the second metal layer 115 is formed below. 120 and the first protective layer 110 are sequentially etched to form the via hole 160 from one side of the strained layer 150 to the drain pad of the first metal layer 105. A via contact 165 is formed to electrically connect the drain pad of the first metal layer 105 and the lower electrode 145 by sputtering a metal such as tungsten (W), platinum, aluminum, or titanium therein. . Therefore, the via contact 165 is formed from the lower electrode 145 to the top of the drain pad in the via hole 160. The first signal transmitted from the outside is applied to the lower electrode 145 through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 105, and the via contact 165.

Subsequently, after the fourth photoresist (not shown) is applied to the patterned lower electrode 145 and the upper part of the via hole 160 by a spin coating method, the portion extending from both sides of the first layer is the lower electrode. The central portion of the first layer having a slightly wider rectangular shape than the one at 145 and formed integrally therewith is patterned to have a rectangular flat plate shape to form the support layer 140. That is, as shown in FIG. 4, the support layer 140 has rectangular arms extending from both support portions, and a rectangular flat plate having a larger area between these arms has a shape formed integrally with the arms on the same plane. . Then, the fourth photoresist is removed. As a result of the patterning of the support layer 140 as described above, a portion of the sacrificial layer 135 is exposed.

Subsequently, after applying a fifth photoresist (not shown) on the exposed sacrificial layer 135 and the support layer 140 by spin coating, a rectangular flat plate, which is the center of the support layer 140, is exposed. Pattern as much as possible. In addition, a sputtering method or a chemical vapor deposition method is used to form a metal having reflective properties such as silver, platinum, or aluminum on the upper portion of the central portion of the rectangular exposed support layer 140 in a thickness of about 0.3 to 2.0 µm. By deposition. Subsequently, the deposited metal is patterned so that the deposited metal has the same shape as the center portion of the rectangular exposed support layer 140 to form the mirror 180, and then the fifth photoresist is removed.

Referring to FIG. 6B, after forming the mirror 180 as described above, the anti-short film 170 is formed on the resultant using a sputtering method. The anti-shot film 170 is preferably formed using a photoresist. The anti-short film 170 may easily remove the etch protective layer 175 that is not etched during the subsequent etching of the etch protective layer 175 and remains in the form of a spacer on the stepped surface of the strain layer between the upper electrode and the lower electrode. Do this. The anti-short film 170 is patterned by using a mask having a medium size between a mask used when patterning the upper electrode 155 and a mask used when patterning the lower electrode 145. In this case, the anti-short film 170 is formed not only on the upper electrode 155 but also on the stepped surface of the strain layer 150 between the upper electrode 155 and the lower electrode 145.

Referring to FIG. 6C, an etch protection layer 175 is formed on the resultant. The etching protection layer 175 may be formed of a material that is not etched during the etching of the sacrificial layer 135 using hydrogen fluoride vapor. More preferably, the amorphous silicon may be plasma-enhanced chemical vapor deposition (PECVD). To form. Amorphous silicon is a material suitable for the present invention because it can be deposited at a low temperature of about 100 ℃ when using the plasma-enhanced chemical vapor deposition method, and can be easily applied on the anti-short film 170.

The sacrificial layer 135 is then etched using hydrogen fluoride vapor to form an air gap 185 at the location of the sacrificial layer 135. In this case, since the Iso­Cut part is covered with an etch protection layer 175 made of amorphous silicon, which is a material that is not etched in the hydrogen fluoride vapor, hydrogen fluoride vapor can be prevented from penetrating through the Iso­Cut part.

Subsequently, the etch protection layer 175 is removed by a blanket dry etch method. In this case, since the thickness of the etching protection layer 175 formed on the stepped surfaces of the upper electrode 155 and the lower electrode 145 is relatively thicker than the thickness at other portions, the etching protection layer 175 is blanket-etched. After the removal, the etch protection layer 175 remains on the stepped surfaces of the upper electrode 155 and the lower electrode 145.

Referring to FIG. 6D, after performing a rinse and dry process, the anti-short film 170 may be removed by an ashing method to complete the thin film type optical path control apparatus. When the anti-short film 170 is removed, the etch protection layer 175 remaining in the spacer form on the stepped surface of the deformation layer 150 is removed together, so that the upper electrode 155 and the lower electrode due to the remaining etch protection layer 175 are removed. There is no electrical short between the 145s.

In the above-described thin film type optical path control device according to the present invention, a second signal is applied to the upper electrode 155 through a common electrode line from the outside. At the same time, the first signal is applied to the lower electrode 145 through the transistor embedded in the active matrix 100 from the outside, the drain pad of the first metal layer 105, and the via contact 165. An electric field is generated between the electrodes 145 according to the potential difference. Due to this electric field, the deformation layer 150 formed between the upper electrode 155 and the lower electrode 145 causes deformation. The strained layer 150 contracts in a direction orthogonal to the generated electric field, and thus the actuator 200 including the strained layer 150 and the support layer 140 is bent at a predetermined angle. Since the mirror 180 reflecting the light incident from the light source is formed above the central portion of the support layer 140, the mirror 180 is bent at the same angle as the actuator 200. Accordingly, the mirror 180 reflects the incident light at a predetermined angle, and the reflected light passes through the slit and is projected onto the screen to form an image.

As described above, according to the present invention, after applying the anti-short film to the upper portion of the mirror formed result, an etching protective layer for preventing hydrogen fluoride vapor from penetrating the Iso­Cut portion of the lower electrode. When the etch protective layer is etched by the blanket dry etching method, the etch protective layer remains in the form of a spacer on the sidewall of the anti-short film without contacting the stepped surface of the strained layer. Subsequently, when the anti-short film is removed by an ashing method, the etch protection layer remaining in the form of a spacer is also removed. Therefore, it is possible to prevent the electrical short between the upper electrode and the lower electrode due to the etching protection layer remaining in the spacer form on the stepped surface of the strained layer.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

Claims (4)

Providing an active matrix comprising M × N (M, N is an integer) embedded MOS transistors and including drain pads extending from the drains of the transistors; Forming a sacrificial layer on top of the active matrix; Sequentially forming a first layer, a lower electrode layer, a second layer, and an upper electrode layer on the sacrificial layer; Iii) forming an upper electrode by patterning the upper electrode layer in a pixel shape, ii) forming a strained layer by patterning the second layer in a wider pixel shape than the upper electrode, and iii) forming the strained layer in the lower electrode layer. Patterning the lower electrode by patterning the substrate in a wider pixel shape than the strained layer, and iii) forming an actuator by patterning the first layer in a wider pixel shape than the lower electrode; Forming a mirror on top of the support layer; Patterning the anti-short film by forming a short anti-film on top of the actuator and the mirror using a mask of a size used to mask the upper electrode layer and a mask used when patterning the lower electrode layer; Forming an etch protective layer on the anti-short film; Patterning the etch protective layer using a blanket dry etching method so as to expose a portion of the anti-short film after removing the sacrificial layer; And A method of manufacturing a thin film type optical path control device comprising the step of removing the short prevention film. The method of claim 1, wherein the forming of the anti-short film is performed using a photoresist. The method of claim 1, wherein the forming of the etch protective layer is performed by using plasma-enhanced chemical vapor deposition (PECVD). The method of claim 1, wherein the removing of the anti-short film is performed by using an ashing method.

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