KR100265947B1 - Method of manufacturing tma - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film actuated mirror array is to prevent a crack from being generated at a deformation layer in an etching process, and the deformation layer from being etched by hydrogen fluoride vapor. CONSTITUTION: An active matrix(100) has an MxN transistor installed therein, and a drain pad formed on one side thereof. The first layer is formed on the active matrix. A lower electrode layer is formed and patterned on the first layer, thereby forming a lower electrode(140). An insulating line(145) is formed by performing an O2 ion implantation along the interface line of the lower electrode and an Iso-Cut part among the lower electrodes. The second layer is formed and patterned on the lower electrode and the insulating line, thereby forming a deformation layer(150). An upper electrode layer is deposited and patterned on the deformation layer, thereby forming an upper electrode(155). A support layer(135) is formed by patterning the first layer. A mirror(175) is formed on the support layer.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using an Actuated Mirror Array (AMA), and more particularly, to prevent cracks in the strain layer during a subsequent etching process, and the strain layer is fluorinated. The present invention relates to a method for manufacturing a thin film type optical path control device capable of preventing etching by hydrogen vapor.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, such devices are classified into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen.

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1% to 2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. The AMA reflects the light incident from the light source at each angle installed in the mirrors, and the reflected light is projected on the screen through an aperture such as a slit or pinhole to be imaged. The device can adjust the luminous flux to bear. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the electrical first signal (image signal) and the second signal (bias signal) applied. As the actuator deforms, each of the mirrors mounted on top thereof is inclined. Therefore, the inclined mirrors reflect the light incident from the light source at a predetermined angle to form an image on the screen. As an actuator for driving the respective mirrors, a piezoelectric material such as PZT (Pb (Zr, Ti) O ₃ ), or PLZT ((Pb, La) (Zr, Ti) O ₃ ) is used. An actuator may also be configured by using a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. Bulk light path control devices are disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, such a bulk light path adjusting device requires a very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. Such a thin film type optical path control device is disclosed in Korean Patent Application No. 97-11058 (name of the invention: a method of manufacturing a thin film type optical path control device) filed by the present applicant with the Korean Patent Office.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the preceding application.

Referring to FIG. 1B, the thin film type optical path adjusting device includes an active matrix 10 and an actuator 40 formed on the active matrix 10.

The active matrix 10 includes a first metal layer 15 and a first metal layer 15 stacked on top of an active matrix 10 in which M × N (M and N are integers) MOS transistors (not shown) are embedded. ) The first protective layer 20 stacked on the upper portion of the second protective layer 20, the second metal layer 25 stacked on the upper portion of the first protective layer 20, and the second protective layer 30 stacked on the second metal layer 25. ), And an etch stop layer 35 stacked on the second passivation layer 30. The first metal layer 15 includes a drain pad for transmitting the first signal. The second metal layer 25 includes a first layer 25a made of titanium (Ti) and a second layer 25b made of titanium nitride (TiN).

The actuator 40 has a support layer 45 having a cross section formed in parallel with a lower portion of the active matrix 10 through an air gap 80 and having one side contacting a portion of the etch stop layer 35 at which a drain pad is formed. ), The lower electrode 50 stacked on the support layer 45, the strained layer 55 stacked on the lower electrode 50, the upper electrode 60 stacked on the strained layer 55, and Drain of the first metal layer 15 from one side of the strained layer 55 through the lower electrode 50, the support layer 45, the etch stop layer 35, the second protective layer 30, and the first protective layer 20. The via contact 75 may be formed to connect the lower electrode 50 and the drain pad in the via hole 70 vertically up to the pad.

The upper electrode 60 is uniformly operated on a part of the upper electrode 60 so that the light incident from the light source causes the boundary between the portion of the upper electrode 60 that is deformed and the portion that is not deformed due to the deformation of the strained layer 55. A stripe 65 is formed to prevent diffuse reflection at.

Hereinafter, a manufacturing method of the thin film type optical path control device will be described with reference to FIGS. 1A to 1B.

Referring to FIG. 1A, a first metal layer 15 is formed on an active matrix 10 having M × N MOS transistors (not shown). Subsequently, the first metal layer 15 is patterned to expose the gate 11 portion of the MOS transistor below it. Thus, the first metal layer 15 is connected to the drain 12 and the source 13 of the MOS transistor. The active matrix 10 is made of a semiconductor such as silicon or an insulating material such as glass or alumina (Al ₂ O ₃ ). The first metal layer 15 is made of tungsten (W) and includes a drain pad extending from the drain 12 of the transistor to one side of the support layer 45 formed later.

Subsequently, the first protective layer 20 is formed on the first metal layer 15 to protect the active matrix 10 having the transistor embedded therein. The first passivation layer 20 is formed of Phosphor-Silicate Glass (PSG) using a chemical vapor deposition (CVD) method. The first protective layer 20 prevents the transistor embedded in the active matrix 10 from being damaged during subsequent processing.

The second metal layer 25 is formed on the first protective layer 20. In order to form the second metal layer 25, first, the first layer 25a is formed by sputtering titanium (Ti). Titanium nitride (TiN) is formed on the first layer 25a by using a physical vapor deposition (PVD) method to form a second layer 25b. Since the light incident from the light source is incident on not only the upper electrode 60, which is a reflective layer, but also a portion except the portion where the upper electrode 60 is formed, the second metal layer 25 prevents photocurrent from flowing through the active matrix 10. do. Subsequently, a portion of the second metal layer 25 in which the via contact 75 is to be formed is etched in a subsequent process.

The second passivation layer 30 is stacked on the second metal layer 25. The second protective layer 30 is formed using phosphorus silicate glass PSG. The second protective layer 30 also prevents the transistor embedded in the active matrix 10 from being damaged during subsequent processing.

An etch stop layer 35 is stacked on the second passivation layer 30. The etch stop layer 35 is formed of a nitride using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 35 prevents the active matrix 10 and the second passivation layer 30 from being etched due to the subsequent etching process.

The sacrificial layer 40 is stacked on the etch stop layer 35. The sacrificial layer 40 forms phosphorus silicate glass (PSG) by an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 40 covers the upper portion of the active matrix 10 in which the transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 40 is planarized by using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method. Subsequently, a portion of the sacrificial layer 40 in which the drain pad of the first metal layer 15 is formed is etched to expose a portion of the etch stop layer 35.

The support layer 45 is stacked on the exposed etch stop layer 35 and on the sacrificial layer 40. The support layer 45 is formed of nitride using a low pressure chemical vapor deposition (LPCVD) method. Subsequently, the lower electrode 50 is stacked on the support layer 45. The lower electrode 50 is formed by sputtering a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). Subsequently, Iso­Cut is performed to apply an independent signal to the lower electrode 50 for each pixel. The first signal is applied to the lower electrode 50 through the transistor embedded in the active matrix 10 and the drain pad of the first metal layer 15 from the outside.

On top of the lower electrode 50, a strain layer 55 composed of PZT or PLZT is stacked. The strained layer 55 is formed using a sol-gel method, a sputtering method, or a chemical vapor deposition method (CVD). In addition, the strained layer 55 is heat-transferred by rapid thermal annealing (RTA) to cause phase shift. The strained layer 55 is deformed by an electric field generated between the upper electrode 60 and the lower electrode 50.

The upper electrode 60 is stacked on top of the strained layer 55. The upper electrode 60 is formed by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 60 through a common electrode line (not shown) from the outside. Since the upper electrode 60 has excellent electrical conductivity and reflectivity, not only a function of the bias electrode but also a mirror reflecting light incident from the light source is performed.

Subsequently, the upper electrode 60, the strained layer 55, and the lower electrode 50 are sequentially patterned into a predetermined pixel shape from the top of the upper electrode 60. At this time, a part of the upper electrode 60 is uniformly operated so that the light incident from the light source is not deformed from the portion of the upper electrode 60 which causes the deformation according to the deformation of the deformation layer 55. A stripe 65 is formed to prevent diffuse reflection at the boundary of the portion that is not.

The strained layer 55, the lower electrode 50, the support layer 45, the etch stop layer 35, the second protective layer 30, and the first protective layer 20 are sequentially etched from one side of the strained layer 55. The via hole 70 is vertically formed to the drain pad of the first metal layer 15. In the via hole 70, a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 75. The via contact 75 connects the drain pad of the first metal layer 15 and the lower electrode 50. Therefore, the first signal applied from the outside is applied to the lower electrode 50 through the transistor, the drain pad, and the via contact 75 embedded in the active matrix 10. Subsequently, the support layer 45 is patterned into a predetermined pixel shape.

The sacrificial layer 40 is etched using hydrogen fluoride (HF) vapor to form an air gap 80, followed by a rinse and dry treatment to complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal from the outside is applied to the lower electrode 50 through the transistor, the drain pad, and the via contact 75 embedded in the active matrix 10. In addition, a second signal is applied to the upper electrode 60 from the outside through the common electrode line to generate an electric field between the upper electrode 60 and the lower electrode 50. Due to this electric field, the strained layer 55 stacked between the upper electrode 60 and the lower electrode 50 causes deformation. The strained layer 55 contracts in a direction perpendicular to the generated electric field, and the actuator 40 including the strained layer 55 is bent upward. Therefore, the upper electrode 60 on the actuator 40 also inclines in the same direction. Light incident from the light source is reflected by the upper electrode 60 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described thin film type optical path control apparatus, when the etching process for patterning the strained layer, the lower electrode, and the support layer into a pixel shape is performed, the Iso­Cut portion of the lower electrode is damaged. This will be described in more detail with reference to the drawings.

2 is an enlarged plan view of an Iso­Cut part in the above-described thin film type optical path adjusting device. Referring to FIG. 2, in the above-described method for manufacturing a thin film type optical path adjusting device, an IsoCut part (eg, an IsoCut part) may be used to perform etching processes for patterning the deformable layer 55, the lower electrode 50, and the support layer 45 into a predetermined pixel shape. A) is exposed without being covered with a photoresist film. Accordingly, during the etching process, the supporting layer 45 of the IsooverCut part A is over-etched and etched down to the lower etch stop layer 35. As a result, when the sacrificial layer 40 is etched using the hydrogen fluoride vapor, hydrogen fluoride vapor penetrates through the etched portion of the etch stop layer 35 and the second protective layer 30 is damaged. .

In addition, according to the manufacturing method of the thin film type optical path control apparatus described above, since it becomes a nitride layer which is the Iso­Cut addition support layer 45, it has physical properties different from metals such as platinum (Pt) or tantalum constituting the lower electrode 50. In particular, since the strained layer 55 made of a piezoelectric material such as PZT has a property of not being deposited well on top of the nitride layer, voids occur in the Iso­Cut part. As described above, when a rapid heat treatment (RTA) process is performed to phase change the piezoelectric material constituting the strained layer while voids are formed in the strained layer, the strained layer is inflated to cause cracks in the strained layer. do. When cracks occur in the strained layer, not only the piezoelectric properties of the strained layer are lowered, but also a problem arises in that the upper electrode deposited thereon is short-circuited or a photolithography process for patterning the upper electrode cannot be reliably performed.

In addition, hydrogen fluoride vapor penetrates into the strain layer subsequent to the strain layer patterned into a predetermined pixel shape, thereby damaging the strain layer, which causes a short circuit between the upper electrode and the lower electrode.

Accordingly, it is an object of the present invention to provide a method of manufacturing a thin film type optical path control apparatus which can prevent cracks in a strained layer during a subsequent etching process and prevent the strained layer from being etched by hydrogen fluoride vapor. .

1A and 1B are cross-sectional views for explaining a method for manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

2 is an enlarged plan view of an Iso-Cut part in the above-described thin film type optical path adjusting device.

3 is a plan view of a thin film type optical path control apparatus according to the present invention.

4 is a cross-sectional view taken along the line B-B 'of the apparatus shown in FIG.

FIG. 5 is a cross-sectional view taken along line C-C 'of the apparatus shown in FIG.

6A to 9B are cross-sectional views for explaining the manufacturing method of the apparatus shown in FIGS. 4 and 5.

* Explanation of symbols for main parts of the drawings

100: active matrix 105: first metal layer

110: first protective layer 115: second metal layer

120: second protective layer 125: etch stop layer

130: sacrificial layer 135: support layer

140: lower electrode 145: insulated line

150 strain layer 155 upper electrode

In order to achieve the above object, the present invention provides an active matrix including a drain pad formed on one side of the M x N (M, N is an integer) is built-in, the actuator is formed on top of the active matrix It provides a method of manufacturing a thin film type optical path control device comprising the step of forming a mirror on top of the actuator. The forming of the actuator may include (i) forming a first layer on top of the active matrix, ii) forming a bottom electrode layer on top of the first layer, and then patterning the bottom electrode to form a bottom electrode; Forming an insulating line by implanting oxygen (O ₂ ) ions along the boundary line of the IsoCut portion and the lower electrode of the middle portion, i) forming a second layer on the lower electrode and the insulating line, and then patterning the strained layer. Forming the upper electrode layer by laminating and patterning the upper electrode layer on top of the strained layer, and iii) forming the support layer by patterning the first layer.

According to the manufacturing method of the thin film type optical path control apparatus which concerns on this invention, after forming a lower electrode, oxygen ion implantation is performed along the boundary line of an Iso # Cut part and a lower electrode. The portion implanted with oxygen ions becomes an insulator, for example, an insulator of platinum-oxygen (Pt-O) to form an insulation line along the boundary line between the Iso ICut portion and the lower electrode, so that the lower electrode is shorted for each pixel. Subsequently, the strained layer is formed on the lower electrode, and then patterned to expose a portion of the insulating line. After depositing the upper electrode on top of the strained layer, the upper electrode is patterned to expose a portion of the insulating line while having a structure that completely caps the strained layer. The upper electrodes are connected to each other without being separated for each pixel as one side contacts the insulating line. Therefore, since the upper electrode is formed to completely cap the strained layer, it is possible to prevent damage of the strained layer by hydrogen fluoride vapor during the subsequent etching process.

In addition, since the Iso­Cut portion of the lower electrode is not formed before depositing the strained layer composed of the piezoelectric material such as PZT, the strained layer is deposited on the lower electrode so that no step occurs in the strained layer. Therefore, the strained layer may be deposited without voids therein to minimize the occurrence of cracks in the piezoelectric material constituting the strained layer in a heat treatment process for subsequent phase transition.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of a thin film type optical path adjusting device according to the present invention, and FIGS. 4 and 5 are cross-sectional views taken along line B′B ′ and C′C ′ of the apparatus shown in FIG. 3.

3 to 5, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 200, and a mirror 175.

The active matrix 100 having M × N (M and N are integers) MOS transistors (not shown) includes a first metal layer 105 and a first metal layer 105 extending from a source and a drain of the MOS transistor. The first protective layer 110 formed on the upper portion of the first protective layer 110, the second metal layer 115 formed on the upper portion of the second protective layer 120 formed on the second metal layer 115, and 2 includes an etch stop layer 125 formed on the protective layer 120. The first metal layer 105 includes a drain pad extending from the drain of the MOS transistor, and the second metal layer 115 is formed of a titanium (Ti) layer and a titanium nitride (TiN) layer.

The actuator 200 is in contact with a portion of the etch stop layer 125 in which the drain pad of the first metal layer 105 is formed, and the other side is horizontal with the lower portion of the active matrix 100 via the air gap 170. The support layer 135, the lower electrode 140 formed on the support layer, the deformation layer 150 formed on the lower electrode, the upper electrode 155 formed on the deformation layer 150, and one side of the deformation layer 150. The drain pad of the first metal layer 105 through the strained layer 150, the lower electrode 140, the support layer 135, the etch stop layer 125, the second passivation layer 120, and the first passivation layer 110. The via contact 160 includes a via contact 165 formed to connect the lower electrode 140 and the drain pad to the inside of the via hole 160 formed vertically.

The support layer 135 has a shape in which a rectangular flat plate is integrally formed with the arms on the same plane between two rectangular arms formed in parallel from both support portions. A mirror 175 is formed on the rectangular flat plate of the support layer 135. Thus, the mirror 175 has the shape of a rectangular flat plate.

4 and 5, an insulation line 145 is formed on the surface of the lower electrode 140 along the shape of the IsoCut portion separating the lower electrode 140 for each pixel and the lower electrode 140 having a predetermined pixel shape. ) Is formed. The strained layer 150 has a smaller area than the lower electrode 140, and is patterned to partially overlap both sides of the insulating line 145. The upper electrode 155 is formed to completely surround the strained layer 150, and is patterned to expose a portion of the insulating line 145.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

6A to 9B illustrate cross-sectional views for explaining a method of manufacturing the apparatus shown in FIGS. 4 and 5. In Figs. 6A to 9B, the same reference numerals are used for the same members as Figs. 4 and 5.

6A, 7A, 8A, and 9A are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 4, and FIGS. 6B, 7B, 8B, and 9B illustrate a method of manufacturing the device shown in FIG. It is sectional drawing for description.

6A and 6B, after preparing an active matrix 100, which is an n-type doped silicon (Si) wafer, the active matrix using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer for forming an active region and a field region is formed at 100. Subsequently, after forming a gate made of a conductive material such as polysilicon doped with impurities on top of the active region, p ⁺ sources and drains are formed by an ion implantation process, thereby forming M x N (M and N are integers) MOS. Form a transistor.

After forming an insulating film made of an oxide on the resultant formed MOS transistor, the openings for exposing the top of one side of the source and the drain are formed by a photolithography process. Subsequently, a first metal layer 105 made of a metal such as titanium, titanium nitride, or tungsten (W) is deposited on the resultant, on which the openings are formed, and then the first metal layer 105 is patterned by a photolithography process. The patterned first metal layer 105 includes a drain pad extending from the drain of the MOS transistor to one side of the support of the actuator 200.

The first passivation layer 110 is formed on the first metal layer 105. The first passivation layer 110 is formed to have a thickness of about 8000 GPa by using the silicate glass (PSG) chemical vapor deposition (CVD) method. The first protective layer 110 prevents damage to the active matrix 100 in which the MOS transistor is embedded during the subsequent process.

The second metal layer 115 is formed on the first protective layer 110. In order to form the second metal layer 115, first, a titanium layer is formed by sputtering titanium (Ti) to a thickness of about 300 μm. Subsequently, titanium nitride is deposited on top of the titanium layer using a physical vapor deposition (PVD) method to form a titanium nitride layer. The second metal layer 115 prevents light leakage current from flowing into the active matrix 100 because light incident from the light source is incident not only on the mirror 175 but also on a portion other than the portion where the mirror 175 is formed. . Subsequently, a portion of the second metal layer 115 in which the via contact 165 is to be formed in a subsequent process is etched through a photolithography process to form an opening in the second metal layer 115.

The second passivation layer 120 is formed on the second metal layer 115. The second protective layer 120 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 120 also prevents damage to the active matrix 100 in which the MOS transistor is embedded and the results formed on the active matrix 100 during the subsequent process.

An etch stop layer 125 is formed on the second passivation layer 120. The etch stop layer 125 prevents the active matrix 100 and the second passivation layer 120 from being etched due to the subsequent etching process. The etch stop layer 125 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

The sacrificial layer 130 is formed on the etch stop layer 125. The sacrificial layer 130 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to about 3.0 μm using an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 130 covers the upper portion and the etch protection layer 130 of the active matrix 100 in which the MOS transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 130 is planarized by polishing the surface of the sacrificial layer 130 using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method so that the sacrificial layer 130 has a thickness of about 1 .mu.m. .

Subsequently, the portion of the sacrificial layer 130 having the opening of the second metal layer 115 formed thereon and an adjacent portion thereof are etched to expose a portion of the etch stop layer 125, thereby anchoring an anchor that is a support of the actuator 200. Make a position to form.

The first layer 134 is formed on the exposed etch stop layer 125 and on the sacrificial layer 130. The first layer 134 is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD). The first layer 134 is later patterned into the support layer 135.

The lower electrode layer 139 is formed on the first layer 134 using a metal such as platinum, tantalum, or platinum-tantalum (Pt-Ta), which is a metal having excellent electrical conductivity. The lower electrode layer 139 is formed to have a thickness of about 0.01 to 1.0 µm using a sputtering method. After applying the first photoresist (not shown) to the upper portion of the lower electrode layer 139 by spin coating, the lower electrode layer 139 has a mirror-shaped 'c' shape as shown in FIG. 3. After patterning to form the lower electrode 140, the first photoresist is removed. The first signal transmitted from the transistor embedded in the active matrix 100 is applied to the lower electrode 140.

Subsequently, after applying a second photoresist (not shown) to the upper portion of the lower electrode 140 by spin coating, IsoCut in the lower electrode 140 using the second photoresist as an ion implantation mask. Oxygen (O ₂ ) ion implantation is performed on the surface of the portion, followed by heat treatment. At the same time, oxygen ion implantation is performed along the boundary line of the lower electrode 140 and then heat treated to form an ion implantation line, and then the second photoresist is removed. As a result, the IsoCut portion into which the oxygen ions are implanted in the lower electrode 140 becomes the insulating line 145 of Pt-O, so that the lower electrode 140 is shorted for each pixel without performing a separate IsoCut etching process. . In addition, an insulating line 145 of Pt-O is formed along the boundary line of the lower electrode 140.

7A and 7B, a second layer is stacked on the lower electrode 140 and the insulating line 145. The second layer is formed using a piezoelectric material such as PZT or PLZT so as to have a thickness of 0.1 to 1.0 mu m, preferably about 0.4 mu m. The second layer is formed using a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method. After applying a third photoresist (not shown) on top of the second layer by spin coating, the second layer is patterned to have a mirror-shaped 'c' shape slightly narrower than the lower electrode 140 to form a strained layer ( 150) and remove the third photoresist (see FIG. 3). As shown in FIG. 7B, the strained layer 150 is patterned to overlap one side of the insulation line 145 so that a portion of the insulation line 145 under the strained layer 150 is exposed. Subsequently, the piezoelectric material constituting the strained layer 150 is subjected to heat treatment by a rapid heat treatment (RTA) method to cause phase shift. The strained layer 150 is applied to an electric field generated by a second signal applied to the upper electrode 155 and a first signal applied to the lower electrode 140 according to a potential difference between the upper electrode 155 and the lower electrode 140. Cause deformation. As shown in FIG. 7A, before forming the strained layer 150 made of a piezoelectric material such as PZT, the IsoCut is formed on the lower electrode 140 for independent signal application to the lower electrode 140. Instead, an oxygen ion implantation process is performed. Therefore, no step occurs in the Iso­Cut portion of the lower electrode 140. Since the strained layer 150 is deposited on the lower electrode 140 formed flat without a step, the strained layer 150 is deposited evenly without voids, thereby deforming during the heat treatment process of the strained layer 150 for subsequent phase change. Cracking does not occur inside the layer 150.

8A and 8B, an upper electrode layer is stacked on the strained layer 150. The upper electrode layer is formed to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). Subsequently, after applying a fourth photoresist (not shown) on top of the upper electrode layer by a spin coating method, the upper electrode layer has a mirror image having an area about halfway between the lower electrode 140 and the strained layer 150. The upper electrode 155 is formed by patterning to have the shape of 'C' and the fourth photoresist is removed (see FIG. 3). As shown in FIG. 8B, the upper electrode 155 is formed to completely surround the lower deformation layer 150 and is partially patterned to contact the insulating line 145. Therefore, since the upper electrode 155 and the lower electrode 140 are not in contact with each other by the insulating line 145, the occurrence rate of the short is reduced. In addition, the upper electrode 155 in this portion also functions as a protective layer that blocks the strained layer 150 from being etched by the hydrogen fluoride vapor during the subsequent etching process. The second signal is applied to the upper electrode 155 through a common electrode line (not shown).

Subsequently, the strained layer 150, the lower electrode 140, the first layer 134, the etch stop layer 125, the second protective layer 120, and the first protective layer 110 are formed from one side of the strained layer 150. After etching to form the via hole 160, a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) in the via hole 160 using a sputtering method Deposition to form via contact 165. The via contact 165 connects the drain pad of the first metal layer 105 and the lower electrode 140 to each other. Therefore, the first signal applied from the outside is applied to the lower electrode 140 through the transistor, the drain pad, and the via contact 165 embedded in the active matrix 100.

9A and 9B, after a fifth photoresist (not shown) is coated on the upper electrode 155 and the via hole 160 by spin coating, both sides of the first layer 134 are supported. A portion extending from the lower electrode 140 has a slightly wider rectangular shape, and the central portion of the first layer 134 formed integrally therewith is patterned to have a rectangular flat plate shape to form the support layer 135. The fifth photoresist is removed. That is, as shown in FIG. 3, the support layer 135 has a shape in which rectangular arms extend from both support portions, and a rectangular flat plate having a larger area between these arms is formed integrally with the arms on the same plane. Have As a result of the patterning of the support layer 135 as described above, a portion of the sacrificial layer 130 is exposed.

Subsequently, after applying a sixth photoresist (not shown) to the upper part of the exposed sacrificial layer 130 and the upper support layer 135 by spin coating, a rectangular flat plate, which is the center of the support layer 135, is exposed. Pattern as much as possible. In addition, a sputtering method or a chemical vapor deposition method is used to form a metal having reflective properties such as silver, platinum, or aluminum on the upper portion of the center portion of the rectangular exposed support layer 135 to a thickness of about 0.3 to 2.0 µm. By deposition. Subsequently, the deposited metal is patterned so that the deposited metal has the same shape as the center portion of the rectangular exposed support layer 135 to form the mirror 175, and then the sixth photoresist is removed.

Subsequently, the sacrificial layer 130 is etched using hydrogen fluoride vapor to form an air gap 170 at the position of the sacrificial layer 130, followed by rinse and dry to thin-film optical path control apparatus. To complete.

In the above-described thin film type optical path control device according to the present invention, a second signal is applied to the upper electrode 155 through a common electrode line from the outside. At the same time, a first signal is applied to the lower electrode 140 from the outside through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 105, and the via contact 165. An electric field is generated between the electrodes 140 according to the potential difference. Due to this electric field, the deformation layer 150 formed between the upper electrode 155 and the lower electrode 140 causes deformation. The strained layer 150 contracts in a direction perpendicular to the generated electric field, and thus the actuator 200 including the strained layer 150 and the support layer 135 is bent upward at a predetermined angle. Since the mirror 175 reflecting the light incident from the light source is formed above the central portion of the support layer 135, the mirror 175 is bent at the same angle as the actuator 200. Accordingly, the mirror 175 reflects the incident light at a predetermined angle, and the reflected light passes through the slit to be projected onto the screen to form an image.

As described above, according to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after the lower electrode is deposited, oxygen ion implantation is performed on the portion of the lower electrode to be etched without isocutting to form an insulation line. The lower electrode may be shorted for each pixel. Since the step is not generated by the IsoutCut of the lower electrode, the strained layer deposited on the lower electrode is also formed without the step. Therefore, the strained layer is deposited without voids therein to significantly reduce the occurrence of cracks in the piezoelectric material constituting the strained layer during the heat treatment process for subsequent phase transition, resulting in short circuit between the upper electrode and the lower electrode. Can be reduced.

In addition, the upper electrode and the lower electrode are not shorted by the insulating line formed along the periphery of the lower electrode having a predetermined pixel shape, and the upper electrode is formed to have a structure that completely caps the strained layer. The strained layer is surrounded by the upper electrode so that damage by hydrogen fluoride vapor in the subsequent etching process can be minimized.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (3)

Providing an active matrix including M × N (M, N is an integer) transistors and including a drain pad formed on one side; Iii) forming a first layer on top of the active matrix, ii) forming a bottom electrode layer on top of the first layer, and then patterning to form a bottom electrode, iii) Iso-Cut of the bottom electrodes Forming an insulating line by performing oxygen (O ₂ ) ion implantation along the boundary lines of the partial and lower electrodes, i) forming a strained layer by forming a second layer on top of the lower electrode and the insulating line and then patterning (Iii) forming an upper electrode by stacking and patterning an upper electrode layer on top of the strained layer, and iii) patterning the first layer to form a support layer; And Method of manufacturing a thin film type optical path control device comprising the step of forming a mirror on top of the support layer. The method of claim 1, wherein in the step iii), after forming a second layer on the lower electrode and the insulating line, the second layer overlaps the insulating line and is patterned to expose a portion of the insulating line. Method of manufacturing a thin film optical path control device, characterized in that performed. The method of claim 1, wherein the step (iii) is performed by forming an upper electrode layer on the strained layer, and then patterning the upper electrode layer to expose a portion of the insulating line while completely capping the strained layer. The manufacturing method of the thin film type optical path control apparatus.

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