KR19990035317A - Manufacturing method of thin film type optical path control device - Google Patents

Abstract

Disclosed is a method of manufacturing a thin film type optical path control apparatus capable of improving the piezoelectric properties of a strained layer by performing a cleaning process. An active matrix is provided that includes a first metal layer having a transistor embedded therein and having a drain pad. After forming a support layer on the active matrix, a cleaning process is performed. After forming a lower electrode on the support layer, a strained layer is formed on the lower electrode. An upper electrode is formed on the strained layer. After the support layer is formed, a cleaning process is performed to remove contaminants generated during the formation of the support layer, thereby improving piezoelectric properties of the strained layer formed in a subsequent process.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control device using AMA (Actuated Mirror Array), and more particularly, to a thin film type optical path control device that can improve the piezoelectric properties of the strained layer by performing a cleaning process after forming a support layer. It relates to a method for producing.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 96-42197 (name of the invention: a method of manufacturing a thin film type optical path control device that can control the stress of the membrane) filed by the applicant of the Korean Patent Office on September 24, 1996. It is.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the preceding application.

First, the structure of the thin film type optical path control device is as follows.

The thin film type optical path control device includes an active matrix 1 and an actuator 60. An active matrix 1 having an M × N (M, N is an integer) MOS transistor embedded therein and having a drain pad 5 extending from a drain region of the transistor includes the active matrix 1 and a drain pad. The protective layer 10 stacked on the upper portion of the (5) and the etch stop layer 15 stacked on the protective layer 10 is included.

The actuator 60 has a membrane 30 and a membrane in which one side is in contact with a portion of the etch stop layer 15 in which the drain pad 5 is formed, and the other side is horizontally stacked through the air gap 25. A lower electrode 35 stacked on the top of the 30, a strained layer 40 stacked on the lower electrode 35, an upper electrode 45 stacked on the strained layer 40, and the strained layer. The lower electrode 35 in the via hole 50 vertically formed from one side of the 40 to the drain pad 5 through the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. ) And the drain pad 5 include a via contact 55 formed to be electrically connected to each other.

A stripe 46 is formed on a portion of the upper electrode 45. The stripe 46 uniformly operates the upper electrode 45 at the boundary between the portion of the upper electrode 45 that is deformed and the portion that is not deformed according to the deformation of the strained layer 40, so that light incident from the light source is diffusely reflected. To prevent them.

Hereinafter, the manufacturing method of the said thin film type optical path control apparatus is demonstrated.

Referring to FIG. 1A, an active wafer is formed of an n-type doped silicon wafer, in which M × N (M, N is an integer) P-MOS transistors are formed and a drain pad 5 extending from the drain region of the transistor is formed. A protective layer 10 made of phosphorus silicate glass PSG is formed on the matrix 1. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the MOS transistor is embedded during a subsequent process.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 µm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the MOS transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby forming a support of the actuator 60.

The membrane 30 is formed on the exposed etch stop layer 15 and on the sacrificial layer 20. The membrane 30 is formed by depositing nitride to a thickness of about 0.01 to 1.0 mu m using a low pressure chemical vapor deposition (LPCVD) method.

The lower electrode 35 is formed on the membrane 30. The lower electrode 35 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). Subsequently, the lower electrode 35 is separated for each pixel through a photolithography process so that an independent first signal (image signal) is applied to each pixel (Iso-cutting process). A first signal (image signal) is applied to the lower electrode 35 from the outside through the transistor built in the active matrix 1, the drain pad 5, and the via contact 55.

A deformation layer 40 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode 35. The strained layer 40 is formed to have a thickness of about 0.1-1 .0 μm, preferably about 0.4 μm using a sol-gel method, a sputtering method, or a chemical vapor deposition method. do. In addition, the strained layer 40 is subjected to heat treatment by a rapid heat treatment (RTA) method to perform phase shift. The strained layer 40 is applied with a second signal (bias signal) to the upper electrode 45 and a first signal is applied to the lower electrode 35 so that the potential difference between the upper electrode 45 and the lower electrode 35 is reduced. Deformation is caused by the electric field generated.

The upper electrode 45 is stacked on the deformation layer 40. The upper electrode 45 is formed to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. Since the upper electrode 45 has excellent electrical conductivity and reflectivity, the upper electrode 45 performs not only a function of a bias electrode generating an electric field, but also a mirror reflecting light incident from a light source.

Referring to FIG. 1B, the upper electrode 45, the deformation layer 40, and the lower electrode 35 are sequentially patterned from a top of the upper electrode 45 into a predetermined pixel shape. At this time, a portion of the upper electrode 45 is formed with a stripe 46 to uniformly operate the upper electrode 45 to prevent diffuse reflection of light incident from the light source.

Subsequently, the via hole 50 is etched by sequentially etching the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 from one side of the strained layer 40. Form. Therefore, the via hole 50 is formed from one side of the strained layer 40 to the drain pad 5. Subsequently, a via contact 55 is formed in the via hole 50 by depositing a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) using a sputtering method. The via contact 55 electrically connects the drain pad 5 and the lower electrode 35. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. Subsequently, the membrane 30 is patterned to have a predetermined pixel shape.

Then, the sacrificial layer 20 is removed using hydrogen fluoride (HF) vapor to form an air gap 25 at the position of the sacrificial layer 20, and then a rinse and dry treatment is performed. To complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. At the same time, a second signal is applied to the upper electrode 45 to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the electric field, and the actuator 60 including the strained layer 40 is bent upward at a predetermined angle. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described manufacturing method of the thin film type optical path control apparatus, immediately after forming the membrane made of nitride, the lower electrode and the strained layer are sequentially formed. Typically, depositing nitride causes a native oxide to grow on top of the nitride layer. In addition, contaminants such as particles, organic matter, and inorganic matter may occur in the process of depositing nitride. If the process proceeds as it is without removing such contaminants or natural oxide film, the deformation layer formed in the subsequent process is not normally deformed, there is a problem that the displacement of the actuator is reduced.

Accordingly, an object of the present invention is to provide a method for manufacturing a thin film type optical path control apparatus capable of improving the piezoelectric properties of a strained layer by performing a cleaning step after forming a support layer.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

2 is a plan view of a thin film type optical path control apparatus according to the present invention.

FIG. 3 is a cross-sectional view of the apparatus shown in FIG. 2 taken along line A′A ′.

4A to 4D are cross-sectional views illustrating a method of manufacturing the apparatus shown in FIG. 3.

<Explanation of symbols for main parts of the drawings>

100: active matrix 155: first metal layer

160: first protective layer 165: second metal layer

170: second protective layer 175: etch stop layer

185: support layer 190: lower electrode

195 strain layer 200 upper electrode

205 Actuator 210 Beer Hole

215: Beer contact 220: Stripe

225: air gap

In order to achieve the above object, the present invention provides an active matrix comprising a first metal layer having M x N (M, N is an integer) MOS transistor embedded therein and having a drain pad extending from the drain of the transistor. ; And a) forming a support layer on top of the active matrix and then precipitating the active matrix in a hydrogen fluoride (HF) solution iii) washing with a solution of H ₂ O ₂ + H ₂ O, ii) 50: 1 Performing a cleaning process comprising precipitation in a hydrogen fluoride (HF) solution, and iii) performing hot distilled water wash and rinse; b) forming a lower electrode on the support layer; c) forming a strained layer on the lower electrode; And d) forming an actuator comprising the step of forming an upper electrode on the deformation layer.

According to the manufacturing method of the thin film type optical path control apparatus which concerns on this invention, after forming the support layer which consists of nitrides, it performs a washing process. Preferably, the cleaning process is carried out by dipping the wafer into a 50: 1 hydrogen fluoride (HF) solution. Therefore, the particles, natural oxide film, organic material or inorganic material generated in the process of forming the support layer can be removed, so that the piezoelectric properties of the strained layer formed in the subsequent process can be improved.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

FIG. 2 is a plan view of a thin film type optical path adjusting device according to the present invention, and FIG. 3 is a sectional view taken along line AA ′ of the device shown in FIG. 2.

2 and 3, the thin film type optical path control apparatus includes an active matrix 100 and an actuator 205 formed on the active matrix 100.

The active matrix 100 includes an isolation layer 120 for dividing the active matrix 100 into an active region and a field region, and a gate 115, a source 110, and a drain 105 in the active region. The formed MxN (M, N is an integer) P-MOS transistors are included. In addition, the active matrix 100 is stacked on top of the first metal layer 155 and the first metal layer 155 that are stacked on top of the MOS transistor and patterned to be connected to the source 110 and the drain 105, respectively. First protective layer 160, second metal layer 165 stacked on top of first protective layer 160, second protective layer 170 stacked on top of second metal layer 165, and second The anti-etching layer 175 stacked on the protective layer 170 is included. The first metal layer 155 includes a drain pad extending from the drain 105 of the P-MOS transistor, and the second metal layer 165 includes a titanium (Ti) layer and a titanium nitride (TiN) layer. .

The actuator 205 may have one side contacting a portion of the etch stop layer 175 having a drain pad formed thereon, and the other side of the actuator 205 horizontally formed through the air gap 225, and an upper portion of the support layer 185. A lower electrode 190 stacked on the lower electrode 190, a strained layer 195 stacked on top of the lower electrode 190, an upper electrode 200 stacked on top of the strained layer 195, and one side of the strained layer 195. Drain of the first metal layer 155 through the strain layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first passivation layer 160. The via contact 215 may be formed to connect the drain pad and the lower electrode 190 to each other in the via hole 210 perpendicular to the pad.

The support layer 185 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application. Light incident on the part of the upper electrode 200 is uniformly operated by the upper electrode 200 and is incident from the light source at the boundary between the portion of the upper electrode 200 which is deformed according to the deformation of the deformation layer 195 and the portion which is not deformed. Stripes 220 are formed to prevent these diffuse reflections.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

4A to 4D are cross-sectional views for explaining the method for manufacturing the device shown in FIG. 3. 4A to 4D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 4A, after preparing an active matrix 100 formed of an n-type doped silicon (Si) wafer, the active matrix (LOCOS) may be manufactured using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer 120 is formed in 100 to separate the active region and the field region. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source 110 and drain 105 are formed by an ion implantation process. N (M, N is an integer) P-MOS transistors are formed.

After the insulating film 125 made of oxide is formed on the upper part of the resultant transistor, the openings exposing the upper portions of the one side of the source 110 and the drain 105 are formed by a photolithography process. Subsequently, a first metal layer 155 made of a metal such as titanium, titanium nitride, tungsten, or the like is deposited on the resultant on which the openings are formed, and then the first metal layer 155 is patterned by a photolithography process. The patterned first metal layer 155 includes a drain pad extending from the drain 105 of the P-MOS transistor to the support of the actuator 205.

The first passivation layer 160 is formed on the active matrix 100 and the first metal layer 155. The first passivation layer 160 is formed to have a thickness of about 8000 kPa using the silicate glass (PSG) method using a chemical vapor deposition (CVD) method. The first protective layer 160 prevents damage to the active matrix 100 in which the MOS transistor is embedded during a subsequent process.

The second metal layer 165 is formed on the first passivation layer 160. In order to form the second metal layer 165, first, a titanium layer is formed by sputtering titanium to a thickness of about 300 kV, and then titanium nitride is deposited on the titanium layer by using a physical vapor deposition (PVD) method. Form a layer. Since the light incident from the light source is incident not only to the upper electrode 200, which is a reflective layer, but also to a portion other than the portion where the upper electrode 200 is formed, the second metal layer 165 may have a light leakage current in the active matrix 100. To prevent it from flowing. Subsequently, a portion 166 of the second metal layer 165 in which the via contact 215 is to be formed in a subsequent process is etched through a photolithography process to expose a portion of the first passivation layer 160.

The second passivation layer 170 is formed on the exposed first passivation layer 160 and the second metal layer 165. The second protective layer 170 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 170 also prevents damage to the active matrix 100 in which the transistor is embedded and the results formed on the active matrix 100 during the subsequent process.

An etch stop layer 175 is formed on the second passivation layer 170. The etch stop layer 175 prevents the active matrix 100 and the second passivation layer 170 from being etched due to the subsequent etching process. The etch stop layer 175 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

The sacrificial layer 180 is formed on the etch stop layer 175. The sacrificial layer 180 is formed by depositing phosphorus silicate (PSG) to a thickness of about 2.0 to about 3.0 μm by an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 180 covers the top of the active matrix 100 in which the MOS transistor is embedded, the surface flatness is very poor. Therefore, by using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method by polishing the surface of the sacrificial layer 180 so that the sacrificial layer 180 to a thickness of about 1.1㎛ Planarize. Subsequently, a portion of the sacrificial layer 180 where the drain pad 145 is formed is etched to expose a portion of the etch stop layer 175, thereby forming a support of the actuator 205.

Referring to FIG. 4B, a support layer 185 is formed on the exposed etch stop layer 175 and on the sacrificial layer 180. The support layer 185 is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD).

Subsequently, the active matrix 100 was first washed using a standard cleaning solution (SC-1) in which NH ₄ OH: H ₂ O ₂ : H ₂ O was mixed at a ratio of 1: 1: 5 to form an organic material and an inorganic material. After the removal, the active matrix 100 was precipitated in a 50: 1 hydrogen fluoride (HF) solution and removed by the native oxide film formed on the support layer 185 made of nitride and the standard cleaning solution (SC-1) solution. Remove any remaining organic matter. Subsequently, after washing in hot D-I Water, a rinse and dry process is performed. When the cleaning process described above is performed, the thickness of the support layer 185 may be lost to some extent. Therefore, it is preferable to form the support layer 185 thicker than the desired thickness by calculating the thickness loss according to the cleaning process.

The lower electrode 190 is formed on the support layer 185. The lower electrode 190 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). do. At the same time, the lower electrode 190 is separated for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso-cutting process). A first signal is applied to the lower electrode 190 through a transistor embedded in the active matrix 100, a drain pad of the first metal layer 155, and a via contact 215 from the outside.

A strained layer 195 formed of a piezoelectric material such as PZT or PLZT is formed on the lower electrode 190. The strained layer 195 is formed to have a thickness of about 0.1 to 1.0 µm, preferably about 0.4 µm using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the piezoelectric material constituting the strained layer 195 is subjected to heat treatment by a rapid heat treatment (RTA) method to perform phase shift. The strained layer 195 is applied with a second signal (bias signal) to the upper electrode 200 and a first signal is applied to the lower electrode 190 so that the potential difference between the upper electrode 200 and the lower electrode 190 is reduced. Deformation is caused by the electric field generated.

The upper electrode 200 is formed on the strained layer 195. The upper electrode 200 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 200 through a common electrode line (not shown) from the outside. Since the upper electrode 200 has excellent electrical conductivity and reflectivity, the upper electrode 200 performs not only a function of a bias electrode generating an electric field but also a function of a mirror reflecting light incident from a light source.

Referring to FIG. 4C, the upper electrode 200, the strain layer 195, and the lower electrode 190 are sequentially patterned to have a predetermined pixel shape. At this time, a part of the upper electrode 200 is formed with a stripe 220 to uniformly operate the upper electrode 200 to prevent diffuse reflection of light incident from the light source.

Subsequently, the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second protective layer 170, and the first protective layer 160 are formed from one side of the strained layer 195. The via holes are sequentially etched to form via holes 210. Therefore, the via hole 210 is formed from one side of the strained layer 195 to the drain pad of the first metal layer 155. Subsequently, a via contact 215 is formed in the via hole 210 by depositing a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) using a sputtering method. The via contact 215 electrically connects the drain pad of the first metal layer 155 and the lower electrode 190. Therefore, the first signal applied from the outside is applied to the lower electrode 190 through the transistor, the drain pad, and the via contact 215 embedded in the active matrix 100. Subsequently, the support layer 185 is patterned to have a predetermined pixel shape.

Referring to FIG. 4D, the sacrificial layer 180 is etched using hydrogen fluoride (HF) vapor to form an air gap 225 at the position of the sacrificial layer 180, followed by rinse and dry. ) To complete the AMA device.

In the above-described thin film type optical path control device according to the present invention, the first signal transmitted from the outside is the lower electrode through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 155 and the via contact 215. Is applied to 190. At the same time, a second signal is applied to the upper electrode 200 to generate an electric field according to the potential difference between the upper electrode 200 and the lower electrode 190. Due to this electric field, the deformation layer 195 formed between the upper electrode 200 and the lower electrode 190 causes deformation. The strained layer 195 contracts in a direction orthogonal to the electric field, and thus the actuator 205 is bent at a predetermined angle. The upper electrode 200, which also functions as a mirror that reflects light, is formed on the actuator 205 and is inclined together with the actuator 205. Accordingly, the upper electrode 200 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

As described above, according to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming a support layer made of nitride, a cleaning process is performed. Preferably, the cleaning process is carried out by precipitating the active matrix in a 50: 1 hydrogen fluoride (HF) solution. Therefore, since particles, natural oxide films, or other contaminants generated during the formation of the support layer can be removed, the piezoelectric properties of the strained layer formed in a subsequent process can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (1)

Providing an active matrix comprising a first metal layer with M × N (M, N is an integer) embedded therein and having a drain pad extending from the drain of the transistor; And a) forming a support layer on top of the active matrix and then precipitating the active matrix in a hydrogen fluoride (HF) solution iii) washing with a solution of H ₂ O ₂ + H ₂ O, ii) 50: 1 fluorine Performing a cleaning process comprising the step of precipitating in hydrogen hydrogen (HF) solution, and iii) performing hot distilled water washing and rinsing; b) forming a lower electrode on the support layer; c) forming a strained layer on the lower electrode; d) forming an actuator comprising the step of forming an upper electrode on the strained layer.