KR19990019076A - Manufacturing method of thin film type optical path control device - Google Patents

Abstract

Disclosed is a method of manufacturing a thin film type optical path control device. Provided is an active matrix having an M × N MOS transistor embedded therein and having a first metal layer including a drain pad extending from the drain of the transistor. After forming a first sacrificial layer on the active matrix, an actuator including a support layer, a lower electrode, a strained layer, and an upper electrode is formed thereon. After forming an etch protective layer on the stepped surface of the strained layer, a second sacrificial layer is formed on the resultant. After forming a mirror that reflects light on the second sacrificial layer, the first and second sacrificial layers are removed. The etching protection layer may prevent the hydrogen fluoride (HF) vapor from damaging the strained layer during the etching process of the first sacrificial layer and the second sacrificial layer using the subsequent hydrogen fluoride (HF) vapor.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using AMA (Actuated Mirror Array), and more particularly, a thin film type that can prevent the deformation layer from being damaged during an etching process by hydrogen fluoride (HF) vapor. A method for producing an optical path control device.

Spatial light modulators, which are devices for projecting optical energy onto a screen, can be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (10% or more) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect the incident light at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 96-42197 (name of the invention: a method of manufacturing a thin film type optical path control device that can control the stress of the membrane) filed by the applicant of the Korean Patent Office on September 24, 1996. It is.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the preceding application.

First, the structure of the thin film type optical path control device is as follows.

The thin film type optical path control device includes an active matrix 1 and an actuator 60. The active matrix 1 having an M × N (M, N is an integer) MOS transistor embedded therein and having a drain pad 5 extending from the drain region of the transistor includes an active matrix 1 and a drain pad. The protective layer 10 stacked on the upper portion of the (5) and the etch stop layer 15 stacked on the protective layer 10 is included.

The actuator 60 has a membrane 30 and a membrane in which one side is in contact with a portion of the etch stop layer 15 in which the drain pad 5 is formed, and the other side is horizontally stacked through the air gap 25. Lower electrode 35 stacked on top of 30, strained layer 40 stacked on top of lower electrode 35, upper electrode 45 stacked on top of strained layer 40, and strained layer ( The lower electrode 35 in the via hole 50 vertically formed from one side of the 40 to the drain pad 5 through the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. And the drain pad 5 include a via contact 55 formed to be electrically connected to each other.

A stripe 46 is formed on a portion of the upper electrode 45. The stripe 46 uniformly operates the upper electrode 45 so that light incident from the light source is diffusely reflected at the boundary between the portion of the upper electrode 45 that is deformed and the portion that is not deformed according to the deformation of the strained layer 40. To prevent them.

Hereinafter, the manufacturing method of the said thin film type optical path control apparatus is demonstrated.

Referring to FIG. 1A, an M × N (M, N is an integer) phosphorus is formed on an active matrix 1 in which a MOS transistor (not shown) is embedded and a drain pad 5 extending from the drain region of the transistor is formed. A protective layer 10 composed of silicate glass PSG is formed. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded during subsequent processing.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 μm by using an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby making a position where the support of the actuator 60 is to be formed.

Referring to FIG. 1B, the membrane 30 is formed on the exposed etch stop layer 15 and the sacrificial layer 20 with a thickness of about 0.1 μm to about 1.0 μm. Membrane 30 is formed using low pressure chemical vapor deposition (LPCVD). At this time, by forming the membrane 30 while changing the ratio of the reaction gas in the reaction vessel of low pressure, the stress in the membrane 30 is controlled.

The lower electrode 35 made of a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum is formed on the membrane 30. The lower electrode 35 is formed to have a thickness of about 0.1 μm to 1.0 μm using the sputtering method. The lower electrode 35 is patterned to separate the lower electrode 35 for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso­Cut etching process).

The deformation layer 40 made of a piezoelectric material such as PZT or PLZT is formed on the lower electrode 35. The strained layer 40 is formed to have a thickness of about 0.1 μm to about 1.0 μm, preferably about 0.4 μm using a sol-gel method, and then phase-shifted by a rapid heat treatment (RTA) method. The strained layer 40 is applied with a second signal (bias signal) to the upper electrode 45 and a first signal is applied to the lower electrode 35 so that the potential difference between the upper electrode 45 and the lower electrode 35 is reduced. Deformation is caused by the electric field generated.

The upper electrode 45 is formed on the strained layer 40. The upper electrode 45 is formed of a metal having electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 0.1 to 1.0 μm using a sputtering method. The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. In addition, the upper electrode 45 also functions as a mirror that reflects light incident from the light source.

Subsequently, the upper electrode 45 is patterned into a predetermined pixel shape. At this time, the stripe 46 is patterned to form one side of the upper electrode 45. Subsequently, the strained layer 40 and the lower electrode 35 are sequentially patterned into a predetermined pixel shape, and then, from one side of the strained layer 40 to the drain pad 5, the strained layer 40 and the lower electrode ( 35, the via hole 50 is formed by sequentially etching the membrane 30, the etch stop layer 15, and the protective layer 10. Subsequently, a metal such as tungsten, platinum or titanium is deposited in the via hole 50 by a sputtering method to form a via contact 55 that electrically connects the drain pad 5 and the lower electrode 35. . Therefore, the via contact 55 is formed vertically from the lower electrode 35 to the top of the drain pad 5 in the via hole 50. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1.

Subsequently, a photoresist (not shown) is applied to the entire surface of the resultant product in which the via contact 55 is formed and patterned to expose the membrane 30. The membrane 30 is patterned to have a predetermined pixel shape by using the photoresist as an etching mask. Subsequently, the air gap 25 is formed at the position of the sacrificial layer 20 by etching the sacrificial layer 20 by 49% hydrogen fluoride (HF) vapor, and then washed to remove the remaining etching solution. And the drying step to complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied from the outside to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. In addition, a second signal is applied to the upper electrode 45 from the outside to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the electric field, and the actuator 60 including the strained layer 40 is bent upward at a predetermined angle. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described method for manufacturing a thin film type optical path control device, when the sacrificial layer is removed by using hydrogen fluoride (HF) vapor, the signal is damaged due to the deformation layer being damaged by the hydrogen fluoride (HF) vapor. There is a problem that the actuator does not operate properly even if is applied.

Accordingly, it is an object of the present invention to provide a method of manufacturing a thin film type optical path control apparatus which can prevent the deformation layer from being damaged during the etching process of the sacrificial layer by hydrogen fluoride (HF) vapor.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

2 is a cross-sectional view of a thin film type optical path control apparatus according to the present invention.

3A to 3E are manufacturing process diagrams of the apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

100: active matrix 155: first metal layer

160: first protective layer 165: second metal layer

170: second protective layer 175: etch stop layer

185: support layer 190: lower electrode

195 strain layer 200 upper electrode

205 Actuator 210 Beer Hole

215: Beer Contact 225: Air Gap

230: separation layer 235: etching protective layer

240: second sacrificial layer 250: mirror

In order to achieve the above object, the present invention provides an active matrix comprising a M x N (M, N is an integer) transistor is formed and a first metal layer including a drain pad extending from the drain of the transistor, Forming an actuator on top of the active matrix, forming an actuator on top of the first sacrificial layer, forming a support layer, a lower electrode, a strain layer and an upper electrode, from the upper electrode Forming an etch protective layer on the stepped surface to the lower electrode, forming a second sacrificial layer on the actuator, forming a mirror reflecting light on the second sacrificial layer, and It provides a method of manufacturing a thin film type optical path control device comprising the step of removing the first sacrificial layer and the second sacrificial layer.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming the actuator, an etch protective layer made of a material such as amorphous silicon is formed on the stepped surface of the strained layer, and the second sacrificial layer and the mirror are sequentially formed. . The etch protective layer may be configured to infiltrate the strain layer by damaging the hydrogen fluoride (HF) vapor during the etching process of the first sacrificial layer and the second sacrificial layer using subsequent hydrogen fluoride (HF) vapor. You can prevent it. In addition, when the etching protective layer is formed of amorphous silicon, the stepped surface of the strained layer before forming the etching protective layer in order to prevent the electrical short between the upper electrode and the lower electrode caused by the etching protective layer. To form a separation layer of oxide.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

Figure 2 shows a cross-sectional view of the thin film type optical path control apparatus according to the present invention.

Referring to FIG. 2, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 205 formed on the active matrix 100, and a mirror 250 formed on the actuator 205. do.

The active matrix 100 includes an isolation layer 120 for dividing the active matrix 100 into an active region and a field region, and a gate 115, a source 110, and a drain 105 in the active region. The formed M × N (M, N is an integer) number of MOS transistors are included. In addition, the active matrix 100 is stacked on top of the first metal layer 155 and the first metal layer 155 that are stacked on top of the MOS transistor and patterned to be connected to the source 110 and the drain 105, respectively. First protective layer 160, second metal layer 165 stacked on top of first protective layer 160, second protective layer 170 stacked on top of second metal layer 165, and second The anti-etching layer 175 stacked on the protective layer 170 is included. The first metal layer 155 includes a drain pad extending from the drain 105 of the MOS transistor. The second metal layer 165 includes a first layer 165a made of titanium (Ti) and a second layer 165b made of titanium nitride (TiN).

The actuator 205 may have one side contacting a portion of the etch stop layer 175 in which the drain pad of the first metal layer 155 is formed and the other side thereof may be horizontally formed through the air gap 225. , A lower electrode 190 stacked on the support layer 185, a strain layer 195 stacked on the lower electrode 190, an upper electrode 200 stacked on the strain layer 195, and the The first through the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second protective layer 170, and the first protective layer 160 from one side of the strained layer 195. A via contact 215 is formed in the via hole 210 vertically up to the drain pad of the first metal layer 155 so that the lower electrode 190 and the drain pad are connected to each other. The support layer 185 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application.

A mirror 250 is formed on the upper electrode 200, and the center of the mirror 250 is supported by a post 245.

In addition, the separation layer 230 and the etching protection layer 235 are sequentially stacked on the outer surface of the actuator 205 and the stepped surface of the deformable layer 195 inside the via hole 210. The etch protection layer 235 serves to prevent damage to the strained layer 195, and the separation layer 230 is formed between the upper electrode 200 and the lower electrode 190 by the etch protection layer 235. Prevent electrical shorts from occurring.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

3A to 3E are cross-sectional views for explaining the method for manufacturing the device shown in FIG. 2. 3A to 3E, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 3A, after preparing an active matrix 100 formed of an n-type doped silicon (Si) wafer, the active matrix (LOCOS) may be manufactured using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer 120 is formed in 100 to separate the active region and the field region. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source 110 and drain 105 are formed by an ion implantation process. N (M, N is an integer) P-MOS transistors are formed.

After forming the insulating layer 125 made of oxide on the top of the resultant P-MOS transistor is formed, openings for exposing the top of one side of the source 110 and the drain 105, respectively by a photolithography process. Subsequently, after depositing a first metal layer 155 made of a metal such as titanium, titanium nitride, and tungsten (W) on the resultant, the first metal layer 155 is patterned by a photolithography process. The first metal layer 155 patterned as described above includes a drain pad extending from the drain 105 of the MOS transistor to one side of the support of the actuator 205. The first signal (image signal) applied from the outside is transferred to the lower electrode 190 through the MOS transistor embedded in the active matrix 100, the drain pad of the first metal layer 155, and the via contact 215.

The first passivation layer 160 is formed on the first metal layer 155. The first passivation layer 160 is formed to have a thickness of about 8000 kPa using the silicate glass (PSG) method using a chemical vapor deposition (CVD) method. The first protective layer 160 prevents damage to the active matrix 100 in which the MOS transistor is embedded during a subsequent process.

The second metal layer 165 is formed on the first passivation layer 160. In order to form the second metal layer 165, first, titanium (Ti) is sputtered to form the first layer 165a to a thickness of about 300 μm. Next, titanium nitride is deposited on the first layer 165a by using a physical vapor deposition (PVD) method to form a second layer 165b. Since the light incident from the light source is incident on the second metal layer 165 as well as the upper electrode 200, except for the portion where the upper electrode 200 is formed, a light leakage current flows in the active matrix 100. To prevent them. Subsequently, in the subsequent process of the second metal layer 165, the portion 166 on which the via contact 215 is to be formed is etched through a photolithography process.

The second passivation layer 170 is formed on the second metal layer 165. The second protective layer 170 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 170 also prevents damage to the active matrix 100 in which the MOS transistor is embedded and the results formed on the active matrix 100 during the subsequent process.

An etch stop layer 175 is formed on the second passivation layer 170. The etch stop layer 175 prevents the active matrix 100 and the second passivation layer 170 from being etched due to the subsequent etching process. The etch stop layer 175 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

The first sacrificial layer 180 is formed on the etch stop layer 175. The first sacrificial layer 180 is formed by depositing a silicate glass (PSG) to a thickness of about 2.0 to about 3.0 μm using an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the first sacrificial layer 180 covers the top of the active matrix 100 in which the MOS transistor is embedded, the surface flatness of the first sacrificial layer 180 is very poor. Accordingly, the surface of the sacrificial layer 180 is formed such that the first sacrificial layer 180 is about 1 μm thick by using spin on glass (SOG) or chemical mechanical polishing (CMP). Plane by polishing. Subsequently, a portion of the first sacrificial layer 180 where the drain pad 145 is formed is etched to expose a portion of the etch stop layer 175, thereby forming a position at which the supporting portion of the actuator 205 is formed.

Referring to FIG. 3B, a support layer 185 is formed on the exposed etch stop layer 175 and on the sacrificial layer 180. The support layer 185 is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD).

The lower electrode 190 is formed on the support layer 185. The lower electrode 190 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). do. At the same time, the lower electrode 190 is separated for each pixel so that an independent first signal is applied to each pixel (Iso-cut process). A first signal is applied to the lower electrode 190 through a transistor embedded in the active matrix 100 and a drain pad of the first metal layer 155 from the outside.

A strained layer 195 formed of a piezoelectric material such as PZT or PLZT is formed on the lower electrode 190. The strained layer 195 is formed to have a thickness of about 0.1 to 1.0 탆, preferably about 0.4 탆 using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the piezoelectric material constituting the strained layer 195 is subjected to heat treatment by a rapid heat treatment (RTA) method to perform phase shift. The strained layer 195 is applied with a second signal (bias signal) to the upper electrode 200 and a first signal is applied to the lower electrode 190 so that the potential difference between the upper electrode 200 and the lower electrode 190 is reduced. Deformation is caused by the electric field generated.

The upper electrode 200 is formed on the strained layer 195. The upper electrode 200 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 200 through a common electrode line (not shown) from the outside.

Subsequently, the upper electrode 200, the strain layer 195, and the lower electrode 190 are sequentially patterned into a predetermined pixel shape. The strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first passivation layer 160 are formed from one side of the strained layer 195. The via holes are sequentially etched to form via holes 210. Accordingly, the via hole 210 is formed from one side of the strained layer 195 to the drain pad of the first metal layer 155. Subsequently, a via contact 210 may be formed by depositing a metal having electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) in the via hole 210 using a sputtering method. The via contact 215 electrically connects the drain pad of the first metal layer 155 and the lower electrode 190. Therefore, the first signal applied from the outside is applied to the lower electrode 190 through the transistor, the drain pad, and the via contact 215 embedded in the active matrix 100. Subsequently, the support layer 185 is patterned into a predetermined pixel shape.

Referring to FIG. 3C, an oxide is deposited using the chemical vapor deposition (CVD) method as a separation layer 230 on top of the resultant, and the separation layer 230 is patterned by a photolithography process. The separation layer 230 is formed by the upper layer 200 and the lower electrode 190 by an amorphous silicon etch protective layer 235 formed to prevent the strained layer 195 from being damaged by hydrogen fluoride (HF) vapor. In order to prevent the electrical short between the ()) is formed on the stepped surface of the deformable layer 195 in the outer portion of the actuator 205 and the inside of the via hole 210.

Subsequently, an etch protection layer 235 is formed on the resultant. Etch protective layer 235 is preferably formed of a material that is not etched during the subsequent etching process using hydrogen fluoride (HF) vapor, more preferably, amorphous silicon is plasma-enhanced chemical vapor deposition (PECVD) method To form. Subsequently, the etch protection layer 235 is patterned through a photolithography process so that the etch protection layer 235 is formed on the stepped surface of the strained layer 195 on which the separation layer 230 is formed.

Referring to FIG. 3D, a second sacrificial layer 240 is formed on the resultant. The second sacrificial layer 240 is formed of an oxide or phosphorus silicate glass (PSG) using a chemical vapor deposition (CVD) method. Subsequently, a portion of the upper electrode 200 is exposed by patterning the second sacrificial layer 240 by a photolithography process. In this case, before performing the photolithography process to improve the flatness of the second sacrificial layer 240, the surface of the second sacrificial layer 240 is planarized using a chemical mechanical polishing (CMP) method. You can perform more steps.

Referring to FIG. 3E, the mirror 250 is formed by depositing aluminum, platinum, silver, or an aluminum alloy, which is a reflective metal, on the second sacrificial layer 240. Mirror 250 is formed using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method. The center of the mirror 250 is supported by the post 245.

Subsequently, after the mirror 250 is patterned into a predetermined shape, the first sacrificial layer 180 and the second sacrificial layer 230 are removed using hydrogen fluoride (HF) vapor to form an air gap 225. By forming the AMA device having a mirror 250 on top. Here, the strained layer 195 is coated with an etching protection layer 235 made of a material (PECVD-amorphous silicon) that is not etched in hydrogen fluoride (HF) vapor, so that the strained layer 195 is hydrogen fluoride. It is possible to prevent (HF) vapor from penetrating and damaging the strained layer 195.

In the above-described thin film type optical path control device according to the present invention, the first signal transmitted from the outside is the lower electrode through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 155 and the via contact 215. Is applied to 190. At the same time, a second signal is applied to the upper electrode 200 through the common electrode line from the outside to generate an electric field between the upper electrode 200 and the lower electrode 190. Due to this electric field, the strain layer 195 between the upper electrode 200 and the lower electrode 190 causes deformation. The strained layer 195 contracts in a direction orthogonal to the electric field, and thus the actuator 205 is bent at a predetermined angle. Since the mirror 250 is formed on the actuator 205, the mirror 250 is inclined together with the actuator 205. Accordingly, the mirror 250 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

As described above, according to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming the actuator, an etching protective layer made of a material such as amorphous silicon is formed on the step surface of the strained layer, and the second sacrificial layer and the mirror are formed. Form sequentially. Accordingly, the hydrogen fluoride (HF) vapor penetrates into the strained layer during the etching process of the first sacrificial layer and the second sacrificial layer using the hydrogen fluoride (HF) vapor followed by the etching protective layer to form the strained layer. It can prevent damage.

In addition, by forming a separation layer between the etching protection layer and the strained layer, it is possible to prevent the electrical short circuit between the upper electrode and the lower electrode caused by the etching protection layer.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

Providing an active matrix having M × N (M, N is an integer) formed therein and having a first metal layer including a drain pad extending from the drain of the transistor, Forming a first sacrificial layer on the active matrix; Forming an actuator including forming a support layer, a lower electrode, a strained layer, and an upper electrode on the first sacrificial layer; Forming an etch protective layer on a step surface from the upper electrode to the lower electrode through the strain layer; Forming a second sacrificial layer on top of the actuator, Forming a mirror reflecting light on the second sacrificial layer, and And removing the first sacrificial layer and the second sacrificial layer. The method of claim 1, wherein the forming of the etch protective layer is performed by using plasma-enhanced chemical vapor deposition (PECVD). The method of claim 1, wherein the forming of the etch protective layer is performed after forming a separation layer on a step surface from the upper electrode to the lower electrode. The method of claim 3, wherein the forming of the separation layer is performed by using a chemical vapor deposition (CVD) method.