KR100256874B1 - Manufacturing method for thin flim actuated mirror array - Google Patents

Abstract

PURPOSE: A thin-film micromirror array-actuated(TMA) manufacturing method planarizes the surface of a planarization layer to compensate the step caused by an active matrix, thereby improving the planarization rate of a sacrificial layer to be removed in the following process and provide the uniformity of overall residual thickness of the sacrificial layer. CONSTITUTION: A planarization layer(130) for planarizing the surface of an active matrix(100) composed of transistors is laminated on an etch stop layer(125). The planarization layer(130) is deposited with a phosphor silicate glass(PSG) or a low temperature oxide(LTO) with excellent step coverage in the thickness of 1.5 to 2.0 micrometer. The planarization layer(130) is polished to planarize the uneven surface thereof by using a CMP method until the surface of the etch stop layer(125) is exposed. So, the even surface is provided by compensating for the step caused by the active matrix(100). A sacrificial layer(135) is provided on the evened planarization layer(130) to form an air gap.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control device using an Actuated Mirror Array (AMA), and more particularly, to a planarization rate of a thin film type optical path control device that can improve the planarization rate of a sacrificial layer by compensating for a step resulting from an active matrix. It relates to a manufacturing method.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, image processing apparatuses using such an optical modulator are classified into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen. do.

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator built into the AMA produces a variation in response to the electric field generated by the applied electrical image signal and bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode therein into an active matrix in which a transistor is built, and then processing by using a sawing method and installing a mirror on the top. . However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is a patent application No. 96-42197 filed by the applicant of the Korean Patent Office on September 24, 1996 (name of the invention: thin film type optical path control device that can control the stress of the membrane and its manufacturing method) Is disclosed.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the preceding application.

First, the structure of the thin film type optical path control device is as follows.

The thin film type optical path control device includes an active matrix 1 and an actuator 60. The active matrix 1 in which M x N (M, N is an integer) MOS transistors and a drain pad 5 extending from the drain region of the MOS transistor is formed in the active matrix 1 and the drain. The protective layer 10 is stacked on the pad 5 and the etch stop layer 15 is stacked on the protective layer.

The actuator 60 contacts one side of the etch stop layer 15 where the drain pad 5 is formed, and the other side of the membrane 30 is horizontally stacked through the air gap 25. The lower electrode 35 stacked on top, the strained layer 40 stacked on top of the lower electrode, the upper electrode 45 stacked on top of the strained layer, and the lower electrode 35 from one side of the strained layer 40. The lower electrode 35 and the drain pad 5 are formed in the via hole 50 vertically formed through the membrane 30, the etch stop layer 15, and the protective layer 10 to the drain pad 5. And a via contact 55 formed to be connected to each other.

A stripe 46 is formed on a portion of the upper electrode 45. The stripe 46 uniformly operates the upper electrode 45 so that light incident from the light source is diffusely reflected at the boundary between the portion of the upper electrode 45 that is deformed and the portion that is not deformed according to the deformation of the strained layer 40. To prevent them.

Hereinafter, the manufacturing method of the said thin film type optical path control apparatus is demonstrated.

Referring to FIG. 1A, an active wafer is formed of an n-type doped silicon wafer, in which M × N (M, N is an integer) P-MOS transistors are formed and a drain pad 5 extending from the drain region of the transistor is formed. A protective layer 10 is formed on the matrix 1 using phosphorus silicate glass PSG. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded during subsequent processing.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched and damaged during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 µm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the MOS transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby forming a support of the actuator 60.

The membrane 30 is stacked on the exposed etch stop layer 15 and the sacrificial layer 20. The membrane 30 is formed by depositing nitride to a thickness of about 0.01 to 1.0 mu m using a low pressure chemical vapor deposition (LPCVD) method.

The lower electrode 35 is stacked on top of the membrane 30. The lower electrode 35 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). Subsequently, the lower electrode 35 is separated for each pixel through a photolithography process so that an independent first signal (image signal) is applied to each pixel (Iso-cutting process). The first signal is applied to the lower electrode 35 through a transistor built in the active matrix 1 from the outside.

A deformation layer 40 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode 35. The strained layer 40 is formed to have a thickness of 0.1 to 1.0 탆 using a sol-gel method, a sputtering method, or a chemical vapor deposition method. Preferably, the strained layer 40 is formed so that PZT has a thickness of about 0.4 µm using the sol-gel method. In addition, the piezoelectric material constituting the strained layer 40 is subjected to heat treatment by a rapid heat treatment (RTA) method to cause phase shift. In the strained layer 40, a second signal (bias signal) is applied to the upper electrode 45, and a first signal is applied to the lower electrode 35, according to a potential difference between the upper electrode 45 and the lower electrode 35. It is deformed by the generated electric field.

The upper electrode 45 is stacked on the deformation layer 40. The upper electrode 45 is formed so as to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. Since the upper electrode 45 has both electrical conductivity and reflectivity at the same time, the upper electrode 45 functions not only as a bias electrode for generating an electric field but also as a mirror for reflecting incident light.

Referring to FIG. 1B, the upper electrode 45, the deformation layer 40, and the lower electrode 35 are sequentially patterned from a top of the upper electrode 45 into a predetermined pixel shape. At this time, a portion of the upper electrode 45 is formed with a stripe 46 to uniformly operate the upper electrode 45 to prevent diffuse reflection of light incident from the light source.

Subsequently, the via hole 50 is etched by sequentially etching the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 from one side of the strained layer 40. Form. Thus, the via hole 50 is formed from one side of the strained layer 40 to the drain pad 5. Subsequently, a metal having electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form the via contact 55. The via contact 55 connects the drain pad 5 and the lower electrode 35. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. Then, the membrane 30 is patterned into a predetermined pixel shape.

Subsequently, the sacrificial layer 20 is etched using hydrogen fluoride (HF) vapor to form an air gap 25 at the position of the sacrificial layer 20, and then a rinse and dry treatment is performed. To complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. At the same time, a second signal is applied to the upper electrode 45 to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the electric field, and the actuator 60 including the strained layer 40 is bent upward at a predetermined angle. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

According to the manufacturing method of the thin film type optical path control apparatus described in the above-described prior application, as shown in FIG. 1A, the sacrificial layer 20 on the etch stop layer 15 is thick enough to overcome the unevenness of the underlying layer, for example, 2. . After deposition to a thickness of 5 μm or more, the sacrificial layer 20 is planarized by a chemical mechanical polishing (CMP) process, and the sacrificial layer 20 is etched through a photolithography process. The support 22 is formed. However, according to the above-described method, the sacrificial layer does not sufficiently achieve flattening of the uneven portion on the active matrix, resulting in a problem of unevenness of the underlying layer appearing on the mirror surface. In addition, since it is difficult to accurately predict the thickness of the sacrificial layer remaining after performing the CMP process on the entire module of the thin film type optical path control device, it is difficult to ensure uniformity of the sacrificial layer thickness. As a result, the thickness of the remaining sacrificial layer is insufficient or excessive in the entire module, thereby lowering the yield.

Accordingly, an object of the present invention is to form a planarization layer, polish the surface of the planarization layer to planarize it, and then form a sacrificial layer using polysilicon thereon, and remove only the sacrificial layer in a subsequent process, thereby resulting in a step resulting from the active matrix. The present invention provides a method of manufacturing a thin film type optical path control apparatus capable of compensating for and improving a planarization rate of a sacrificial layer.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

2 is a plan view of a thin film type optical path control apparatus according to the present invention.

FIG. 3 is a cross-sectional view of the apparatus shown in FIG. 2 taken along line A′A ′.

4A to 4E are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 3.

<Explanation of symbols for main parts of drawing>

100: active matrix 105: first metal layer

110: first protective layer 115: second metal layer

120: second protective layer 125: etch stop layer

130: planarization layer 135: sacrificial layer

140: support layer 145: lower electrode

150 strain layer 155 upper electrode

160: beer hall 165: beer contact

170: mirror 175: air gap

200: actuator

In order to achieve the above object, the present invention provides a method comprising: providing an active matrix including a drain pad in which M x N (M, N is an integer) embedded therein and extending from a drain region of the transistor; Forming a planarization layer on the active matrix; Planarizing the planarization layer by a chemical mechanical polishing (CMP) method; Forming a sacrificial layer using polysilicon on top of the planarized planarization layer; Forming an actuator on the patterned sacrificial layer, the actuator including a support layer, a lower electrode, a strain layer, and an upper electrode; And removing the sacrificial layer using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ).

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, a material having a stable and superior step coverage on the active matrix, preferably phosphorus silicate glass (PSG) having a low concentration of phosphorus (P), Alternatively, a planarization layer made of low temperature oxide (LTO) is formed to a thickness such that the level difference of the underlying layer can be planarized. The planarization layer may be polished by chemical mechanical polishing (CMP) to obtain a flat surface. After the planarization layer is planarized in this manner, a sacrificial layer is formed using polysilicon as a sacrificial layer for forming an air gap, and only the sacrificial layer is removed in a subsequent step. Therefore, the planarization layer can be formed by using a material excellent in step application property and easy to polish, thereby improving the planarization rate of the surface of the planarization layer. In addition, since the sacrificial layer is formed on the planarized planarization layer, the remaining thickness of the sacrificial layer can be easily estimated, and the overall residual thickness uniformity of the sacrificial layer formed on the active matrix can be secured.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

FIG. 2 is a plan view of a thin film type optical path adjusting device according to the present invention, and FIG. 3 is a cross-sectional view taken along line A′A ′ of the apparatus shown in FIG. 2.

2 and 3, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 200, and a mirror 170.

The active matrix 100 having M × N (M, N is an integer) embedded therein includes a first metal layer 105 extending from a source and a drain of the MOS transistor and a first metal layer formed on the first metal layer. The protective layer 110, the second metal layer 115 formed on the first protective layer, the second protective layer 120 formed on the second metal layer, and the etch stop layer 125 formed on the second protective layer. It includes. The first metal layer 105 includes a drain pad extending from the drain of the MOS transistor, and the second metal layer 115 includes a titanium (Ti) layer and a titanium nitride (TiN) layer.

Referring to FIG. 3, one side of the actuator 200 is in contact with a portion in which the drain pad of the first metal layer 105 is formed, and the other side of the actuator 200 is disposed through the air gap 175. The support layer 140 formed horizontally below the active matrix 100, the lower electrode 145 formed on the support layer 140, the strained layer 150 formed on the lower electrode 145, and the strained layer 150. The upper electrode 155 formed on the upper portion of the strained layer 150, the lower electrode 145, the support layer 140, the second protective layer 120, and the first protective layer 1 from one side of the strained layer 150. The via contact 165 is formed to connect the lower electrode 145 and the drain pad to the inside of the via hole 160 vertically formed through the 110 to the drain pad of the first metal layer 105. The support layer 140 functions as a membrane of the thin film type optical path adjusting device described in the previous application.

The support layer 140 has a shape in which a rectangular flat plate is integrally formed with the arms on the same plane between two rectangular arms formed in parallel from both support portions. A mirror 170 is formed on an upper portion of the rectangular flat plate of the support layer 140. Thus, the mirror 170 has the shape of a rectangular flat plate.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

Figures 4a to 4e shows a manufacturing process of the thin film type optical path control apparatus according to the present invention.

Referring to FIG. 4A, after preparing an active matrix 100, which is an n-type doped silicon (Si) wafer, the active matrix 100 is prepared by using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). ) To form an isolation layer for dividing the active region and the field region. Subsequently, a gate made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source and drain are formed by an ion implantation process, thereby forming M x N (M and N are integers). MOS transistors are formed.

After forming an insulating film made of an oxide on the resultant formed MOS transistor, the openings for exposing the top of one side of the source and the drain are formed by a photolithography process. Subsequently, a first metal layer 105 made of a metal such as titanium, titanium nitride, or tungsten (W) is deposited to have a thickness of about 7000 to 8000 kPa on the upper portion of the resultant product in which the openings are formed, and then the first metal layer 105 is deposited. Is patterned by a photolithography process. The patterned first metal layer 105 includes a drain pad extending from the drain of the MOS transistor to one side of the support of the actuator 200.

The first passivation layer 110 is formed on the first metal layer 105. The first passivation layer 110 is formed to have a thickness of about 8000 GPa by using the silicate glass (PSG) chemical vapor deposition (CVD) method. The first protective layer 110 prevents damage to the active matrix 100 in which the MOS transistor is embedded during a subsequent process.

The second metal layer 115 is formed on the first protective layer 110. In order to form the second metal layer 115, first, a titanium layer is formed by sputtering titanium (Ti). Subsequently, titanium nitride is deposited on the titanium layer using a physical vapor deposition (PVD) method to form a titanium nitride layer. The second metal layer 115 is formed to have a thickness of about 2000 to 3000 GPa. The second metal layer 115 prevents light leakage current from flowing through the active matrix 100 because the light incident from the light source is incident not only on the mirror 170 but also on a portion other than the portion where the mirror 170 is formed. . Subsequently, a portion of the second metal layer 115 in which the via contact 165 is to be formed in a subsequent process is etched through a photolithography process to form an opening in the second metal layer 115.

The second passivation layer 120 is formed on the second metal layer 115. The second protective layer 120 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 120 also prevents damage to the active matrix 100 having the transistor embedded therein and the results formed on the active matrix 100 during the subsequent process.

An etch stop layer 125 is formed on the second passivation layer 120. The etch stop layer 125 prevents the active matrix 100 and the second passivation layer 120 from being etched due to a subsequent etching process. The etch stop layer 125 is formed by depositing silicon nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method so as to have a thickness of about 1000 ~ 2000Å.

The planarization layer 130 is stacked on the etch stop layer 125. Since the planarization layer 130 serves to planarize the surface of the active matrix 100 in which the transistor is embedded, a material capable of flattening the level difference of the underlying layer of a stable and excellent step coating property, preferably 1. It is formed by evaporating to a thickness of 5 to 2.0 mu m. The planarization layer 130 is formed by depositing by chemical vapor deposition (CVD) using phosphorus silicate glass (PSG). Preferably, the planarization layer 130 has a concentration of phosphorus (P) that is not easily dissolved in bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ), which is easy to be polished and used in a subsequent etching process. It is formed using low phosphorus silicate glass (PSG), or low temperature oxide (LTO). When the planarization layer 130 is formed using an oxide such as LTO, the step of stacking the etch stop layer 125 under the planarization layer 130 may be omitted. That is, since the planarization layer 130 formed using LTO does not dissolve well in bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ), the second protective layer 120 and the active matrix (below) 100) can perform a sufficient function to protect.

Since the planarization layer 130 covers the upper portion of the active matrix 100 in which the P-MOS transistor is embedded, the planarity of the surface thereof is very poor. Therefore, the surface of the planarization layer 130 is polished and planarized using a chemical mechanical polishing (CMP) method. The planarization layer 130 may be polished until the surface of the etch stop layer 125 is exposed using the lower etch stop layer 125 as the CMP termination layer, or planarized by polishing a portion of the planarization layer 130 remaining. Therefore, as shown in FIG. 4A, a flat surface may be obtained by compensating for a step resulting from the active matrix 100.

Referring to FIG. 4B, the sacrificial layer 135 is formed on the planarization layer 130 planarized as described above. The sacrificial layer 135 is provided to form an air gap 175 in a subsequent process, and the polysilicon is formed at about 600 ° C. by low pressure chemical vapor deposition (LPCVD). It is formed by vapor deposition. As described above, in the present invention, the planarization layer 130 is formed and the upper portion thereof is polished to overcome the step of the active matrix 100 to achieve planarization and to form an air gap with the sacrificial layer 135. The materials of the planarization layer 130 and the sacrificial layer 135 may be appropriately selected and used. Therefore, in the conventional method, the sacrificial layer simultaneously performs two roles of the planarization layer and the sacrificial layer for forming the actuator 200, thereby overcoming the difficulty of material selection involved and determining the thickness of the sacrificial layer during the thin film deposition process. As a result, a much more stable thickness uniformity can be obtained than the uniformity of the sacrificial layer thickness obtained in the chemical mechanical polishing (CMP) process.

Subsequently, the portion of the second passivation layer 120 is exposed by etching the portion of the sacrificial layer 135 in which the opening of the second metal layer 115 is formed and the portion adjacent thereto, thereby supporting the actuator 200. Make a position where the anchor anchor will be formed.

Referring to FIG. 4C, a first layer 139 is formed on the exposed planarization layer 130 and on the sacrificial layer 135. The first layer 139 is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD). The first layer 139 is later patterned into the support layer 140.

A lower electrode layer is formed on the first layer 139 using a metal such as platinum, tantalum, or platinum-tantalum (Pt-Ta), which is a metal having excellent electrical conductivity. The lower electrode layer is formed to have a thickness of about 0.01 to 1.0 탆 using the sputtering method. Subsequently, the lower electrode layer is separated for each pixel so that an independent first signal is applied to each pixel (Iso-cutting process). The lower electrode layer is later patterned into the lower electrode 145. The first electrode transmitted from the transistor embedded in the active matrix 100 is applied to the lower electrode 145.

A second layer made of PZT or PLZT is formed on the lower electrode layer. The second layer is formed to have a thickness of about 0.1 to 1.0 mu m, preferably about 0.4 mu m, using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the second layer is subjected to a heat treatment by a rapid heat treatment (RTA) method to cause phase shift. The second layer is later patterned into strained layer 150. The deformable layer 150 has a second signal applied to the upper electrode 155 and a first signal applied to the lower electrode 145 to generate an electric field generated according to a potential difference between the upper electrode 155 and the lower electrode 145. Causes deformation.

An upper electrode layer is stacked on the second layer. The upper electrode layer is formed of a metal having electrical conductivity and reflectivity, such as platinum, aluminum, or silver, to have a thickness of about 0.01 to 1.0 탆 using a sputtering method.

After applying a first photoresist (not shown) to the upper electrode layer by spin coating, patterning the upper electrode layer to have a mirror-shaped 'C' shape as shown in FIG. 2. The upper electrode 155 is formed. The second signal is applied to the upper electrode 155 through a common electrode line (not shown) from the outside. Subsequently, after removing the first photoresist, a second photoresist (not shown) is applied to the patterned upper electrode 155 and the second layer by spin coating, and then the second layer is The strained layer 150 is formed by patterning the electrode 155 to have a shape of a mirror image 'c' slightly wider than the electrode 155 (see FIG. 2).

After applying a third photoresist (not shown) on the upper electrode 155, the strained layer 150, and the lower electrode layer by spin coating, the lower electrode layer is a mirror image slightly wider than the strained layer 150. The lower electrode 145 is patterned to have a shape of 'c'.

Referring to FIG. 4D, the strained layer 150, the lower electrode 145, the first layer 139, and the etch stop layer are formed from a portion of the strained layer 150 in which an opening of the second metal layer 115 is formed below. The 125, the second passivation layer 120, and the first passivation layer 110 are sequentially etched to form the via hole 160 from one side of the strained layer 150 to the drain pad of the first metal layer 105. Afterwards, the drain pad of the first metal layer 105 and the lower electrode 145 are connected to each other in the via hole 160 by sputtering a metal such as tungsten (W), platinum, aluminum, or titanium. Via contact 165 is formed. Therefore, the via contact 165 is formed from the lower electrode 145 to the top of the drain pad in the via hole 160. The first signal transmitted from the outside is applied to the lower electrode 145 through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 105, and the via contact 165.

Subsequently, a fourth photoresist (not shown) is applied to the patterned lower electrode 145 and the via hole 160 by a spin coating method, and then extended from both supporting portions of the first layer 139. The portion has a rectangular shape slightly wider than the lower electrode 145, and the central portion of the first layer 139 formed integrally with the lower electrode 145 is patterned to have a rectangular flat plate shape to form the support layer 140. That is, as shown in FIG. 2, the support layer 140 has a shape in which rectangular arms extend from both support portions, and a rectangular flat plate having a larger area between these arms is formed integrally with the arms on the same plane. Have Then, the fourth photoresist is removed. As a result of the patterning of the support layer 140 as described above, a portion of the sacrificial layer 135 is exposed.

After applying a fifth photoresist (not shown) on the exposed sacrificial layer 135 and the support layer 140 by spin coating, a rectangular flat plate, which is the center of the support layer 140, is exposed. Pattern as much as possible. In addition, a sputtering method or a chemical vapor deposition method is applied to the upper portion of the center portion of the rectangular exposed support layer 140 having a reflectivity such as silver, platinum, or aluminum to a thickness of about 0.3 to 2.0 μm. To be deposited. Subsequently, after forming the mirror 170 by patterning the deposited metal so that the deposited metal has the same shape as the center portion of the rectangular exposed support layer 140, the fifth photoresist is removed.

Referring to FIG. 4E, the sacrificial layer 135 is etched using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ) to form an air gap 175 at a position of the sacrificial layer 135. Arin and dry treatments are performed to complete the AMA device.

In the above-described thin film type optical path control device according to the present invention, a second signal is applied to the upper electrode 155 through a common electrode line from the outside. At the same time, a first signal is applied to the lower electrode 145 from the outside through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 115, and the via contact 165. An electric field is generated between the electrodes 145 according to the potential difference. Due to this electric field, the deformation layer 150 formed between the upper electrode 155 and the lower electrode 145 causes deformation. The strained layer 150 contracts in a direction perpendicular to the electric field, and thus the actuator 200 including the strained layer 150 and the support layer 140 is bent at a predetermined angle. Since the mirror 170 reflecting the light incident from the light source is formed above the central portion of the support layer 140, the mirror 170 is bent at the same angle as the actuator 200. Accordingly, the mirror 170 reflects the incident light at a predetermined angle, and the reflected light passes through the slit to be projected onto the screen to form an image.

According to the manufacturing method of the thin film type optical path control device according to the present invention, after forming a planarization layer on the etch stop layer to a thickness enough to flatten the step of the underlying layer, the surface of the planarization layer is chemical mechanical polishing (CMP The method can be polished to overcome the steps resulting from the active matrix to obtain a flat surface. After the planarization layer is planarized in this manner, a sacrificial layer is formed using polysilicon as a sacrificial layer for forming an air gap, and only the sacrificial layer is removed in a subsequent process.

Therefore, the planarization layer can be formed by using a material excellent in step application property and easy to polish, thereby improving the planarization rate of the surface of the planarization layer. In addition, since the sacrificial layer is formed on the planarized planarization layer, the remaining thickness of the sacrificial layer can be easily estimated, and the overall residual thickness uniformity of the sacrificial layer formed on the active matrix can be secured. As a result, it is possible to reduce the defect of the device caused by excessive polishing of the sacrificial layer.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

Claims (3)

Providing an active matrix having M × N (M, N is an integer) embedded therein and including a drain pad extending from the drain region of the transistor; Forming a planarization layer on the active matrix; Planarizing the planarization layer by a chemical mechanical polishing (CMP) method; Forming a sacrificial layer using polysilicon on top of the planarized planarization layer; Forming an actuator on the patterned sacrificial layer, the actuator including a support layer, a lower electrode, a strain layer, and an upper electrode; And And removing the sacrificial layer using bromine fluoride (BrF ₃ ) or xenon fluoride (XeF ₂ ). The method of claim 1, wherein the forming of the planarization layer is performed using phosphorus silicate glass (PSG) or low temperature oxide (LTO) having a low concentration of phosphorus (P). . The method of claim 1, wherein the forming of the planarization layer is performed after laminating an etch stop layer on the active matrix.

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