KR100256793B1 - Manufacturing method for thin flim actuated mirror array - Google Patents

Abstract

PURPOSE: A thin-film micromirror array-actuated(TMA) manufacturing method is provided to prevent a hydrogen fluoride vapor from permeating an active matrix or an active layer through an Iso-Cut part during the etching process of a sacrificial layer, thereby minimizing the damage of the active matrix or the active layer. CONSTITUTION: An Iso-Cut part region of the etch passivation layer(130) is formed by laminating a silicon nitride or an amorphous silicon on an etch stop layer(125) in the thickness of 1.5 to 2.0 micrometer by a plasma enhanced CVD method. The silicon nitride or the amorphous silicon with an excellent etching resistance against hydrogen fluoride vapor is formed by reacting a reaction gas composed of only a nitrous oxide and a silane except for an ammonia. The Iso-Cut part region of the etch passivation layer(130) remains and the etch stop layer(125) is exposed through the etched other region, after the patterning of the etch passivation layer(130) using a mask for covering only the Iso-Cut part region of the etch passivation layer(130). A sacrificial layer(135) is formed on the exposed etch stop layer(125) and the etch passivation layer(130). An air gap is formed in the position of the sacrificial layer(135) by etching the sacrificial layer(135) with the hydrogen fluoride vapor. At this time, the etch passivation layer(130) shields the lower of the Iso-Cut part region.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using an Actuated Mirror Array (AMA). More specifically, when the etching process for patterning the strain layer, the lower electrode, and the support layer into a pixel shape is performed, The present invention relates to a method for manufacturing a thin film type optical path control device that can prevent damage.

Spatial light modulators, which are devices for projecting optical energy onto a screen, can be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (10% or more) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect the incident light at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is a patent application No. 96-42197 filed by the applicant of the Korean Patent Office on September 24, 1996 Is disclosed.

Figure 1b shows a cross-sectional view of the thin film type optical path control device described in the preceding application.

Referring to FIG. 1B, the thin film type optical path adjusting device includes an active matrix 1 and an actuator 60. The active matrix 1 in which M x N (M, N is an integer) MOS transistors and a drain pad 5 extending from the drain region of the transistor is formed in the active matrix 1 and the drain pad 5. The protective layer 10 stacked on top of the protective layer 10 and the etch stop layer 15 stacked on the protective layer 10 is included.

The actuator 60 is a membrane formed on the lower portion of the active matrix 1 horizontally through the air gap 25 with one side contacting the portion where the drain pad 5 is formed below the etch stop layer 15. 30, the lower electrode 35 stacked on the membrane 30, the strained layer 40 stacked on the lower electrode 35, and the upper electrode 45 stacked on the strained layer 40. And a lower portion in the via hole 50 formed vertically from one side of the strained layer 40 to the drain pad 5 through the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. The via 35 includes a via contact 55 formed to electrically connect the electrode 35 and the drain pad 5 to each other.

A stripe 46 is formed on a part of the upper electrode 45. The stripe 46 operates the upper electrode 45 uniformly so that the light incident from the light source is diffusely reflected at the boundary between the portion of the upper electrode 45 which is deformed and the portion which is not deformed according to the deformation of the deforming layer 40. prevent.

Hereinafter, a manufacturing method of the thin film type optical path control device will be described with reference to FIGS. 1A to 1B.

Referring to FIG. 1A, an M × N (M, N is an integer) element is formed on an active matrix 1 in which a MOS transistor (not shown) is embedded and a drain pad 5 extending from a drain region of the MOS transistor is formed. A protective layer 10 composed of silicate glass PSG is formed. The protective layer 10 is formed to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the transistor is embedded during subsequent processing.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 10 and the active matrix 1 from being etched and damaged during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 μm by using an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby making a position where the support of the actuator 60 is to be formed.

Referring to FIG. 1B, the membrane 30 is formed on the exposed etch stop layer 15 and the sacrificial layer 20 to a thickness of about 0.1 μm to about 1.0 μm. Membrane 30 is formed using low pressure chemical vapor deposition (LPCVD). At this time, by forming the membrane 30 while varying the ratio of the reaction gas in the reaction vessel of low pressure, the stress in the membrane 30 is controlled.

On the membrane 30, a lower electrode 35 made of a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum is formed. Subsequently, the lower electrode 35 is separated for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso­Cut etching process).

On the lower electrode 35, a strained layer 40 made of a piezoelectric material such as PZT or PLZT is formed. The strained layer 40 is formed to have a thickness of about 0.1 μm to about 1.0 μm, preferably about 0.4 μm using a sol-gel method, and then heat treated by a rapid heat treatment (RTA) method. Phase change the piezoelectric material constituting 40). In the strained layer 40, a second signal (bias signal) is applied to the upper electrode 45, and a first signal is applied to the lower electrode 35, according to a potential difference between the upper electrode 45 and the lower electrode 35. It is deformed by the generated electric field.

The upper electrode 45 is formed on the strained layer 40. The upper electrode 45 is formed of a metal having electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 0.1 to 1.0 μm using a sputtering method. The second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside. The upper electrode 45 functions not only as a bias electrode for generating an electric field but also as a mirror for reflecting light incident from a light source.

Subsequently, the upper electrode 45 is patterned into a predetermined pixel shape. In this case, the stripe 46 is patterned to form a portion of the upper electrode 45. Subsequently, the strained layer 40 and the lower electrode 35 are sequentially patterned into a predetermined pixel shape, and then, from one side of the strained layer 40 to an upper portion of the drain pad 5, the strained layer 40 and the bottom thereof. The via hole 50 is formed by sequentially etching the electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. Subsequently, a metal such as tungsten, platinum or titanium is deposited by a lift-off method to form a via contact 55 that electrically connects the drain pad 5 and the lower electrode 35. Thus, the via contact 55 is formed vertically from the lower electrode 35 to the top of the drain pad 5 in the via hole 50. Therefore, the first signal applied from the outside is applied to the lower electrode 35 through the transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1.

Subsequently, a photoresist (not shown) is applied to the entire surface of the resultant in which the via contact 55 is formed and patterned to expose the membrane 30. Subsequently, the membrane 30 is patterned into a predetermined pixel shape using a photoresist as a mask. The air gap 25 is formed by etching the sacrificial layer 20 using 49% hydrogen fluoride (HF) vapor, followed by a cleaning and drying process to complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. At the same time, a second signal is applied to the upper electrode 45 through a common electrode line (not shown) from the outside to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the generated electric field, and the actuator 60 including the strained layer 40 is bent upward at a predetermined angle. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described manufacturing method of the thin film type optical path control apparatus, there is a problem that the Iso­Cut part is damaged when etching processes for patterning the strained layer, the lower electrode, and the membrane into a predetermined pixel shape, respectively. This will be described in more detail with reference to the drawings.

2 is a plan view showing an enlarged Iso_Cut part in the above-described thin film type optical path control device.

Referring to FIG. 2, in the above-described method for manufacturing a thin film type optical path control apparatus, an IsoCut part (eg, an IsoCut part) may be used to perform etching processes for patterning the deformable layer 40, the lower electrode 35, and the membrane 30 into a predetermined pixel shape. A) is exposed without being covered with a photoresist (not shown). Thus, during the etching process, the membrane 30 of the Iso­Cut portion A is over-etched and etched down to the lower etch stop layer 15. As a result, when the sacrificial layer 20 is etched using hydrogen fluoride vapor, hydrogen fluoride vapor penetrates through the etched portion of the etch stop layer 15 so that the protective layer 10 and the transistor below The problem arises that the embedded active matrix 1 or a strained layer made of a piezoelectric material such as PZT on top thereof is damaged.

Therefore, an object of the present invention is a thin film type optical path that can prevent damage to the protective layer and the active matrix under the IsoCut part when etching processes for patterning the thin films constituting the actuator, such as the strain layer, the lower electrode, and the support layer, into pixel shapes, respectively. It is to provide a method for producing a control device.

1A and 1B are cross-sectional views illustrating a method of manufacturing a thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is an enlarged plan view of an IsoutCut part in a thin film type optical path adjusting device according to the manufacturing method described in the preceding application. FIG.

3 is a plan view of a thin film type optical path control apparatus according to the present invention.

4 is an enlarged perspective view of the apparatus shown in FIG. 3.

FIG. 5 is a cross-sectional view of the apparatus shown in FIG. 3 taken along line A′A ′.

6A to 6C are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 5.

<Explanation of symbols for main parts of drawing>

100: active matrix 105: first metal layer

110: first protective layer 115: second metal layer

120: second protective layer 125: etch stop layer

130: etching protective layer 135: sacrificial layer

140: support layer 145: lower electrode

150 strain layer 155 upper electrode

160: beer hall 165: beer contact

170: mirror 175: air gap

200: actuator

In order to achieve the above object, the present invention provides an active matrix including a drain pad in which M x N (M, N is an integer) transistors are built in and extend from the drain of the transistor. An etch stop layer is formed on the active matrix. An etch protective layer is formed using silicon nitride or amorphous silicon formed by reacting a reaction gas containing no ammonia on top of the etch stop layer, and is patterned, leaving only a portion of the area, and removing the remaining area. After the sacrificial layer is laminated on the etch protection layer, the surface is planarized. The sacrificial layer is patterned to expose portions of the active matrix in which drain pads are formed. After forming the first and lower electrode layers on the exposed active matrix and the sacrificial layer, the lower electrode layer is Iso­Cut for each pixel. The second layer and the upper electrode layer are formed on the lower electrode layer, and then sequentially etched into pixel shapes to form the upper electrode, the strain layer, the lower electrode, and the support layer, and a mirror is formed on the support layer. By removing the sacrificial layer to form an air gap, the thin film type optical path control device is completed.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming the etching prevention layer, the silicon nitride formed by reacting a reaction gas containing ammonia (NH ₃ ) having high etching resistance to hydrogen fluoride vapor ( An etching protection layer is formed using silicon nitride or amorphous silicon. The etch protective layer is patterned using a mask covering only the IsoCut portion to leave the etch protective layer of the IsoCut portion and the rest is etched.

Therefore, since the etch protective layer protects the IsoCut portion, the hydrogen fluoride vapor penetrates into the active matrix or the strained layer through the IsoCut portion during the etching process of the sacrificial layer using the hydrogen fluoride vapor to damage the active matrix or the strained layer. I can prevent wearing.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

Figure 3 is a plan view of a thin film type optical path control apparatus according to the present invention, Figure 4 shows an enlarged perspective view of the device shown in Figure 3, Figure 5 is a AA 'line of the device shown in Figure 3 It shows a cut section.

3, 4, and 5, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 200, and a mirror 170.

The active matrix 100 having M × N (M, N is an integer) P-MOS transistors includes a first metal layer 105 and a first metal layer 105 extending from a source and a drain of the MOS transistor. The first passivation layer 110 formed on the upper portion, the second metal layer 115 formed on the first passivation layer 110, the second passivation layer 120 formed on the second metal layer 115, and the second The etch stop layer 125 is formed on the passivation layer 120. The first metal layer 105 includes a drain pad extending from the drain of the MOS transistor, and the second metal layer 115 is formed of a titanium (Ti) layer and a titanium nitride (TiN) layer.

Referring to FIG. 4, the actuator 200 has one side in contact with a portion of the etch stop layer 125 in which a drain pad of the first metal layer 105 is formed, and the other side thereof has an active matrix (eg, an air gap 175). The support layer 140 formed horizontally with the lower portion of the lower portion 100, the lower electrode 145 formed on the upper portion of the support layer 140, the strained layer 150 formed on the lower electrode 145, the upper portion of the strained layer 150 The upper electrode 155 and the strained layer 150, the lower electrode 145, the support layer 140, the etch stop layer 125, the second protective layer 120, and the first protection from one side of the strained layer 150. The via contact 165 may be formed to connect the lower electrode 145 and the drain pad to the via hole 160 formed vertically through the layer 110 to the drain pad of the first metal layer 105. The support layer 140 performs the function of a membrane supporting the actuator of the thin film optical path control device described in the previous application.

The support layer 140 has a shape in which a rectangular flat plate is integrally formed with the arms on the same plane between two rectangular arms formed in parallel from both support portions. The mirror 170 is formed on the rectangular flat plate of the support layer 140. Thus, the mirror 170 has the shape of a rectangular flat plate.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

6a to 6c show a manufacturing process of the thin film type optical path control apparatus according to the present invention.

Referring to FIG. 6A, after preparing an active matrix 100, which is an n-type doped silicon (Si) wafer, the active matrix 100 is prepared using a conventional device isolation process, for example, silicon partial oxidation (LOCOS). An isolation layer for forming an active region and a field region is formed on the substrate. Subsequently, after forming a gate made of a conductive material such as polysilicon doped with impurities on top of the active region, p ⁺ sources and drains are formed by an ion implantation process, whereby M × N (M and N are integers) P -Form a MOS transistor;

After forming an insulating film made of an oxide on top of the resultant P-MOS transistor is formed, openings for exposing the top of one side of the source and the drain, respectively, by a photolithography process. Subsequently, a first metal layer 105 made of a metal such as titanium, titanium nitride, or tungsten (W) is deposited on the resultant, on which the openings are formed, and then the first metal layer 105 is patterned by a photolithography process. The first metal layer 105 patterned as described above includes a drain pad extending from the drain of the P-MOS transistor to one side of the support of the actuator 200.

The first passivation layer 110 is formed on the first metal layer 105. The first passivation layer 110 is formed to have a thickness of about 8000 GPa by using the silicate glass (PSG) chemical vapor deposition (CVD) method. The first protective layer 110 prevents damage to the active matrix 100 in which the MOS transistor is embedded during the subsequent process.

The second metal layer 115 is formed on the first protective layer 110. In order to form the second metal layer 115, first, a titanium layer is formed by sputtering titanium (Ti) to a thickness of about 300 μm. Subsequently, titanium nitride is deposited on top of the titanium layer using a physical vapor deposition (PVD) method to form a titanium nitride layer. The second metal layer 115 prevents light leakage current from flowing through the active matrix 100 because the light incident from the light source is incident not only on the mirror 170 but also on a portion other than the portion where the mirror 170 is formed. . Subsequently, a portion of the second metal layer 115 in which the via contact 165 is to be formed in a subsequent process is etched through a photolithography process to form an opening in the second metal layer 115.

The second passivation layer 120 is formed on the second metal layer 115. The second protective layer 120 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 120 also prevents damage to the active matrix 100 in which the MOS transistor is embedded and the results formed on the active matrix 100 during the subsequent process.

An etch stop layer 125 is formed on the second passivation layer 120. The etch stop layer 125 prevents the active matrix 100 and the second passivation layer 120 from being etched due to the subsequent etching process. The etch stop layer 125 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

An etch protection layer 130 is formed on the etch stop layer 125. The etching protective layer 130 is formed of silicon nitride or amorphous silicon formed by reacting a reaction gas consisting of only nitrous oxide (N ₂ O) and silane (SiH ₄ ) except for ammonium (NH ₃ ). ．It is formed by laminating with thickness of about 0㎛. The etching protection layer 130 is formed of silicon nitride or amorphous silicon using a plasma enhanced CVD (PECVD) method.

Subsequently, the etching protection layer 130 is patterned using a mask covering only the IsoCut part of the etching protection layer 130 to leave the etching protection layer of the IsoCut subregion, and the remaining area is etched to expose the lower etching prevention layer 125. .

The sacrificial layer 135 is formed on the exposed etch stop layer 125 and the etch protection layer 130. The sacrificial layer 135 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to about 3.0 μm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 135 covers the upper portion and the etch protection layer 130 of the active matrix 100 in which the P-MOS transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 135 is planarized by polishing the surface of the sacrificial layer 135 using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method so that the thickness of the sacrificial layer 135 is about 1 .mu.m. . In this case, the etch protection layer 130 formed in the Iso­Cut subregion is also polished to be planarized together with the sacrificial layer 135 while the upper portion of the etch protection layer 130 is exposed.

Subsequently, the portion of the sacrificial layer 135 having the opening of the second metal layer 115 formed thereon and an adjacent portion thereof are etched to expose a portion of the etch stop layer 125, thereby anchoring an anchor which is a support of the actuator 200. Make a position to form.

Referring to FIG. 6B, the first layer 139 is formed on the exposed etch stop layer 125, the sacrificial layer 135, and the etch passivation layer 130. The first layer 139 is formed to have a thickness of about 0.1 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD). The first layer 139 is later patterned into the support layer 140.

The lower electrode layer 144 is formed on the first layer 139 by using a metal such as platinum, tantalum, or platinum-tantalum (Pt-Ta), which is a metal having excellent electrical conductivity. The lower electrode layer 144 is formed to have a thickness of about 0.01 to 1.0 탆 using a sputtering method. Subsequently, the lower electrode layer 144 is separated for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso­Cut process). The lower electrode layer 144 is later patterned into the lower electrode 145. The first signal transferred from the transistor embedded in the active matrix 100 is applied to the lower electrode 145.

The second layer 149 is stacked on the lower electrode layer 144. The second layer 149 is formed using a piezoelectric material such as PZT or PLZT to have a thickness of about 0.1 to 1.0 탆, preferably about 0.4 탆. The second layer 149 is formed by using a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method, and then thermally transformed by a rapid heat treatment (RTA) method to phase change. The second layer 149 is later patterned into the strained layer 150. In the strained layer 150, a second signal (bias signal) is applied to the upper electrode 155, and a first signal is applied to the lower electrode 145, according to a potential difference between the upper electrode 155 and the lower electrode 145. It is deformed by the generated electric field.

The upper electrode layer 154 is stacked on the second layer 149. The upper electrode layer 154 is formed of a metal having electrical conductivity and reflectivity, such as platinum, aluminum, or silver, to have a thickness of about 0.01 to 1.0 탆 using a sputtering method.

Referring to FIG. 6C, after the first photoresist (not shown) is coated on the upper electrode layer 154 by spin coating, the upper electrode layer 154 may be mirror imaged as shown in FIG. 4. The upper electrode 155 is formed by patterning to have a shape of 'c'. The second signal is applied to the upper electrode 155 through a common electrode line (not shown) from the outside. Subsequently, after removing the first photoresist, a second photoresist (not shown) is applied on the patterned upper electrode 155 and the second layer 149 by spin coating, and then the second layer 149 ) Is patterned to have a mirror-shaped 'c' shape slightly wider than the upper electrode 155 to form a strained layer 150 (see FIG. 4). Subsequently, the second photoresist is removed and a third photoresist (not shown) is applied on the upper electrode 155, the deformation layer 150, and the lower electrode layer 144 by spin coating, and then the lower electrode layer is applied. The lower electrode 145 is formed by patterning the 144 to have a mirror-shaped 'c' shape slightly wider than the strained layer 150.

Next, the strained layer 150, the lower electrode 145, the first layer 139, the etch stop layer 125, and the first layer are formed from a portion of the strained layer 150 in which an opening of the second metal layer 115 is formed below. The protective layer 120 and the first protective layer 110 are sequentially etched to form the via hole 160 from one side of the strained layer 150 to the drain pad of the first metal layer 105. The via contact 165 is formed in the inside of the 160 to connect the drain pad of the first metal layer 105 and the lower electrode 145 by sputtering a metal such as tungsten (W), platinum, aluminum, or titanium. do. Therefore, the via contact 165 is formed from the lower electrode 145 to the top of the drain pad in the via hole 160. The first signal transmitted from the outside is applied to the lower electrode 145 through the transistor embedded in the active matrix 100, the drain pad of the first metal layer 105, and the via contact 165.

Subsequently, after the fourth photoresist (not shown) is applied to the patterned lower electrode 145 and the via hole 160 by the spin coating method, a portion extending from both supporting portions of the first layer 139. Silver has a slightly wider rectangular shape than the lower electrode 145, and the center portion of the first layer 139 formed integrally with the lower electrode 145 is patterned to have a rectangular flat plate shape to form the support layer 140. That is, as shown in FIG. 4, the support layer 140 has a shape in which rectangular arms extend from both support portions, and a rectangular flat plate having a larger area between these arms is formed integrally with the arms on the same plane. Have Then, the fourth photoresist is removed. As a result of the patterning of the support layer 140 as described above, a portion of the sacrificial layer 135 is exposed.

Subsequently, a fifth photoresist (not shown) is applied on the exposed sacrificial layer 135 and the support layer 140 by spin coating, and then a rectangular flat plate, which is the center of the support layer 140, is exposed. Pattern as much as possible. In addition, a sputtering method or a chemical vapor deposition method is used to form a metal having reflective properties such as silver, platinum, or aluminum on the upper portion of the central portion of the rectangular exposed support layer 140 in a thickness of about 0.3 to 2.0 µm. By deposition. Subsequently, the deposited metal is patterned so that the deposited metal has the same shape as the central portion of the rectangular exposed support layer 140 to form the mirror 170, and then the fifth photoresist is removed.

Subsequently, the sacrificial layer 135 is etched using hydrogen fluoride vapor to form an air gap 175 at the position of the sacrificial layer 135. In this case, the lower part of the IsoCut part is etched on the etch protective layer 130 made of silicon nitride or amorphous silicon formed by reacting a material having excellent etching resistance against hydrogen fluoride vapor, such as ammonia (NH ₃ ). Since it is blocked by the IsoCut part, hydrogen fluoride vapor can be prevented from penetrating into the active matrix 100 or the strained layer 150. The sacrificial layer 135 is etched and removed as described above, followed by rinsing and drying to complete the thin film type optical path control device.

In the above-described thin film type optical path control device according to the present invention, a second signal is applied to the upper electrode 155 through a common electrode line from the outside. At the same time, the first signal is applied to the lower electrode 145 through the transistor embedded in the active matrix 100 from the outside, the drain pad of the first metal layer 105, and the via contact 165. An electric field is generated between the electrodes 145 according to the potential difference. Due to this electric field, the deformation layer 150 formed between the upper electrode 155 and the lower electrode 145 causes deformation. The strained layer 150 contracts in a direction orthogonal to the generated electric field, and the actuator 200 including the strained layer 150 and the support layer 140 is bent at a predetermined angle. Since the mirror 170 reflecting the light incident from the light source is formed above the central portion of the support layer 140, the mirror 170 is bent at the same angle as the actuator 200. Accordingly, the mirror 170 reflects the incident light at a predetermined angle, and the reflected light passes through the slit to be projected onto the screen to form an image.

As described above, according to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming the etch stop layer, it is formed by reacting a reaction gas containing no ammonia (NH ₃ ) with high etching resistance to hydrogen fluoride vapor One silicon nitride or amorphous silicon is used to form an etch protective layer. The etch protective layer is patterned using a mask covering only the IsoCut portion to leave the etch protective layer of the IsoCut portion and the rest is etched.

Therefore, since the etch protective layer protects the IsoCut portion, hydrogen fluoride vapor penetrates into the active matrix or strain layer through the IsoCut portion during the etching process of the sacrificial layer using hydrogen fluoride vapor, thereby causing damage to the active matrix or strain layer. You can prevent it.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

Providing an active matrix comprising M × N (M, N is an integer) transistors and including drain pads extending from the drains of the transistors; Forming an etch stop layer on the active matrix; Forming an etch protective layer using silicon nitride or amorphous silicon formed by reacting a reaction gas containing no ammonia on top of the etch stop layer, and patterning the etch protective layer to remove only the remaining regions; Stacking a sacrificial layer on top of the etch protection layer and then planarizing the surface; Patterning the sacrificial layer to expose a portion of the active matrix in which a drain pad is formed; i) forming a first layer on top of the exposed active matrix and the sacrificial layer, ii) forming a bottom electrode layer on top of the first layer, and then IsoCut the bottom electrode layer for each pixel; ) Forming a second layer and an upper electrode layer on the lower electrode layer; i) sequentially etching the upper electrode layer, the second layer, the lower electrode layer, and the first layer into a pixel shape to form an upper electrode, a deformation layer, and a lower electrode. And forming a support layer, and iii) forming a mirror on top of the support layer; And And removing the sacrificial layer to form an air gap. The method of claim 1, wherein the etching protection layer is formed using a plasma-enhanced chemical vapor deposition (PECVD) method. The method of claim 1, wherein the planarizing the surface of the sacrificial layer is performed by polishing the surface of the sacrificial layer until the top of the etch protection layer is exposed. The method of claim 1, wherein the etching protection layer is patterned to be formed below an Iso­Cut part of the lower electrodes.

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