KR19990004783A - Thin film type optical path controller - Google Patents

Abstract

A thin film type optical path control device is disclosed. The apparatus includes an active matrix in which M × N MOS transistors are embedded and including a first metal layer, and an actuator formed on the active matrix. The first metal layer is patterned larger than the pattern of the active region in which the source / drain is formed. The actuator may include: i) a support layer on one side of which is in contact with the top of the active matrix and the other side of the actuator being formed parallel to the active matrix via an air gap; ii) a bottom electrode formed on the top of the support layer; And a strained layer formed on the strained layer, and iii) an upper electrode formed on the strained layer. Since the first metal layer blocks the source / drain depletion layer of the MOS transistor that may generate the light leakage current, the light leakage current may be minimized.

Description

Thin Film Type Light Path Regulator

The present invention relates to a thin film type optical path control device using an Actuated Mirror Array (AMA), and more particularly, to change a first metal layer pattern of an active matrix to reduce metal contact resistance and to provide a photo leakage current (photo-) in the active matrix. The present invention relates to a thin-film optical path control device capable of reducing leakage current.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 97-11058 (Invention name: Method of manufacturing thin film type optical path control device) filed by the applicant to the Korean Patent Office.

FIG. 1 is a plan view of an active matrix in the thin film type optical path adjusting device described in the preceding application, and FIG. 2 is a cross-sectional view taken along line A′A ′ of the active matrix. 3 is a cross-sectional view of a thin film type optical path adjusting device taken along a line B′B ′ of FIG. 1.

1 to 3, the thin film type optical path control apparatus includes an active matrix 10 and an actuator 40 formed on the active matrix 10.

The active matrix 10 includes a first metal layer 15 stacked on top of an active matrix 10 having M × N MOS transistors and a first protective layer 20 stacked on top of the first metal layer. , A second metal layer 25 stacked on top of the first passivation layer, a second passivation layer 30 stacked on top of the second metal layer, and an etch stop layer 35 stacked on top of the second passivation layer. It includes. The first metal layer 15 includes a gate line 11 connected to the gate 2 of the MOS transistor, a source line 12 connected to the source 3, and a drain pad 13 connected to the drain 4. . The second metal layer 25 includes a first layer 25a made of titanium (Ti) and a second layer 25b made of titanium nitride (TiN), and a portion where the via contact 75 is to be formed is opened. (Reference numeral 26 in FIG. 1).

The actuator 40 has a membrane 45 stacked in parallel with the etch stop layer 35 through one side of the etch stop layer 35 and a side thereof in contact with a portion where the drain pad is formed, and the other side through the air gap 80. The lower electrode 50 stacked on the membrane 45, the strained layer 55 stacked on the lower electrode 50, the upper electrode 60 stacked on the strained layer 55, and the strain The drain from one side of the layer 55 through the strained layer 55, the lower electrode 50, the membrane 45, the etch stop layer 35, the second protective layer 30, and the first protective layer 20. And a via contact 75 formed inside the via hole 70 vertically up to the pad 13.

A stripe 65 is formed at the center of the upper electrode 60 to uniformly operate the upper electrode 60 to prevent diffuse reflection of light incident from the light source.

In Fig. 1, the hatched portions represent active regions in which the sources / drains 3 and 4 are formed.

Hereinafter, the manufacturing method of the said thin film type optical path control apparatus is demonstrated.

First, an active matrix 10 made of silicon (Si) doped with n-type is prepared, and then an isolation layer for separating an active region and a field region from the active matrix 10 using a conventional device isolation process ( To form 1). Subsequently, a gate 2 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then a p ⁺ source 3 and a drain 4 are formed by an ion implantation process. N (M, N are integer) PMOS transistors are formed.

After the insulating film 5 made of oxide is formed on the resultant formed transistor, the openings exposing the upper portions of one side of the gate 2, the source 3, and the drain 4 are formed by a photolithography process. . Subsequently, after depositing the first metal layer 15 made of a metal such as tungsten (W) on the resultant product on which the openings are formed, the first metal layer 15 is patterned by a photolithography process to thereby form the gate 2. A gate line 11 connected to the source line, a source line 12 connected to the source 3, and a drain pad 13 connected to the drain 4 are formed.

Subsequently, a first protective layer 20 is formed on the first metal layer 15 to protect the active matrix 10 having the transistor embedded therein. The first protective layer 20 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 8000 kW using a chemical vapor deposition (CVD) method. The first protective layer 20 prevents the transistor embedded in the active matrix 10 from being damaged during subsequent processing.

The second metal layer 25 is formed on the first protective layer 20. In order to form the second metal layer 25, first, a titanium (Ti) metal is sputtered to form the first layer 25a having a thickness of about 300 μm. Subsequently, titanium nitride (TiN) is stacked on the first layer 25a by using a physical vapor deposition method to form a second layer 25b. Since the light incident from the light source is incident not only to the upper electrode 60, which is a reflective layer, but also to a portion other than the portion where the upper electrode 60 is formed, the second metal layer 25 allows light leakage current to flow through the active matrix 10. Prevent it. Subsequently, a portion of the second metal layer 25 in which the via contact 75 is to be formed is etched and patterned in a subsequent process.

The second protective layer 30 is stacked on the second metal layer 25. The second protective layer 30 is formed to a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 30 also prevents the transistor embedded in the active matrix 10 from being damaged during subsequent processing.

An etch stop layer 35 is stacked on the second passivation layer 30. The etch stop layer 35 is formed by depositing nitride to a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 35 prevents the active matrix 10 and the second passivation layer 30 from being etched due to a subsequent etching process.

The sacrificial layer 37 is stacked on the etch stop layer 35. The sacrificial layer 37 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to 3.0 μm by the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 37 covers the upper portion of the active matrix 10 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 37 is formed so that the sacrificial layer 37 is about 1.1 μm thick by using spin on glass (SOG) or chemical mechanical polishing (CMP). It is flattened by grinding. Subsequently, a portion of the sacrificial layer 37 having a drain pad formed thereon is etched to expose a portion of the etch stop layer 35, thereby forming a support 38 of the actuator.

The membrane 45 is stacked on top of the exposed etch stop layer 35 and on top of the sacrificial layer 37. The membrane 45 is formed by depositing nitride to a thickness of about 0.01 to 1.0 탆 using low pressure chemical vapor deposition (LPCVD).

Subsequently, a lower electrode 50 is stacked on top of the membrane 45. The lower electrode 50 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). At the same time, the lower electrode 50 is separated for each pixel so that a unique first signal (image signal) is applied to each pixel (Iso-Cutting process). The first electrode (image signal) transmitted from the transistor embedded in the active matrix 10 is applied to the lower electrode 50.

On top of the lower electrode 50, a strain layer 55 composed of PZT or PLZT is stacked. The strained layer 55 may have a thickness of about 0.1 to 1.0 μm, preferably about 0.4 μm using a sol-gel method, a sputtering method, or a chemical vapor deposition method. Form. In addition, the strained layer 55 is subjected to a heat treatment by a rapid heat treatment (RTA) method to phase change. The strained layer 55 is deformed by an electric field generated between the upper electrode 60 and the lower electrode 50.

The upper electrode 60 is stacked on the deformation layer 55. The upper electrode 60 is formed to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). The second electrode (bias signal) is applied to the upper electrode 60 through a common electrode line (not shown). Since the upper electrode 60 has excellent electrical conductivity and reflection characteristics, the upper electrode 60 performs not only a function of a bias electrode generating an electric field but also a function of a mirror reflecting incident light.

Subsequently, the upper electrode 60, the strain layer 55, and the lower electrode 50 are sequentially patterned from a top of the upper electrode 60 into a predetermined pixel shape. In this case, a stripe 65 is formed on one side of the upper electrode 60 to uniformly operate the upper electrode 60 to prevent diffuse reflection of light incident from the light source.

Subsequently, the strained layer 55, the lower electrode 50, the membrane 45, the etch stop layer 35, the second protective layer 30, and the first protective layer 20 are removed from one side of the strained layer 55. The via holes 70 are sequentially formed by etching. Accordingly, the via hole 70 is formed from the other side of the strained layer 55 to the drain pad 13 of the first metal layer 15. Subsequently, a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 75. The via contact 75 electrically connects the drain pad 13 and the lower electrode 50 of the first metal layer 15. Therefore, the first signal applied from the outside is applied to the lower electrode 50 through the transistor, the drain pad 13, and the via contact 75 embedded in the active matrix 10. Subsequently, after the membrane 45 is patterned into a predetermined pixel shape, the sacrificial layer 37 is etched using hydrogen fluoride (HF) vapor to form an air gap 80, followed by cleaning and drying. dry) to complete the AMA device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 50 through the MOS transistor, the drain pad 13, and the via contact 75 embedded in the active matrix 10. In addition, a second signal is applied to the upper electrode 60 to generate an electric field between the upper electrode 60 and the lower electrode 50. By this electric field, the strain layer 55 laminated between the upper electrode 60 and the lower electrode 50 causes deformation. The strained layer 55 contracts in a direction orthogonal to the electric field, and the actuator 40 including the strained layer 55 is bent upward at a predetermined angle. Therefore, the upper electrode 60 on the actuator 40 also inclines in the same direction. Light incident from the light source is reflected by the upper electrode 60 at a predetermined angle, and then is projected onto the screen to form an image.

However, according to the above-described thin film type optical path adjusting device, as shown in FIG. 2, the light emitted from the light source is separated from the depletion layer 8 of the source / drain 3 and 4 of the MOS transistor. It enters into the part C which is in contact with the edge of 1). As such, light incident in the depletion layer 8 generates a large amount of electron-hole pairs, and the generated minority carriers are all sourced / drained by the drift electric field applied to the depletion layer 8. 3, 4), light leakage current is generated in the active matrix 10. In addition, even when the MOS transistor is turned off, a minority carrier introduced into the drain 4 flows into the lower electrode 50 through the drain pad 13, so that charge is charged to the lower electrode 50. Accumulate. As a result, a potential difference occurs between both ends of the strained layer 55, and the strained layer 55 is tilted, thereby causing a problem in that the turn-off operation is not properly performed.

In addition, since the portion 26 in which the via contact 75 is to be formed is opened in the second metal layer 25 formed to prevent the light leakage current from flowing into the active matrix 10, light is emitted to the open portion. Incidentally, incident light cannot fundamentally prevent the light leakage current from flowing into the active matrix 10.

Accordingly, an object of the present invention is to provide a thin film type optical path control apparatus capable of changing the first metal layer pattern of the active matrix to reduce the metal contact resistance and reduce the light leakage current in the active matrix.

1 is a plan view of an active matrix of the thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is a cross-sectional view of the apparatus shown in FIG. 1 taken along line A′A ′.

FIG. 3 is a cross-sectional view of a thin film type optical path adjusting device taken along a line B′B ′ of FIG. 1.

4 is a plan view of an active matrix in the thin film type optical path control device according to the present invention.

5 is a cross-sectional view taken along line C′C ′ of the active matrix shown in FIG. 4.

6 is a cross-sectional view of a thin film type optical path adjusting device taken along a line D′ D ′ of FIG. 4.

7A to 7E are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 6.

Explanation of symbols for the main parts of the drawings

100: active matrix 105: drain

110: source 115: gate

120: device isolation layer 151: gate line

152 source line 153 drain pad

155: first metal layer 160: first protective layer

165: second metal layer 170: second protective layer

175: etch stop layer 180: sacrificial layer

185: support layer 190: lower electrode

195 strain layer 200 upper electrode

205 Actuator 210 Beer Hole

215: Beer contact 220: Stripe

225: air gap

In order to achieve the above object, the present invention provides a thin film type optical path control including an active matrix including M × N (M, N is an integer) MOS transistors and an actuator formed on top of the active matrix. Provide the device. The first metal layer is patterned larger than the pattern of the active region in which the source / drain is formed to block the source / drain depletion layer of the MOS transistor that may generate photo leakage current. The actuator may include: i) a support layer on one side of which is in contact with the top of the active matrix and the other side of the actuator being formed parallel to the active matrix via an air gap; ii) a bottom electrode formed on the top of the support layer; And a strained layer formed on the strained layer, and iii) an upper electrode formed on the strained layer.

In the above-described thin film type optical path control device according to the present invention, the first signal (image signal) transmitted from the outside is applied to the lower electrode through the transistor, the drain pad, and the via contact embedded in the active matrix. At the same time, a second signal (bias signal) is applied to the upper electrode to generate an electric field between the upper electrode and the lower electrode. By this electric field, the strained layer between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction orthogonal to the electric field, whereby the actuator is bent upward with a predetermined angle. The upper electrode, which also functions as a mirror that reflects light, is formed on the actuator and is inclined with the actuator. Accordingly, the upper electrode reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the thin film type optical path adjusting device according to the present invention, the first metal layer of the active matrix is patterned larger than the pattern of the active region in which the source / drain of the MOS transistor is formed. Accordingly, the first metal layer blocks the depletion layer of the source / drain which may generate a light leakage current, thereby reducing the amount of charge induced in the lower electrode through the drain pad by the light leakage current when the MOS transistor is turned off. Can be. Therefore, the turn-off operation of the MOS transistor can be improved to improve the contrast when driving the AMA module.

In addition, since the area of the first metal layer is increased as compared with the conventional thin film type optical path control device, the metal contact resistance can be reduced. Furthermore, since the via contact open region of the second metal layer formed to prevent the light leakage current from flowing into the active matrix is also blocked by the first metal layer, it is fundamental to prevent the light leakage current from flowing through the open region into the active region. You can stop it.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of an active matrix in the thin film type optical path control apparatus according to the present invention, FIG. 5 is a cross-sectional view taken along line CC ′ of the active matrix, and FIG. 6 is a line DD ′ of FIG. 4. The cross-sectional view of the thin film type optical path control device is shown.

4 to 6, the thin film type optical path control apparatus includes an active matrix 100 and an actuator 205 formed on the active matrix 100.

The active matrix 100 includes an isolation layer 120 for dividing the active matrix 100 into an active region and a field region, and a gate 115, a source 110, and a drain 105 in the active region. The formed M × N MOS transistors are included. In addition, the active matrix 100 is stacked on the MOS transistor and connected to the gate 115, the gate line 151 connected to the source 110, and the source line 152 and the drain 105 connected to the source 110. A first metal layer 155 including a drain pad 153 connected to the first metal layer, a first protective layer 160 stacked on the first metal layer, and a second metal layer 165 stacked on the first protective layer ), A second protective layer 170 stacked on the second metal layer, and an etch stop layer 175 stacked on the second protective layer. Here, the second metal layer 165 includes a first layer 165a stacked using titanium (Ti) and a second layer 165b stacked using titanium nitride (TiN).

The first metal layer 155 is patterned larger than the pattern of the active region (hatched portion of FIG. 4) in which the source / drain 110 and 105 of the MOS transistor are formed. Therefore, the first metal layer 155 blocks a region (see E of FIG. 5) in which the light may be incident to the depletion layer 118 of the source / drain 110 and 105 to generate a light leakage current. Accordingly, even though light is incident into the depletion layer 118 and the minority carriers generated by the light are introduced into the source / drain 110 and 105 by a drift electric field applied in the depletion layer 118, The minority carrier does not flow into the lower electrode 190 by the first metal layer 115. Therefore, even when the MOS transistor is turned off, the amount of charge induced in the lower electrode 190 through the drain pad 153 by the photo leakage current can be reduced, thereby improving the turn-off operation of the MOS transistor to drive the AMA module. The contrast can be improved. In addition, since the area s of the first metal layer is increased as compared with the conventional thin film type optical path control device, the metal contact resistance can be reduced.

In addition, the second metal layer 165 formed to prevent the light leakage current from flowing into the active matrix 100 has a portion 166 in which the via contact 215 is to be opened. Blocked by 155, it is possible to fundamentally prevent the light leakage current flowing through the open region 166 to the active region.

One side of the actuator 205 is in contact with a portion of the etch stop layer 175 in which the drain pad 145 is formed, and the other side thereof is formed in parallel with the lower portion of the active matrix 100 through the air gap 225. A support layer 185 having a cross section, a lower electrode 190 stacked on top of the support layer 185, a strain layer 195 stacked on top of the lower electrode 190, and an upper layer stacked on top of the strain layer 195. The electrode 200 and the strain layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second protective layer 170, and the first protective layer from one side of the strain layer 195. And a via contact 215 formed in the via hole 210 formed vertically through the 160 to the drain pad 145.

The support layer 185 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application. A stripe 220 is formed at one side of the upper electrode 200 to uniformly operate the upper electrode 200 to prevent diffuse reflection of incident light.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

7A to 7E are cross-sectional views for explaining the method for manufacturing the device shown in FIG. 6. 7A to 7E, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 7A, after preparing an active matrix 100 formed of an n-type doped silicon (Si) substrate, the active layer 100 may be prepared using a conventional device isolation process, for example, local oxidation of silicon (LOCOS). An isolation layer 120 is formed in the matrix 100 to separate the active region and the field region. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source 110 and drain 105 are formed by an ion implantation process. N (M, N are integer) PMOS transistors are formed.

After the insulating film 112 made of oxide is formed on the upper part of the resultant transistor formed thereon, openings exposing upper portions of one side of the gate 115, the source 110, and the drain 105 are formed by a photolithography process. . Subsequently, the first metal layer 155 made of a metal such as tungsten (W) is deposited on the resultant formed product, and then the first metal layer 155 is patterned by a photolithography process to thereby form the gate 115. A gate line 151 to be connected, a source line 152 connected to the source 110, and a drain pad 153 connected to the drain 105 are formed. In this case, the first metal layer 155 is patterned larger than the pattern of the active region in which the source / drain 110 and 105 are formed. The first signal (image signal) applied from the outside is transferred to the lower electrode 190 through the MOS transistor and the drain pad 153 embedded in the active matrix 100.

Referring to FIG. 7B, a first protective layer 160 is formed on the first metal layer 155 to protect the active matrix 100 in which the MOS transistor is embedded. The first passivation layer 160 is formed to have a thickness of about 8000 GPa by using a vapor deposition method (CVD) of phosphorus silicate glass (PSG). The first protective layer 160 prevents the transistor embedded in the active matrix 100 from being damaged during subsequent processes.

The second metal layer 165 is formed on the first passivation layer 160. In order to form the second metal layer 165, first, titanium (Ti) is sputtered to form the first layer 165a to a thickness of about 300 μm. Subsequently, titanium nitride (TiN) is deposited on the first layer 165a by using a physical vapor deposition (PVD) method to form a second layer 165b. Since the light incident from the light source is incident not only to the upper electrode 200, which is a reflective layer, but also to a portion other than the portion where the upper electrode 200 is formed, the second metal layer 165 may have a light leakage current in the active matrix 100. To prevent it from flowing. Subsequently, in the subsequent process of the second metal layer 165, the portion 166 on which the via contact 215 is to be formed is etched through a photolithography process.

Subsequently, a second protective layer 170 is formed on the second metal layer 165. The second protective layer 170 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 170 also prevents damage to the transistor embedded in the active matrix 100 during the subsequent process.

Subsequently, an etch stop layer 175 is formed on the second passivation layer 170. The etch stop layer 175 prevents the active matrix 100 and the second passivation layer 170 from being etched due to the subsequent etching process. The etch stop layer 175 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å. The etch stop layer 175 prevents the active matrix 100 and the second passivation layer from being etched due to the subsequent etching process.

Subsequently, a sacrificial layer 180 is formed on the etch stop layer 175. The sacrificial layer 180 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to 3.0 μm by the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 180 covers the top of the active matrix 100 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the surface of the sacrificial layer 180 is polished so that the sacrificial layer 180 has a thickness of about 1 μm by using spin on glass (SOG) or chemical mechanical polishing (CMP). By planarizing it. Subsequently, a portion of the sacrificial layer 180 under which the drain pad 145 is formed and a portion (not shown) where the gate line 151 is formed are etched to expose a portion of the etch stop layer 175, thereby providing an actuator ( A support 182 of 205 is formed.

Referring to FIG. 7C, a support layer 185 is formed on the exposed etch stop layer 175 and on the sacrificial layer 180. The support layer 185 is formed to have a thickness of about 0.1 to 1.0 μm using low pressure chemical vapor deposition (LPCVD).

Subsequently, a lower electrode 190 is formed on the support layer 185. The lower electrode 190 is formed to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). At the same time, by separating the lower electrode 190 for each pixel, an independent first signal is applied to each pixel (Iso-Cutting process). The first signal transferred from the transistor embedded in the active matrix 100 is applied to the lower electrode 190.

Subsequently, a strain layer 195 formed of PZT or PLZT is formed on the lower electrode 190. The strained layer 195 is formed to have a thickness of about 0.1 to 1.0 탆, preferably about 0.4 탆 using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the piezoelectric material constituting the strained layer 190 is subjected to heat treatment by rapid thermal annealing (RTA) to phase change and then polarize. The deformation layer 190 causes deformation by an electric field generated between the upper electrode 200 and the lower electrode 190.

Subsequently, an upper electrode 200 is formed on the deformation layer 190. The upper electrode 200 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). A second signal (bias signal) is applied to the upper electrode 200 through a common electrode line (not shown) from the outside. Since the upper electrode 200 has excellent electrical conductivity and reflectivity, the upper electrode 200 performs not only a function of a bias electrode generating an electric field but also a function of a mirror reflecting incident light.

Subsequently, the upper electrode 200, the deformation layer 195, and the lower electrode 190 are sequentially etched and patterned from the upper portion of the upper electrode 200 in a predetermined pixel shape. At this time, a stripe 220 is formed at the center of the upper electrode 200 to uniformly operate the upper electrode 200 to prevent diffuse reflection of light incident from the light source.

Referring to FIG. 7D, the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first protection from one side of the strained layer 195. The layers 160 are sequentially etched to form via holes 210. Therefore, the via hole 210 is formed from the other side of the strained layer 195 to the drain pad 145 of the first metal layer 155. Subsequently, a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 215. The via contact 215 electrically connects the drain pad 145 and the lower electrode 190 of the first metal layer 155. Therefore, the first signal applied from the outside is applied to the lower electrode 190 through the transistor, the drain pad 145, and the via contact 215 embedded in the active matrix 100. Subsequently, the support layer 185 is patterned into a predetermined pixel shape.

Referring to FIG. 7E, the sacrificial layer 180 is etched using hydrogen fluoride (HF) vapor to form an air gap 225, followed by a rinse and dry treatment to perform an AMA device. Complete

After completing the M × N thin film type AMA devices as described above, the active matrix 100 may be sputtered or evaporated on a metal such as chromium (Cr), nickel (Ni), or gold (Au). At the bottom of the to form an ohmic contact (not shown). In addition, a conventional photo is prepared in preparation for bonding a tape carrier package (TCP) (not shown) for applying a second signal to a subsequent upper electrode 200 and a first signal to a lower electrode 190. The active matrix 100 is cut to a predetermined thickness using a lithographic method. Subsequently, a photoresist layer (not shown) is formed over the pad of the AMA panel so that the pad of the AMA panel (not shown) has a sufficient height in preparation for TCP bonding. Subsequently, a portion of the photoresist layer on which the pad is formed is patterned to expose the pad of the AMA panel. Subsequently, the photoresist layer is etched using a dry etching method or a wet etching method, and the active matrix 100 is completely cut into a predetermined shape, and then the pads of the AMA panel and the TCP pads are ACF (Anisotropic Conductive Film). (Not shown) to complete the manufacture of the thin film AMA module.

In the above-described thin film type optical path control device according to the present invention, the first signal transmitted through the pad of the TCP and the pad of the AMA panel is a transistor, the drain pad 145 and the via contact 215 embedded in the active matrix 100. It is applied to the lower electrode 190 through. At the same time, a second signal is applied to the upper electrode 200 through the pad of the TCP, the pad of the AMA panel, and the common electrode line to generate an electric field between the upper electrode 200 and the lower electrode 190. Due to this electric field, the strain layer 195 between the upper electrode 200 and the lower electrode 190 causes deformation. The strained layer 195 is contracted in a direction orthogonal to the electric field, so that the actuator 205 is bent upward at a predetermined angle. The upper electrode 200, which also functions as a mirror that reflects light, is formed on the actuator 205 and is inclined together with the actuator 205. Accordingly, the upper electrode 200 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

As described above, according to the thin film type optical path adjusting device according to the present invention, the first metal layer of the active matrix is patterned larger than the pattern of the active region in which the source / drain of the MOS transistor is formed. Accordingly, the first metal layer blocks the depletion layer of the source / drain which may generate a light leakage current, thereby reducing the amount of charge induced in the lower electrode through the drain pad by the light leakage current when the MOS transistor is turned off. Can be. Therefore, the turn-off operation of the MOS transistor can be improved to improve the contrast when driving the AMA module.

In addition, since the area of the first metal layer is increased as compared with the conventional thin film type optical path control device, the metal contact resistance can be reduced. Furthermore, since the via contact open region of the second metal layer formed to prevent the light leakage current from flowing into the active matrix is also blocked by the first metal layer, it is fundamental to prevent the light leakage current from flowing through the open region into the active region. You can stop it.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

An active layer including an M × N (M, N is an integer) number of MOS transistors and a first metal layer 155 patterned larger than a pattern of an active region in which the sources / drains 110 and 105 of the MOS transistors are formed. Matrix 100; And i) a support layer 185 formed in parallel with the active matrix 100 via an air gap 225, the other side of which is in contact with an upper portion of the active matrix 100, and ii) an upper portion of the support layer 185. A lower electrode 190 formed therein, iii) an actuator 205 having a strained layer 195 formed on the lower electrode 190, and iii) an upper electrode 200 formed on the strained layer 195. Thin film type optical path control device comprising a. 2. The apparatus of claim 1, wherein the first metal layer (155) is patterned to block a source / drain depletion layer (118) of the MOS transistor that may generate a light leakage current. The method of claim 1, wherein the active matrix 100 includes a first passivation layer 160 formed on the first metal layer 155 and a second metal layer 165 formed on the first passivation layer 160. And a second protective layer (170) formed on the second metal layer (165) and an etch stop layer (175) formed on the second protective layer (170). 4. The apparatus of claim 3, wherein the first metal layer (155) is patterned to block the open area (166) of the second metal layer (165).