KR100270990B1 - Thin film actuated mirror array and method for manufacturing the same - Google Patents

Abstract

Disclosed are a thin film type optical path adjusting device capable of minimizing point defects of a pixel and a method of manufacturing the same. The apparatus includes a support layer having a shape of a square ring including a first anchor and a second anchor in contact with an etch stop layer, a lower electrode having the same shape as the support layer, a strained layer having a shape of a mirror-shaped 'c', and a deformation. An upper electrode having the same shape as the layer, an insulating layer for insulating the upper electrode and the lower electrode, and upper electrode connecting means for connecting adjacent upper electrodes. After forming the strained layer excluding the step of iso-cutting the lower electrode, an insulating layer is formed between the upper electrode connecting means and the lower electrode, thereby preventing the occurrence of an electrical short between the upper electrode and the lower electrode, thereby preventing The defect can be minimized.

Description

Thin film type optical path control device and its manufacturing method

The present invention relates to a thin film type optical path control apparatus using AMA (Actuated Mirror Array) and a method of manufacturing the same. More specifically, it is possible to minimize the point defects of pixels by preventing cracks of the deformation layer. It relates to a thin film type optical path control device and a method of manufacturing the same.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. The image processing apparatus using the optical path adjusting device or the spatial light modulator typically has a direct-view image display device and a projection-type image device according to a method of displaying optical energy on a screen. display device).

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Accordingly, reflective light modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, the structure and operation principle are simple, and high light efficiency (10% or more light efficiency) can be obtained compared with LCD and DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. Sikk bulk light path controllers are disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode therein into an active matrix in which a transistor is built, and then processing by using a sawing method and installing a mirror on the top. . However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Patent Application No. 96-59191 (name of the invention: thin film type optical path control device which can improve the light efficiency) which the applicant has filed a patent application on November 28, 1996 with the Korean Patent Office.

FIG. 1 shows a plan view of the thin film type optical path control device described in the preceding application, FIG. 2 shows a perspective view of the device of FIG. 1, and FIG. 3 shows a cross-sectional view taken along line AA ′ of the device of FIG. 2. will be.

1 to 3, the thin film type optical path adjusting device includes an active matrix 1, an actuator 65 formed on the active matrix 1, and a mirror 60.

The active matrix 1 in which M x N (M, N is an integer) embedded therein includes a drain pad 5, an active matrix 1, and a drain extending from a drain (not shown) of the MOS transistor. The protective layer 10 may be stacked on the pad 5, and the etch stop layer 15 may be stacked on the protective layer 10.

The actuator 65 may be anchors 31a and 31b that both sides of the lower side of one side contact the portion where the drain pad 5 is formed in the lower portion of the etch stop layer 15 and support the actuator 65. Membrane 30, the lower electrode 35 stacked on top of membrane 30, the deformable layer 40 stacked on top of lower electrode 35, and the other side formed horizontally through the air gap 25 The upper electrode 45 stacked on the layer 40, and the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer from one side of the strained layer 40 ( The via contact 55 may be formed to connect the lower electrode 35 and the drain pad 5 to the inside of the via hole 50 vertically through the drain pad 5.

Referring to FIG. 2, the membrane 30 has a rectangular flat plate integrated with the arms on the same plane between two rectangular arms formed in parallel from both side anchors 31a and 31b. It has a shape that is formed as. The mirror 60 is formed on the rectangular flat plate of the membrane 30. Thus, the mirror 60 has the shape of a rectangular flat plate.

Hereinafter, a method of manufacturing the above-described thin film type optical path control apparatus will be described with reference to the drawings.

4A to 4D show a manufacturing process diagram of the thin film type optical path control device. Referring to FIG. 4A, a protective layer 10 is stacked on top of an active matrix 1 in which M × N MOS transistors are embedded and a drain pad 5 extending from a drain of the MOS transistor is formed. The protective layer 10 is formed of phosphorus silicate glass (PSG) to have a thickness of about 1.0 to 2.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 prevents damage to the active matrix 1 in which the MOS transistor is embedded during the subsequent process.

An etch stop layer 15 is stacked on the passivation layer 10. The etch stop layer 15 is formed to have a thickness of about 0.1 to 0.2 탆 using low pressure chemical vapor deposition (LPCVD). The etch stop layer 15 prevents the active matrix 1 and the protective layer 10 in which the MOS transistor is embedded are etched due to a subsequent etching process.

The sacrificial layer 20 is stacked on the etch stop layer 15. The sacrificial layer 20 is formed of a silicate glass (PSG) to have a thickness of about 0.5 to 4.0 ㎛ by the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the top of the active matrix 1 in which the MOS transistors are embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 20 is planarized by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, the portions 31 where the drain pad 5 is formed below the sacrificial layer 20 and adjacent portions thereof are etched to expose a part of the etch stop layer 15 so as to support the actuator 65. 31b) is formed.

Referring to FIG. 4B, the membrane 30 is stacked on the exposed etch stop layer 15 and the sacrificial layer 20. The membrane 30 is formed to have a thickness of about 0.1 to 1.0 μm using a low pressure chemical vapor deposition (LPCVD) method. Subsequently, the lower electrode 35 is stacked on the membrane 30 using a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). The lower electrode 35 is formed to have a thickness of about 0.1 to 1.0 μm using a sputtering method, and then the lower electrode 35 is applied to apply an independent first signal (image signal) for each pixel. Iso-cutting. The first signal is applied to the lower electrode 35 from the outside through the MOS transistor and the drain pad 5 embedded in the active matrix 1.

The strained layer 40 is stacked on the lower electrode 35. The strained layer 40 is 0.1-1.0 μm, preferably 0.4 μm, for a piezoelectric material such as PZT or PLZT using a sol-gel method, sputtering method, or chemical vapor deposition (CVD) method. It is formed to have a thickness of. Subsequently, the piezoelectric material constituting the strained layer 40 is phase shifted by using a rapid heat treatment (RTA) method.

The upper electrode 45 is stacked on the deformation layer 40. The upper electrode 45 is formed of aluminum (Al), platinum (Pt), silver (Ag), or the like to have a thickness of about 0.1 to 1.0 μm using a sputtering method. The second signal (bias signal) is applied to the upper electrode 45 from the outside through a common electrode line (not shown). Therefore, when the first myth is applied to the lower electrode 35 and the second signal is applied to the upper electrode 45, an electric field is generated according to the potential difference between the upper electrode 45 and the lower electrode 35. According to the electric field, the deformation layer 40 formed between the upper electrode 45 and the lower electrode 35 causes deformation.

Referring to FIG. 4C, after the first photoresist (not shown) is coated and patterned on the upper electrode 45 by spin coating, the first photoresist is used as a mask. The electrode 45 is patterned to have a mirror-shaped 'c' shape. Subsequently, after the first photoresist is removed, a second photoresist layer (not shown) is applied and patterned on the patterned upper electrode 45 and the deformable layer 40 by spin coating. Using the second photoresist as a mask, the strained layer 40 is patterned to have a mirror-shaped 'c' shape slightly wider than the upper electrode 45. Subsequently, after removing the second photoresist, a third photoresist (not shown) is applied and patterned on top of the upper electrode 45, the deforming layer 40, and the lower electrode 35 by a spin coating method. Next, the lower electrode 35 is patterned to have a mirror-shaped 'c' shape slightly wider than the strained layer 40 using the third photoresist as a mask.

Subsequently, the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10 are formed from the portion of the strained layer 40 in which the drain pad 5 is formed below. After etching to form a via hole 50 from one side of the strained layer 40 to the drain pad 5, tungsten (W), platinum (Pt), aluminum (Al) inside the via hole 50 Alternatively, the via contact 55 is formed such that the drain pad 5 and the lower electrode 35 are connected to each other by sputtering a metal such as titanium (Ti). Accordingly, the first signal is applied from the outside to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. After this, the third photoresist is removed.

Referring to FIG. 4D, after the fourth photoresist (not shown) is coated and patterned on the lower electrode 35 and the via hole 50, the fourth photoresist is patterned as described above. Is used as a mask to pattern the membrane (30). In this case, the membrane 30 extends from the anchors 31a and 31b, which are both supporting portions, has a rectangular shape slightly wider than the lower electrode 35, and the central portion of the membrane 30 integrally formed therewith is a rectangular flat plate. Is patterned as: That is, as shown in FIG. 2, the membrane 30 has rectangular arms formed from the anchors 31a and 31b, which are both supporting portions, and a rectangular flat plate having a larger area than the arms is formed on the same plane. It has a shape formed integrally with the arms. Subsequently, the fourth photoresist is removed. As a result of the patterning of the membrane 30 as described above, a portion of the sacrificial layer 20 is exposed.

Subsequently, a fifth photoresist (not shown) is applied to the exposed sacrificial layer 20 and the upper portion of the membrane 30 by spin coating, and then the fifth photoresist is patterned to form the membrane 30. To expose the square plate, the center of Subsequently, a metal such as silver (Ag), platinum (Pt), or aluminum (Al) is sputtered to a thickness of about 0.3 to 2.0 μm on the upper portion of the membrane 30 exposed in the rectangular shape, and then the sputtered metal It is patterned to have the same shape as the shape of the rectangular membrane of the exposed membrane 30 to form a mirror (60). Subsequently, the fifth photoresist and the sacrificial layer 20 are removed using hydrogen fluoride (HF) vapor, followed by a rinse and dry process to form M × N AMA devices. .

However, in the above-described thin film type optical path control device, the sacrificial layer is formed to form the iso-cutting portion of the lower electrode and the anchors that are the supporting portions of the actuator by iso-cutting a portion of the lower electrode and forming a strained layer thereon. Cracks occur in the strained layer on the patterned portion, and the cracks have a problem in that the upper electrode is partially connected to the lower electrode, thereby causing an electrical short between the upper electrode and the lower electrode. When an electrical short occurs between the upper electrode and the lower electrode, the corresponding actuator is not driven, resulting in a point defect of the pixel.

Accordingly, an object of the present invention is to provide a thin film type optical path control apparatus capable of minimizing point defects of a pixel by blocking cracks in the strained layer and preventing electrical short between the upper electrode and the lower electrode.

In addition, another object of the present invention is to provide a method of manufacturing a thin film type optical path control device that can minimize the point defects of the pixel by blocking the crack of the strain layer and prevent electrical short between the upper electrode and the lower electrode.

1 is a plan view of a thin film type optical path adjusting device described in the above prior application.

FIG. 2 is a perspective view of the apparatus shown in FIG. 1. FIG.

3 is a cross-sectional view of the apparatus shown in FIG. 2 taken along line A-A '.

4A to 4D are manufacturing process diagrams of the apparatus shown in FIG. 3.

5 is a plan view of a thin film type optical path control apparatus according to the present invention.

6 is a perspective view of the apparatus shown in FIG. 5.

FIG. 7 is a cross-sectional view taken along line B-B 'of the apparatus shown in FIG.

8 is a cross-sectional view taken along line C-C 'of the apparatus shown in FIG.

9A to 9E are manufacturing process diagrams of the apparatus shown in FIG.

<Description of the code | symbol about the principal part of drawing>

100: active matrix 101: device isolation film

102 gate 103 source

104: drain 105: MOS transistor

106: insulating film 107: first metal layer

110: first protective layer 111: second metal layer

113: second protective layer 114: etching prevention layer

120: first air gap 125: support layer

126: first anchor 127: second anchor

130: lower electrode 135: strained layer

140: upper electrode 145: actuator

150a, 150b: insulation layer 156: via contact

160a, 160b: upper electrode connecting means 165: second air gap

170: Post 200: Mirror

In order to achieve the above object of the present invention, the present invention provides an active matrix having a first metal layer having a MOS transistor embedded therein and having a drain pad extending from the drain of the transistor. Provided is a thin film type optical path control apparatus including an actuator having an electrode, a deformation layer, an upper electrode, an insulating layer, and an upper electrode connecting means, and a mirror formed on the actuator. The support layer may have a rectangular ring having one side contacting a portion where the drain pad is formed below the active matrix and both sides of the same straight line to be the first anchor and the second anchor, and the other side being formed horizontally on the active matrix. Has the shape of. The lower electrode has the same shape as the support layer but has a smaller area than the support layer. The strained layer has a mirror-shaped 'c' shape, and the upper electrode has the same shape as the strained layer but has a smaller area than the strained layer. The insulating layer is formed from one side of the upper electrode to an upper electrode of an adjacent actuator past the upper part of the lower electrode on the second anchors, and the upper electrode connecting means is adjacent from the part of the upper electrode past the upper part of the insulating layer. It is connected to the upper electrode of the actuator. A via contact is formed from a portion of the lower electrode formed on the first anchor to the drain pad to connect the lower electrode and the drain pad.

In order to achieve the above object of the present invention, the present invention provides an active matrix including a first metal layer having a drain pad in which a MOS transistor is embedded and extending from the drain of the transistor. A first sacrificial layer is formed, and the first sacrificial layer is patterned to expose portions of the active matrix in which the drain pads of the first metal layer are formed and both sides of the portions in which the drain pads are formed. A first layer, a lower electrode layer, a second layer, and an upper electrode are formed on the sacrificial layer, and the upper electrode layer, the second layer, the lower electrode layer, and the first layer are patterned to form an upper electrode, a strain layer, and a lower electrode. And a support layer having a first anchor and a second anchor, the actuator being adjacent from one side of the upper electrode. Forming an insulating layer to one side of the upper electrode of the upper electrode; forming upper electrode connecting means from a portion of the upper electrode to a portion of the upper electrode of an adjacent actuator; and the lower electrode and the first anchor positioned on the portion where the drain pad is formed. To form a via hole from the lower electrode to the drain pad, to form a via contact in the via hole, and to form and pattern a second sacrificial layer on top of the actuator to form a mirror on the top of the actuator. It provides a method for manufacturing a thin film type optical path control device comprising the step of forming.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal transmitted from the outside is applied to the lower electrode through the MOS transistor embedded in the active matrix, the drain pad of the first metal layer and the via contact. At the same time, the second signal transmitted from the outside is applied to the upper electrode through the upper electrode connecting means to generate an electric field according to the potential difference between the upper electrode and the lower electrode. Due to this electric field, the strain layer formed between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction orthogonal to the electric field, thereby causing the actuator to bend at a predetermined angle. The mirror is formed on top of the actuator so that it is tilted at the same angle as the actuator. Therefore, the mirror reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit and is projected onto the screen to form an image.

According to the present invention, a support layer having a shape of a square ring including a first anchor and a second anchor each contacting the etch stop layer, a lower electrode having the same shape as the support layer, a strained layer having a shape of 'c' on the mirror, An upper electrode having the same shape as the strained layer, an insulating layer for insulating the upper electrode and the lower electrode, and upper electrode connecting means for connecting adjacent upper electrodes are formed. Therefore, after forming the strained layer without iso-cutting the lower electrode, an insulating layer is formed between the upper electrode connecting means and the lower electrode, thereby preventing the electrical short between the upper electrode and the lower electrode to prevent the point of the pixel. The defect can be minimized.

Hereinafter, a thin film type optical path adjusting apparatus according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a plan view of a thin film type optical path control device according to the present invention, Figure 6 is a perspective view of the device shown in Figure 5, Figure 7 is a cross-sectional view taken along the line BB 'of the device shown in FIG. 8 is a cross-sectional view taken along line CC ′ of the apparatus shown in FIG. 6.

5 to 8, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 100, an actuator 145 formed on the active matrix 100, and a mirror formed on the actuator 145. 200).

The active matrix 100 is formed with an isolation layer 101 for dividing the active matrix 100 into an active region and a field region, and a gate 102, a source 103, and a drain 104 in the active region. M × N (M and N are natural numbers) P-MOS transistors 105 are included. In addition, the active matrix 100 may be stacked on top of the P-MOS transistor 105 and patterned to be connected to the source 103 and the drain 104, respectively, of the first metal layer 107 and the first metal layer 107. The first protective layer 110 stacked on the top, the second metal layer 111 stacked on the first protective layer 110, the second protective layer 113 stacked on the second metal layer 111, And an etch stop layer 114 stacked on the second passivation layer 113. The first metal layer 107 includes a drain pad and a source line (not shown) extending from the drain 104 of the P-MOS transistor 105 to transmit the first signal, and the second metal layer 111 It consists of a titanium (Ti) layer and a titanium nitride (TiN) layer.

The actuator 145 may include a support layer 125 including a first anchor 126 and second anchors 127a and 127b, a lower electrode 130, a strained layer 135, an upper electrode 140, and And a via contact 156. The first anchor 126 is in contact with a portion of the anti-etching layer 114 at which the drain pad 108 of the first metal layer 107 is formed, and the second anchors 127a and 127b respectively contact the anti-etching layer 114. It is in contact with both sides adjacent to the first anchor 126 of the first anchor 126 is formed on the same straight line. The support layer 125 has a rectangular ring shape, one side of which is supported by the first anchor 126 and the second anchors 127a and 127b, and the other side is horizontally formed on the etch stop layer 114. The lower electrode 130 has the same shape as the support layer 125, but is formed on the support layer 125 with a narrower area than the support layer 125. That is, the lower electrode 130 also has the shape of a square ring. The deformation layer 135 is not formed at a portion where the first anchor 126 and the second anchors 127a and 127b, which are one side of the support layer 125, are positioned, and the lower electrode 130 on the other side of the support layer 125. It is formed on the top of the mirror-shaped 'c' shape. The upper electrode 140 has the same shape as the strained layer 135 but has a smaller area than the strained layer 135 and is formed on the strained layer 135. The via contact 156 may include a first anchor (not shown) in a portion in which the hole 112 of the second metal layer 111 and the drain pad 108 of the first metal layer 107 are formed below the lower electrode 130. 126, through the etch stop layer 114, the second passivation layer 113, and the first passivation layer 110, to the drain pad 108 of the first metal layer 107. The lower electrode 130 and the drain pad 108 of the first metal layer 107 are formed to be connected to each other.

Referring to FIG. 6, insulating layers 150a and 150b are formed from one side of the deformable layer 135 to one side of the deformed layers of neighboring actuators through the tops of the second anchors 127a and 127b, respectively. Upper electrode connecting means 160a and 160b are formed on the insulating layers 150a and 150b to connect the upper electrode of the adjacent actuator and the upper electrode 140 of the actuator 145. The insulating layers 150a and 150b have upper electrode connecting means 160a and 160b connected to the lower electrode 130 under the insulating layers 150a and 150b to electrically connect the upper electrode 140 and the lower electrode 130. Prevent shorts from occurring Accordingly, the upper electrode 140 may be connected to the upper electrodes of adjacent actuators through the upper electrode connecting means 160a and 160b so that a second signal (bias signal) applied from the outside may be transmitted to the upper electrodes of the respective actuators. have.

A first signal (image signal) is applied to the lower electrode 130 through the MOS transistor and the via contact 156 embedded in the active matrix 100 from the outside. At the same time, when the second signal (bias signal) is applied to the upper electrode 140 from the outside through the upper electrode connecting means 160a and 160b, an electric field is generated between the upper electrode 140 and the lower electrode 130. As a result, the deformation layer 135 causes deformation.

The mirror 200 has a shape of a rectangular flat plate whose lower portion is supported by a post 170 formed at a central portion of one side of the upper electrode 140 and both sides thereof are horizontally formed.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

9A to 9E are views for explaining a method of manufacturing the apparatus shown in FIG. 9A to 9E, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 9A, an active matrix 100, which is a wafer made of silicon doped with n-type, is prepared, and then active on the active matrix 100 using a silicon partial oxidation method (LOCOS), which is a conventional device isolation process. An isolation layer 101 is formed to distinguish between an active region and a field region. Subsequently, a gate 102 made of a conductive material such as poly silicon doped with impurities is formed on the active region, and then p ⁺ source 103 and drain 104 are formed using an ion implantation process. By forming the P-MOS transistors 105 in the active matrix 100, M x N (M and N are natural numbers) are formed.

After the insulating film 106 made of oxide is formed on the P-MOS transistor 105, the openings exposing the upper portions of the one side of the source 103 and the drain 104, respectively, using a photolithography method. Form them. Subsequently, a first metal layer 107 made of titanium (Ti), titanium nitride (TiN), tungsten (W), nitride, or the like is deposited on the resultant, and then the first metal layer 107 is photo-etched. Pattern with. The patterned first metal layer 107 includes a drain pad 108 extending from the drain 104 of the P-MOS transistor 105 to the bottom of the first anchor 126 supporting the support layer 125. do.

The first passivation layer 110 is formed on the first metal layer 107 and the active matrix 100. The first passivation layer 110 is formed to have a thickness of about 0.8 μm using the silicate glass (PSG) method by chemical vapor deposition (CVD). The first protective layer 110 prevents damage to the active matrix 100 in which the P-MOS transistor 105 is embedded due to a subsequent process.

The second metal layer 111 is formed on the first protective layer 110. The second metal layer 111 forms a titanium layer having a thickness of about 300 kW using a sputtering method of titanium, and then, about 1200 kW of titanium nitride using a physical vapor deposition (PVD) method on the titanium layer. It is completed by forming a titanium nitride layer having a thickness. Since the light incident from the light source is incident not only to the mirror 200 but also to a portion other than the portion covered by the mirror 200, photocurrent flows through the active matrix 100 so that the device malfunctions. To prevent it. Subsequently, a portion of the second metal layer 111 in which the via hole 155 is to be formed in a subsequent process, that is, a portion in which the drain pad of the first metal layer 107 is formed is etched, as shown in FIG. 8. Likewise, holes 112 are formed in the second metal layer 111.

The second protective layer 113 is stacked on the second metal layer 111. The second passivation layer 113 is formed to have a thickness of about 0.2 μm using the silicate glass PSG using a chemical vapor deposition method. The second protective layer 113 prevents damage to the active matrix 100 and the results formed on the active matrix 100 during subsequent processing.

An etch stop layer 114 is stacked on the second passivation layer 113. The etch stop layer 114 prevents the second passivation layer 113 and the results on the active matrix 100 from being etched due to a subsequent etching process. The etch stop layer 114 is formed of a low temperature oxide (LTO) such as silicon oxide (SiO ₂ ) or phosphorus pentoxide (P ₂ O ₅ ). The etch stop layer 114 is formed to have a thickness of about 0.2 to 0.8 μm at a temperature of about 350 to 450 ° C. using a low pressure chemical vapor deposition (LPCVD) method.

The first sacrificial layer 119 is stacked on the etch stop layer 114. The first sacrificial layer 119 serves to facilitate stacking of the thin films constituting the actuator 145. The first sacrificial layer 119 is formed to have a thickness of about 2.0 to 3.0 μm by using a low pressure chemical vapor deposition (LPCVD) method at a temperature of about 500 ° C. or less. Subsequently, the surface of the first sacrificial layer 119 is polished using a chemical mechanical polishing (CMP) method to planarize the surface of the first sacrificial layer 119 to have a thickness of about 1.1 μm.

Subsequently, after applying and patterning a first photoresist (not shown) on the first sacrificial layer 119, a second photoresist is disposed below the first sacrificial layer 119 using the first photoresist as a mask. The first anchor 126 supporting the support layer 125 formed later by etching a portion where the hole 112 of the metal layer 111 is formed and both adjacent portions thereof to expose a portion of the etch stop layer 114 in a rectangular shape. ) And the position where the second anchors 127a and 127b are to be formed. Thus, the etch stop layer 114 is exposed in the shape of three squares spaced apart by a predetermined distance. Subsequently, the first photoresist is removed.

Referring to FIG. 9B, the first layer 124 is stacked on the upper portion of the etch stop layer 114 and the first sacrificial layer 119 exposed in the shape of a quadrangle as described above. The first layer 124 is formed to have a thickness of about 0.1 to 1.0 μm using a low pressure chemical vapor deposition (LPCVD) method, such as a nitride material. The first layer 124 is later patterned with a support layer 125, wherein the support layer 125 comprising the first anchor 126 and the second anchors 127a, 127b is in the shape of a rectangular ring, preferably, It has a rectangular ring shape and supports the actuator 145. In this case, a portion of the first layer 124 attached to the etch stop layer 114 among the portions attached to the etch stop layer 114 exposed in the shape of the three rectangles is the first anchor 126. The portions attached to both sides of the quadrangular etch stop layer 114 become second anchors 127a and 127b.

The lower electrode layer 129 is stacked on top of the first layer 124. The lower electrode layer 129 has a thickness of about 0.1 to 1.0 μm using a sputtering method or a chemical vapor deposition method on an electrically conductive metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). Form to have. The lower electrode layer 129 is later patterned with a lower electrode 130 having a first signal applied from the outside and having a rectangular ring shape, preferably, a rectangular ring shape.

A second layer 134 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode layer 129. The second layer 134 is formed to have a thickness of about 0.1 to 1.0 μm using a sol-gel method, a sputtering method, or a chemical vapor deposition method. Preferably, the second layer 134 is formed to have a thickness of about 0.4 μm by sputtering PZT prepared by the sol-gel method. Subsequently, the piezoelectric material constituting the second layer 134 is subjected to heat treatment by a rapid heat treatment (RTA) method to perform phase change. The second layer 134 is later deformed by an electric field generated between the upper electrode 140 and the lower electrode 130 and patterned into a strained layer 135 having a mirror-shaped 'c' shape.

The upper electrode layer 139 is stacked on top of the second layer 134. The upper electrode layer 139 is formed of a metal having electrical conductivity such as platinum, tantalum, silver (Ag), or platinum-tantalum to have a thickness of about 0.1 to 1.0 μm using a sputtering method or a chemical vapor deposition method. The upper electrode layer 139 is later applied with a second signal and patterned into the upper electrode 140 having a mirror-shaped 'c' shape.

Referring to FIG. 9C, after applying and patterning a second photoresist (not shown) on the upper electrode layer 139, using the second photoresist as a mask, the upper electrode layer 139 is formed in a mirror image ' Patterned into the upper electrode 140 having a '' shape (see FIG. 6). Therefore, the upper electrode 140 is not formed on the portion where the first layer 124 contacts the etch stop layer 114. The second signal is applied to the upper electrode 140 through the upper electrode connecting means 160a and 160b formed later from the outside. Then, the second photoresist is removed.

Subsequently, in the same manner as the method of patterning the upper electrode layer 139 to the upper electrode 140, as shown in FIG. 6, the second layer 134 is patterned to have the same shape as the upper electrode 140. However, the strained layer 135 having a shape of a 'c' in a mirror area having a larger area than the upper electrode 140 is formed. Subsequently, after applying and patterning a third photoresist (not shown) on the lower electrode layer 129, the lower electrode layer 129 is formed in a rectangular ring shape, preferably using the third photoresist as a mask. The lower electrode 130 is patterned to have a rectangular ring shape. The lower electrode 130 has a larger area than the deformation layer 135 and is patterned to be separated from the lower electrode of the adjacent actuator. In this case, unlike the shapes of the strained layer 135 and the upper electrode 140, the lower electrode 130 is also formed on an upper portion of the portion where the first layer 124 contacts the etch stop layer 114.

Subsequently, the first layer 124 is patterned to form the support layer 125 including the first anchor 126 and the second anchors 127a and 127b. In this case, both sides of the portion of the first layer 124 contacting the etch stop layer 114 exposed in the shape of the three quadrangles are second anchors 127a and 127b, and the center portion of the first layer 124 is the first anchor 126. ) That is, the first anchor 126 is formed inside the actuator 145, and the second anchors 127a and 127b are formed on both outer sides of the actuator 145. Each of the first anchor 126 and the second anchors 127a and 127b has a rectangular box shape, and a hole 112 of the second metal layer 111 is formed under the first anchor 126 ( 8). The support layer 125 is patterned to have the shape of a rectangular ring, preferably a rectangular ring. In this state, when the first sacrificial layer 119 is removed later, a supporting layer 125 having a shape as shown in FIG. 6 is formed. Accordingly, the actuator 145 including the upper electrode 140, the strain layer 135, the lower electrode 130, and the support layer 125 is completed.

Referring to FIG. 9D, a third photoresist (not shown) is applied and patterned on the support layer 125 and the actuator 145 to form an upper portion of the first anchor 126 and the second anchors 127a and 127b. A portion of the lower electrode 130 and the upper electrode 140 formed at the portion are exposed. Subsequently, by depositing and patterning a low temperature oxide such as amorphous silicon or silicon oxide (SiO ₂ ) or phosphorus pentoxide (P ₂ O ₅ ) on the exposed lower electrode 130 and the upper electrode 140, Each of the insulating layers 150a and 150b is formed from a portion of the upper electrode 140 to a portion of the upper electrode of the adjacent actuator past the upper portion of the lower electrode 130 on the second anchors 127a and 127b. The insulating layers 150a and 150b are formed to have a thickness of about 0.2 to 0.4 µm using a low pressure chemical vapor deposition (LPCVD) method. The insulating layers 150a and 150b prevent the electrical short between the upper electrode 140 and the lower electrode 130 by connecting the upper electrode connecting means 160a and 160b formed later to the lower electrode 130. .

Subsequently, the first anchor 126, the etch stop layer 114, the second passivation layer 113, and the first protection from a portion of the lower electrode 130 where the hole 112 of the second metal layer 111 is formed below. After the layer 110 is etched to form the via hole 155 to the drain pad 108 of the first metal layer 107, the via contact 156 is formed in the via hole 155. Accordingly, the lower electrode 130 is connected to the drain pad 108 of the first metal layer 107 through the via contact 156. At the same time, as shown in FIG. 8, the upper electrode connecting means 160a, 160b is formed from a part of the upper electrode 140 to the upper electrode of the adjacent actuator past the top of the insulating layers 150a, 150b. The upper electrode 140 of the actuator adjacent to the upper electrode 140 of the actuator 145 is connected to each other through the upper electrode connecting means 160a and 160b. The via contact 156 and the upper electrode connecting means 160a and 160b are formed by depositing platinum or platinum-tantalum to have a thickness of about 0.1 μm to about 1.0 μm using a sputtering method or a chemical vapor deposition method.

Referring to FIG. 9E, a second sacrificial layer having a height sufficient to completely cover the actuator 145 by depositing polycrystalline silicon on the actuator 145 and the support layer 125 by low pressure chemical vapor deposition (LPCVD). 164). Subsequently, the surface of the second sacrificial layer 164 is planarized by using a chemical mechanical polishing (CMP) method so that the top of the second sacrificial layer 164 has a flat surface. Subsequently, the second sacrificial layer 164 is patterned to form the mirror 200 and the post 170, thereby exposing a portion of the upper electrode 140 at a position opposite the via contact 156. Next, a metal, such as aluminum (Al) having excellent reflectivity, is deposited on a portion of the exposed upper electrode 140 and on the second sacrificial layer 164 by using a sputtering method or a chemical vapor deposition method and then deposited. The metal is patterned to simultaneously form a mirror 200 having a rectangular flat plate shape and a post 170 supporting the mirror 200.

Then, the first sacrificial layer 119 and the second sacrificial layer 164 are simultaneously removed using xenon fluoride (XeF ₂ ) or bromine fluoride (BrF ₂ ), and a rinse and dry treatment is performed. Is performed to complete the AMA device as shown in FIG. As described above, when the second sacrificial layer 164 is removed, the second air gap 165 is formed at the position of the second sacrificial layer 164, and when the first sacrificial layer 119 is removed, the first sacrificial layer 119 is removed. The first air gap 120 is formed at the position of.

In the above-described thin film type optical path control device according to the present invention, the first signal transmitted from the outside is the MOS transistor 105 embedded in the active matrix 100, the drain pad 108 and the via contact of the first metal layer 107. It is applied to the lower electrode 130 through the (156). At the same time, as the second signal is applied to the upper electrode 140 through the upper electrode connecting means 160a and 160b from the outside, an electric field is generated according to a potential difference between the upper electrode 140 and the lower electrode 130. . Due to this electric field, the deformation layer 135 formed between the upper electrode 140 and the lower electrode 130 causes deformation. As the strained layer 135 contracts in a direction perpendicular to the electric field, the actuator 145 including the strained layer 135 is bent at a predetermined angle, and the support layer 125 is also bent at a predetermined angle. The mirror 200 reflecting the light incident from the light source is inclined together with the upper electrode 140 because the mirror 200 is supported by the post 170 and formed on the actuator 145. Accordingly, the mirror 200 reflects incident light at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the thin film type optical path control apparatus and a manufacturing method thereof according to the present invention, a support layer having a shape of a square ring including a first anchor and a second anchor in contact with the etch stop layer, a lower electrode having the same shape as the support layer, and a mirror image A strained layer having a 'c' shape, an upper electrode having the same shape as the strained layer, an insulating layer for insulating the upper electrode and the lower electrode, and upper electrode connecting means for connecting adjacent upper electrodes are formed. Therefore, after forming the strained layer without iso-cutting the lower electrode, an insulating layer is formed between the upper electrode connecting means and the lower electrode, thereby preventing the electrical short between the upper electrode and the lower electrode to prevent the point of the pixel. The defect can be minimized.

Although described above with reference to the preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (8)

An active matrix (100) containing a first metal layer (107) with a MOS transistor (105) embedded therein and having a drain pad (108) extending from the drain (104) of the transistor (105); Iii) one side of the active matrix 100 is in contact with a portion where the drain pad 108 is formed below and both sides of the same straight line to form the first anchor 126 and the second anchors 127a and 127b, A support layer 125 formed on the other side horizontally on the active matrix 100, ii) a lower electrode 130 formed on the support layer 125, and a strained layer formed on the lower electrode 130 135), iv) an upper electrode 140 formed on the deformable layer 135, and iii) an adjacent actuator passing from the one side of the upper electrode 140 through the top of the second anchors 127a and 127b. An actuator 145 including upper electrode connecting means 160a and 160b formed up to an upper electrode; A via contact 156 formed from the lower electrode 130 to the drain pad 108 through a first anchor 126; And Thin film type optical path control device, characterized in that it comprises a mirror (200) formed on top of the actuator (145). The method of claim 1, wherein the support layer 125 has a shape of a square ring, the lower electrode 130 has a shape of a square ring of a smaller area than the support layer 125, the deformation layer 135 is a mirror image It has a 'c' shape, the upper electrode 140 is a thin film type optical path control device, characterized in that it has a mirror-shaped 'c' shape of a narrower area than the deformation layer 135. The method of claim 1, wherein the insulating layer (150a, 150b) is formed between the upper electrode connecting means (160a, 160b) and the lower electrode 130 above the second anchors (127a, 127b). Thin film type optical path control device. The method of claim 3, wherein the upper electrode connecting means (160a, 160b) is made of platinum (Pt) or platinum-tantalum (Pt-Ta), the insulating layer (150a, 150b) is amorphous silicon (amorphous silicon) or Thin film type optical path control device, characterized in that made of low temperature oxide (low temperature oxide). Providing an active matrix including a first metal layer having a MOS transistor embedded therein and having a drain pad extending from the drain of the transistor; Forming a first sacrificial layer on the active matrix, and then patterning the first sacrificial layer to expose portions of the active matrix in which the drain pads of the first metal layer are formed and both sides of the portions in which the drain pads are formed; ; Forming a first layer, a lower electrode layer, a second layer, and an upper electrode on the active matrix and the first sacrificial layer; Patterning the upper electrode layer, the second layer, the lower electrode layer, and the first layer to form a support layer having an upper electrode, a strain layer, a lower electrode, and first and second anchors; Forming an insulating layer from one side of the upper electrode to one side of the upper electrode of an adjacent actuator; Forming upper electrode connecting means from a portion of the upper electrode to a portion of the upper electrode of an adjacent actuator; Etching the lower electrode and the first anchor on the portion where the drain pad is formed to form a via hole from the lower electrode to the drain pad, and then forming a via contact in the via hole; And And forming and patterning a second sacrificial layer on top of the actuator, and forming a mirror on top of the actuator. The method of claim 5, wherein the forming of the insulating layer is performed using a low pressure chemical vapor deposition method. The method of claim 5, wherein the forming of the upper electrode connecting means is performed by using a sputtering method or a chemical vapor deposition method. The method of claim 5, wherein the forming of the upper electrode connecting means and the forming of the via contact are performed at the same time.