KR20000044204A - Manufacturing method for thin film micromirror array-actuated device - Google Patents

Abstract

PURPOSE: A manufacturing method of the TMA device is provided to improve the quality of the image projected to the screen by improving the optical energy utilization and to improve the horizontal characteristic of a mirror. CONSTITUTION: A device comprises an active matrix(100), a substrate(101), a first metal layer(135), a first protection layer(140), a second metal layer(145), a second protection layer(150), an etching preventing layer(155), a first sacrificial layer(160), and a supporting layer(170). A manufacturing method comprises a step of providing the active matrix including the first metal layer which has the drain pad extended from the drain of the transistor; a step of forming the actuator including the first and second upper electrode, first and second electrodisplacives and the lower electrode by patterning the lower part electrode layer, the second layer and the upper part electrode layer sequentially; a step of forming a supporting instrument including the second anchor, first anchor, supporting layer, and a supporting line; a step of forming a post hole by patterning and depositing the sacrificial layer; and a step of forming a post by evening the oxide silicon layer.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using thin-film micromirror array-actuated (TMA). More particularly, the thin film type can improve the image quality of an image projected on a screen by forming a horizontal mirror. It relates to a method for manufacturing an optical path control device.

Optical path control devices or spatial light modulators for projecting optical energy onto the screen can be applied to various fields such as optical communication, image processing and information display devices. Typically, image processing apparatuses using such an optical modulator are classified into a direct view type image display device and a projection type image display device according to a method of displaying optical energy on a screen.

An example of a direct view type imaging device is a CRT (Cathode Ray Tube), which is a so-called CRT device, which has excellent image quality but increases in weight and volume as the size of the screen increases, leading to an increase in manufacturing cost. have. Projection type image display devices include liquid crystal display (LCD), deformable mirror device (DMD) and AMA. Such projection image display apparatuses can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmission light modulators, while DMD and AMA can be classified as reflective light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, the light efficiency is low due to the polarity of the light, there is a problem inherent in the liquid crystal material, for example, the response speed is slow and its inside is easy to overheat. In addition, the maximum light efficiency of existing transmission optical modulators is limited to a range of 1-2% and requires dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein into an active matrix in which transistors are built, and then processing it using a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control device (TMA) that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 97-28914 (name of the invention: a method of manufacturing a thin film type optical path control device) filed by the applicant of the Korean Patent Office on June 30, 1997.

The manufacturing method of the thin film type optical path control apparatus described in the preceding application is as follows.

1 is a cross-sectional view of a thin film type optical path control device disclosed in the preceding application, Figures 2a to 2c are views for explaining the manufacturing method of the device shown in FIG.

Referring to FIG. 2A, a device isolation layer 6 is formed on a substrate 1, which is an n-type doped silicon wafer, by using a silicon partial oxidation (LOCOS) method to distinguish between an active region and a field region. Subsequently, a gate 4 made of polysilicon is formed on the active region, and then p ⁺ source 3 and drain 2 are formed by an ion implantation process, thereby forming M x N (M) on the substrate 1. , N is a natural number) to form P-MOS transistors.

After the insulating film 7 made of oxide is formed on the P-MOS transistor, the openings are formed to expose the upper portions of one side of the source 3 and the drain 2 by photolithography. Subsequently, a first metal layer 8 made of a metal such as tungsten is deposited on the resultant product on which the openings are formed, and then the first metal layer 8 is patterned. The patterned first metal layer 8 comprises a drain pad to which the actuator will be connected in a subsequent process.

A first protective layer 9 is formed on top of the first metal layer 8 to prevent damage to the substrate 1 in which the P-MOS transistor is embedded during subsequent processing. The first protective layer 9 is deposited with a thickness of 8000 kPa of silicate glass (PSG) by chemical vapor deposition (CVD). The second metal layer 10 is formed on the first protective layer 9. The second metal layer 10 is formed by sputtering titanium to form a first layer 10a having a thickness of 300 kPa, and then layering titanium nitride on the first layer 10a by physical vapor deposition (PVD). The second layer 10b is formed and completed. The second metal layer 10 also enters a portion other than the portion covered by the upper electrode 30 so that photocurrent flows through the active matrix 16 to prevent the device from malfunctioning. Subsequently, a portion of the second metal layer 10 to be formed later, the via contact 39 is etched through a photolithography process.

The second passivation layer 12 made of insulated glass PSG is stacked on the second metal layer 10. The second protective layer 12 is formed to have a thickness of about 2000 kPa by chemical vapor deposition. On top of the second passivation layer 12, an etch stop layer 13 is deposited to prevent the second passivation layer 12 and the products on the substrate 1 from being etched during the subsequent etching process. The etch stop layer 13 is formed by depositing nitride (Si ₃ N ₄ ) to a thickness of about 1000 to 2000 kPa by low pressure chemical vapor deposition (LPCVD).

The first sacrificial layer 14 is stacked on the etch stop layer 13. The first sacrificial layer 14 is formed by depositing silicate glass (PSG) to a thickness of 2.0 to 3.0 μm by an atmospheric pressure chemical vapor deposition (APCVD) method, and then chemical mechanical polishing the surface of the first sacrificial layer 14. Polishing is carried out by the (CMP) method to flatten the surface. Subsequently, a portion of the first sacrificial layer 14 having a drain pad formed thereon is etched to expose a portion of the etch stop layer 13, thereby forming a support portion of the actuator.

A third layer 17 is stacked on the exposed etch stop layer 13 and on the first sacrificial layer 14. The third layer 17 is formed by depositing nitride to a thickness of 0.1 to 1.0 mu m by low pressure chemical vapor deposition (LPCVD). The lower electrode layer 23 is stacked on top of the third layer 17. The lower electrode layer 23 is deposited to have a thickness of 0.1 to 1.0 μm using a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) by sputtering or chemical vapor deposition. Subsequently, the lower electrode layer is subjected to an iso-cutting process and separated for each pixel so that an independent first signal is applied to each pixel.

A fourth layer 25 made of a piezoelectric material is stacked on the lower electrode layer 23. The fourth layer 25 is formed by spin coating PZT prepared by the sol-gel method to have a thickness of 0.4 μm. Subsequently, the piezoelectric material constituting the fourth layer 25 is subjected to heat treatment by rapid thermal treatment (RTA) to cause phase shift. The upper electrode layer 28 is stacked on top of the second layer 25. The upper electrode layer 28 is formed by depositing a metal such as platinum, tantalum, silver, or platinum-tantalum having a thickness of 0.1 to 1.0 mu m using a sputtering method or a chemical vapor deposition method.

Referring to FIG. 2B, after applying and patterning a first photoresist (not shown) on the upper electrode layer 28, the upper electrode layer 28 is patterned using the mask to form the upper electrode 30. Then, the first photoresist is removed.

Subsequently, the fourth layer 25 is patterned in the same manner as the patterning of the upper electrode layer 28 to form the strained layer 27. That is, after the second photoresist (not shown) is coated on the upper electrode 30 and the fourth layer 25 by spin coating, the fourth layer 25 using the second photoresist as a mask. Pattern. Subsequently, the lower electrode layer 23 is patterned in the same manner as the method for patterning the upper electrode layer 28 to form the lower electrode 24.

Subsequently, the lower electrode 24, the third layer 17, the etch stop layer 13, the second passivation layer 12, and the first passivation layer 9 are sequentially etched from the strained layer 27 to form a via hole 38. ) Is formed, and a via contact 39 is formed from the drain pad to the lower electrode 24 through the via hole 38. The via contact 39 is formed by depositing platinum or platinum-tantalum by a sputtering method or a chemical vapor deposition method. Subsequently, the third layer 17 is patterned in the same manner as the method for patterning the lower electrode layer 23 to form the support layer 19.

Referring to FIG. 2C, after the first sacrificial layer 14 is removed using hydrogen fluoride (HF) vapor, the second sacrificial layer 42 is removed by using a polymer having excellent fluidity on the actuator 31. Form. Subsequently, the second sacrificial layer 42 is patterned to expose a portion of the upper electrode 30 to form a post hole, and then the fluid material layer 40 is disposed on the post hole and the second sacrificial layer 42. Preferably, a silicon oxide (SiO ₂ ) film is applied.

The fluid material layer 40 is planarized until the surface of the second sacrificial layer 42 is exposed. Thus, posts that will later support the mirror layer 41 are formed by the flowable material layer 40.

Subsequently, aluminum, which is a reflective metal, is deposited on the fluid material layer 40 and the second sacrificial layer 42 by physical vapor deposition (PVD) or chemical vapor deposition to form a mirror layer 41. . After the patterning of the mirror layer 41, the second sacrificial layer 42 is removed to complete the actuator 31 having the mirror layer 41 thereon.

However, in the manufacturing method of the above-described thin film type optical path control device, when the fluid material layer made of silicon oxide is applied on the second sacrificial layer and then flattened to form a post, the silicon oxide is subjected to chemical mechanical polishing. (CMP) the amount of removal is quite small, and since the silicon oxide must be deposited to a thickness of about 5.2㎛ in order to fill the post hole, the surface of the second sacrificial layer exposed the layer of fluent material made of silicon oxide The process of planarization by chemical mechanical polishing requires a considerable time. As described above, if the chemical mechanical polishing method is performed for a long time, the outer portion of the TMA module is polished more and the center portion of the TMA module is less polished to expose the surface of the second sacrificial layer to the outer portion of the TMA module. The liquid material layer formed at the center of the TMA module is less polished and remains on top of the second sacrificial layer. When the mirror is formed on the upper part of the TMA module, the horizontal level of the mirror is lowered. There is a problem of deterioration.

Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film type optical path control apparatus which can shorten the overall process time by shortening the planarization process time and improving the light efficiency.

1 is a perspective view of a thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is a cross-sectional view of the apparatus shown in FIG. _{1 taken along} lines A ₁ -A ₂ .

3A to 3C are manufacturing process diagrams of the apparatus shown in FIG. 2.

4 is a perspective view of a thin film type optical path control apparatus according to the present invention.

FIG. 5 is a cross-sectional view of the device shown in FIG. _{4 taken along} lines B ₁ -B ₂ .

6A to 6F are manufacturing process diagrams of the apparatus shown in FIGS. 4 and 5.

<Explanation of symbols for main parts of the drawings>

100: active matrix 101: substrate

120: transistor 135: first metal layer

140: first protective layer 145: second metal layer

150: second protective layer 155: etch stop layer

160: first sacrificial layer 165: first air gap

170: support layer 171: first anchor

172a, 172b: second anchor 174: support line

175: support element 180: lower electrode

190, 191: first and second strained layers

200, 201: first and second upper electrodes 210: actuators

220, 221: first and second insulating layers

230 and 231: first and second upper electrode connecting members

249 silicon oxide layer 250 post

260: mirror 270: empty hall

280: beer contact 300: second sacrificial layer

310: second air gap

In order to achieve the above object of the present invention, the present invention provides a method of manufacturing a thin film type optical path control device comprising the step of providing an active matrix, forming an actuator, forming a support element, and forming a mirror To provide. The active matrix includes a MOS transistor, and a first metal layer having a drain pad extending from the drain of the transistor is formed. The actuator and the support element are formed by sequentially forming a first layer, a lower electrode layer, a second layer and an upper electrode layer on the active matrix, and then patterning the upper electrode layer sequentially. The actuator includes a first and a second upper electrode, a first and a second deformable layer, and a lower electrode, and the support element includes a support layer, a support line, and a first anchor and a second anchor formed by patterning the first layer. It includes. The forming of the mirror may include forming a post hole by forming a second sacrificial layer on the support element and the actuator and patterning the second sacrificial layer, and then stacking and patterning silicon oxide on the second sacrificial layer and the top of the post hole to form a post hole. A silicon oxide layer is formed on the periphery of the hole and the post hole, and then the silicon oxide layer is planarized by chemical mechanical polishing to form a post, and a mirror is formed on top of the post and the second sacrificial layer.

According to the present invention, the silicon oxide layer is laminated on the second sacrificial layer and the upper part of the post hole and patterned to form a silicon oxide layer on the periphery of the post hole and the post hole, and then the silicon oxide layer is planarized to form a post. And by forming a mirror on the upper portion of the second sacrificial layer, it is possible to shorten the time for the planarization process for forming the post, and to improve the horizontal degree of the mirror formed on the post, it is possible to improve the light efficiency .

Hereinafter, a manufacturing method of a thin film type optical path control device according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 3 shows a perspective view of a thin film type optical path control apparatus according to the present invention, Figure 4 shows a cross-sectional view of the device of Figure 3 cut line B ₁ -B ₂ .

Referring to FIG. 3, the thin film type optical path control apparatus according to the present invention includes an active matrix 100, a support element 175 formed on the active matrix 100, an actuator 210 formed on the support element 175, And a mirror 260 formed on the actuator 210.

3 and 4, the active matrix 100 includes a substrate 101 having M × N (M, N is a natural number) P-MOS transistors 120 and the P-MOS transistors 120. A first metal layer 135 formed on the substrate 101, a first passivation layer 140 formed on the first metal layer 135, and a first passivation layer extending from the drain 105 and the source 110. The second metal layer 145 formed on the upper portion of the 140, the second protective layer 150 formed on the second metal layer 145, and the etch stop layer 155 formed on the second protective layer 150 are disposed. Include.

The first metal layer 135 includes a drain pad extending from the drain 105 of the P-MOS transistor 120 to transmit a first signal (image signal), and the second metal layer 145 includes a titanium layer and nitride. It consists of a titanium layer.

Referring to FIG. 3, the support element 175 includes a support line 174, a support layer 170, a first anchor 171, and second anchors 172a and 172b. The support line 174 and the support layer 170 are horizontally formed on the etch stop layer 155 via the first air gap 165. The common electrode line 240 is formed on the support line 174, and the support line 174 serves to support the common electrode line 240.

The support layer 170 has a rectangular ring shape, preferably a rectangular ring shape, and is integrally formed with the support line 174 along a direction orthogonal to the support line 174 on the same plane. The first anchor 171 is integrally formed with the two arms in the lower portion between the two arms horizontally extending in the direction orthogonal to the support line 174 of the square ring-shaped support layer 170 to form an etch stop layer ( 155, and two second anchors 172a and 172b are formed integrally with the two arms at an outer lower portion of the two arms and attached to the etch stop layer 155. The first anchor 171 and the second anchors 172a and 172b each have a shape of a rectangular box.

The support layer 170 is supported by the first anchor 171 in the center portion and supported by both anchors 172a and 172b. The first anchor 171 is formed at a portion of the etch stop layer 155 where the drain pad of the first metal layer 135 is located. In the central portion of the first anchor 171, the first metal layer may be formed through the etch stop layer 155, the second passivation layer 150, the holes (not shown) of the second metal layer 145, and the first passivation layer 140. The via hole 270 is formed to the drain pad of the 135.

The actuator 210 is formed on the support layer 170 in the shape of a mirror 'C' with respect to the support line 174. The actuator 210 includes a lower electrode 180, a first strained layer 190, a second strained layer 191, a first upper electrode 200, and a second upper electrode 201. The lower electrode 180 has a mirror-shaped 'c' shape spaced apart from the support line 174 by a predetermined distance, and is stepped toward the first anchor 171 at both sides of one side of the lower electrode 180. The protrusions are formed corresponding to each other. The protrusions of the lower electrode 180 extend to the periphery of the via hole 270 formed in the first anchor 171, respectively.

The via contact 280 is formed from the drain pad of the first metal layer 135 to the protrusions of the lower electrode 180 through the via hole 280 to electrically connect the drain pad and the lower electrode 180.

The two arms of the mirror-shaped 'c' shaped lower electrode 180 each have a rectangular flat plate shape, and the first and second deformable layers 190 and 191 respectively have two arms of the lower electrode 180. It has a shape of a rectangular flat plate with a narrower area and is formed on top of two arms of the lower electrode 180. In addition, the first and second upper electrodes 200 and 201 have a shape of a rectangular plate having a smaller area than the first and second deformable layers 190 and 191, respectively, and have the first and second deformed layers 190 and 191. It is formed at the top of the.

The first insulating layer 220 is formed from one side of the first upper electrode 200 to a part of the support layer 170 through the first deforming layer 190 and the lower electrode 180, and the first upper electrode 200. The first upper electrode connecting member 230 is formed from one side of the first through the first insulating layer 220 and the support layer 170 to the common electrode line 240. The first upper electrode connecting member 230 connects the first upper electrode 200 and the common electrode line 240 to each other, and the first insulating layer 220 is formed of the first upper electrode 200 and the lower electrode 180. One side is connected to each other to prevent the electrical short (short) occurs. In addition, a second insulating layer 221 is formed from one side of the second upper electrode 201 to a part of the support layer 170 through the second strained layer 191 and the lower electrode 180, and the second upper electrode ( The second upper electrode connecting member 231 is formed from one side of the 201 to the common electrode line 240 through a portion of the second insulating layer 221 and the support layer 170. The second insulating layer 221 and the second upper electrode connecting member 231 are formed to be parallel to the first insulating layer 220 and the first upper electrode connecting member 230, respectively. The second upper electrode connecting member 231 connects the second upper electrode 201 and the common electrode line 240 to each other, and the second insulating layer 221 is formed of the second upper electrode 201 and the lower electrode 180. The other side is connected to each other to prevent electrical short circuit.

A mirror 260 and a mirror 260 may be disposed on a portion of the lower electrode 280 where the first and second upper electrodes 200 and 201 are not formed, that is, a portion formed parallel to the support line 174. A supporting post 250 is formed. The mirror 260 is supported at the center portion by the post 250, and both sides thereof are horizontally formed on the upper portion of the actuator 210 via the second air gap 310. The mirror 260 reflects light incident from a light source (not shown) at a predetermined angle so that the image is projected onto the screen.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5F are diagrams for describing a method of manufacturing the apparatus shown in FIGS. 3 and 4. In Figs. 5A to 5F, the same reference numerals are used for the same members as Figs. 3 and 4.

Referring to FIG. 5A, first, a device isolation layer 125 is formed on a substrate 101, which is a silicon wafer doped with n-type, by using a silicon partial oxidation (LOCOS) method. Subsequently, after forming the gate 115 made of a conductive material such as polysilicon of the active region, p ⁺ source 110 and drain 105 are formed by an ion implantation process, thereby forming M × N on the substrate 101. (M and N are natural numbers) P-MOS transistors 120 are formed.

After the insulating film 130 made of oxide is formed on the P-MOS transistor 120 formed thereon, the source 110 and the one side of the drain 105 of the transistor 120 by photolithography are respectively formed. Form openings that expose. Subsequently, after depositing the first metal layer 135 made of titanium, titanium nitride, tungsten, nitride, or the like on the resultant, the first metal layer 135 is patterned by photolithography. The patterned first metal layer 135 includes a drain pad extending from the drain 205 of the transistor 120 to the bottom of the first anchor 171 supporting the support layer 170.

The first passivation layer 140 is stacked on the substrate 101 on which the first metal layer 135 and the transistor 120 are formed. The first passivation layer 140 is formed to have a thickness of about 8000 Å by depositing silicate glass (PSG) by chemical vapor deposition (CVD). The first protective layer 140 prevents damage to the substrate 101 in which the P-MOS transistor 120 is embedded during a subsequent process.

A second metal layer 145 formed of a titanium layer and a titanium nitride layer is formed on the first protective layer 140. The titanium layer is deposited by sputtering to have a thickness of about 300 kPa, and the titanium nitride layer is formed on the titanium layer by physical vapor deposition (PVD) to have a thickness of about 1200 kPa. Since the light incident from the light source is incident on the second metal layer 145 not only the mirror 260 but also a portion other than the portion covered by the mirror 260, a photo leakage current is applied to the substrate 101. To prevent the device from malfunctioning. Subsequently, a portion of the second metal layer 145 in which the via hole 270 is to be formed in a subsequent process, that is, a portion in which the drain pad of the first metal layer 135 is located is etched to form a hole in the second metal layer 145. Not shown).

The second passivation layer 150 is stacked on the second metal layer 145. The second protective layer 150 is formed to have a thickness of about 2000 kPa by depositing the silicate glass by chemical vapor deposition. The second protective layer 150 prevents the substrate 101 and the resulting products formed on the substrate 101 from being damaged during subsequent processing.

An etch stop layer 155 is stacked on the second passivation layer 150. The etch stop layer 155 prevents the second passivation layer 150 and the results on the substrate 101 from being etched and damaged during the subsequent etching process. The etch stop layer 155 is formed using a low temperature oxide such as silicon oxide or phosphorus pentoxide. The etch stop layer 155 is formed to have a thickness of about 0.2 to 0.8 μm at a temperature of about 350 to 450 ° C. by low pressure chemical vapor deposition (LPCVD). Accordingly, the substrate 101 having the transistor 120 embedded therein, the first metal layer 135, the first protective layer 140, the second metal layer 145, the second protective layer 150, and the etch stop layer 155 may be formed. The active matrix 100 is completed.

The first sacrificial layer 160 made of polysilicon is stacked on the etch stop layer 155. The first sacrificial layer 160 serves to facilitate stacking of the thin films constituting the actuator 210. The first sacrificial layer 160 is deposited by a low pressure chemical vapor deposition method at a temperature of about 500 ° C. or less to form a thickness of about 2.0 to 3.0 μm. Subsequently, the surface of the first sacrificial layer 160 is polished using a chemical mechanical polishing (CMP) method to planarize the surface of the first sacrificial layer 160 to have a thickness of about 1.1 μm.

5B is a plan view illustrating a state in which the first sacrificial layer 160 is patterned. 5A and 5B, after applying and patterning a first photoresist (not shown) on the first sacrificial layer 160, the first sacrificial layer 160 is formed using the first photoresist as a mask. ) To expose a portion of the etch stop layer 155 by etching the portion where the hole of the second metal layer 145 is located below and portions adjacent to both sides thereof, so that the first anchor 171 and the second anchors 172a, 172b) is formed where the first photoresist is removed. Accordingly, the etch stop layer 155 is exposed in the shape of three squares spaced apart by a predetermined distance.

Referring to FIG. 5C, the first layer 169 is stacked on the exposed etch stop layer 155 and the first sacrificial layer 160. The first layer 169 is formed to have a thickness of about 0.1 to 1.0 μm by depositing a hard material such as nitride or metal by low pressure chemical vapor deposition (LPCVD). The first layer 169 is later patterned with a support element 275 that includes a support layer 170, a support line 174, and anchors 171, 172a, 172b.

The lower electrode layer 179 is stacked on top of the first layer 169. The lower electrode layer 179 is formed to have a thickness of about 0.1 to 1.0 μm by depositing a metal having electrical conductivity such as platinum, tantalum or platinum-tantalum by a sputtering method or a chemical vapor deposition method. The lower electrode layer 179 is later applied with a first signal, and is patterned as a mirror-shaped 'c' shaped lower electrode 180 formed on both sides of one side to correspond to each other.

A second layer 189 made of a piezoelectric material such as PZT or PLZT is formed on the lower electrode layer 179. Preferably, the second layer 189 is formed to have a thickness of about 0.4 μm by spin coating PZT prepared by the sol-gel method. Subsequently, the piezoelectric material constituting the second layer 189 is subjected to heat treatment by a rapid thermal treatment (RTA) method for phase shifting. The second layer 189 may be the first strained layer 190 and the second upper electrode 201, which are deformed by a first electric field generated between the first upper electrode 200 and one side of the lower electrode 180. And a second deformation layer 191 causing deformation by a second electric field generated between the other side of the lower electrode 180 and the other side.

The upper electrode layer 199 is stacked on top of the second layer 189. The upper electrode layer 199 is formed by depositing a metal having electrical conductivity such as platinum, tantalum, silver or platinum-tantalum by sputtering or chemical vapor deposition to have a thickness of about 0.1 to 1.0 μm. The upper electrode layer 199 is later patterned with a first upper electrode 200 and a second upper electrode 201, each of which is applied with a second signal (bias signal) and spaced apart by a predetermined distance.

Referring to FIG. 5D, after applying and patterning a second photoresist (not shown) on the upper electrode layer 199, each of the upper electrode layers 199 may be formed using a second photoresist as a mask. The first upper electrode 200 and the second upper electrode 201 are formed in a shape, preferably, in a rectangular flat plate and spaced apart from each other by a predetermined distance, and then the second photoresist is removed. The second signal is applied to the first and second upper electrodes 200 and 201 through the common electrode line 240 formed later from the outside, respectively.

Subsequently, by patterning the second layer 189 in the same manner as the method of patterning the upper electrode layer 199, each of the first strained layer 190 having a shape of a rectangular flat plate and formed side by side at a predetermined distance from each other; The second strained layer 191 is formed. In this case, as shown in FIG. 3, the first and second deformable layers 190 and 191 have a rectangular flat shape with a slightly larger area than the first and second upper electrodes 300 and 301, respectively.

Subsequently, the lower electrode layer 179 has a mirror-shaped 'c' shape with respect to the support line 174 formed later, and has a lower electrode 180 having protrusions formed in a step toward the first anchor 171. To form. In this case, the two arms of the lower electrode 180 are formed to have a rectangular flat plate having a larger area than the first and second deformable layers 190 and 191, respectively. In addition, when the lower electrode layer 179 is patterned, the common electrode line 240 is simultaneously formed with the lower electrode 180 in a direction orthogonal to the lower electrode 180 on one side of the first layer 169. The common electrode line 240 is formed to be spaced apart from the lower electrode 180 by a predetermined distance on the support line 174 formed later. Thus, the actuator 210 including the first and second upper electrodes 200 and 201, the first and second strained layers 190 and 191, and the lower electrode 180 is completed.

Subsequently, the first layer 169 is patterned to form a support element 175 comprising a support layer 170, a support line 174, a first anchor 171 and second anchors 172a and 172b. . In the first layer 169, both sides of the portions contacting the etch stop layer 155 exposed in the shape of the three quadrangles are second anchors 172a and 172b, and the center portion of the first anchor 171 is used. Becomes Each of the first anchor 171 and the second anchors 172a and 172b has a rectangular box shape, and a hole of the second metal layer 145 and a hole of the first metal layer 135 are disposed below the first anchor 171. The drain pad is located. The first and second deformable layers 190 and 191 are formed parallel to each other on two arms horizontally extending in a direction orthogonal to the support line 174 of the support layer 170, respectively. Accordingly, the first anchor 171 is formed below the mirror-shaped 'c' shaped lower electrode 180, and the second anchors 172a and 172b are formed below the outer electrode 180, respectively. do.

Next, a third photoresist (not shown) is applied and patterned on the support element 175 and the actuator 210 to form first and second upper portions from the common electrode line 240 formed on the support line 274. Portions of the electrodes 200 and 201 are exposed. At this time, the protrusions of the lower electrode 180 are also exposed together from the first anchor 171.

Subsequently, by depositing and patterning a low temperature oxide such as amorphous silicon or silicon oxide to phosphorus pentoxide on the exposed portion, a portion of the first upper electrode 200 is formed through the first strained layer 190 and the lower electrode 180. The first insulating layer 220 is formed to a part of the support layer 170, and at the same time, a part of the support layer 170 is formed from the part of the second upper electrode 201 through the second strained layer 191 and the lower electrode 180. Until the second insulating layer 221 is formed. The first and second insulating layers 220 and 221 are formed to have a thickness of about 0.2 to 0.4 μm, respectively, by low pressure chemical vapor deposition (LPCVD).

Subsequently, the first anchor 171, the etch stop layer 155, and the etch stop layer 155 are formed from an upper portion of the center of the first anchor 171, which is a portion where the hole of the second metal layer 145 and the drain pad of the first metal layer 135 are formed. A portion of the second passivation layer 150 and the first passivation layer 140 is etched to form a via hole 270 up to the drain pad of the first metal layer 135, and then a lower portion thereof is formed through the via hole 270 from the drain pad. The via contact 280 is formed to the protrusions of the electrode 180 (see FIG. 4). At the same time, the first upper electrode connecting member 230 is formed from the first upper electrode 200 to the common electrode line 240 through a portion of the first insulating layer 220 and the support layer 170, and the second upper electrode The second upper electrode connecting member 231 is formed from the 201 to the common electrode line 240 through a portion of the second insulating layer 221 and the support layer 170.

The via contact 280, the first and second upper electrode connection members 230 and 231 are respectively deposited with platinum, tantalum or platinum-tantalum to have a thickness of about 0.1 to 0.2 μm by sputtering or chemical vapor deposition. This deposited metal is then patterned to form. The first and second upper electrode connecting members 230 and 231 connect the first and second upper electrodes 200 and 201 and the common electrode line 240, respectively, and the lower electrode 180 connects the via contact 280. It is connected to the drain pad of the first metal layer 135 through.

Referring to FIG. 5E, polysilicon or amorphous silicon is laminated on the actuator 210 and the support element 175 by a plasma enhanced chemical vapor deposition (PECVD) method to form a second sacrificial layer ( 300).

In addition, the second sacrificial layer 300 is patterned so that portions of the lower electrode 180 formed parallel to the support line 174 (that is, the first and second upper electrodes 200 and 201 are not formed thereon). A portion of the non-coated portion) to form a post hole from the second sacrificial layer 300 to the lower electrode 180, thereby creating a position where a post 250 supporting the mirror 260 is subsequently formed.

Subsequently, silicon oxide (SiO ₂ ) is deposited on the post hole and the second sacrificial layer 300 by plasma enhanced chemical vapor deposition to fill the post hole. The silicon oxide layer 249 is formed on the post hole and the periphery of the post hole by patterning the stacked silicon oxide. In the method of patterning the stacked silicon oxide, a fourth photoresist (not shown) is applied and patterned on the stacked silicon oxide to form the fourth photoresist pattern on the post hole. By etching the silicon oxide by a wet etching method, the silicon oxide layer 249 is formed in the periphery of the post hole and the post hole. Therefore, the silicon oxide layer 249 is formed to a predetermined thickness on the post hole and the post hole peripheral part, and the upper part of the second sacrificial layer 300 is exposed on the outer part of the post hole peripheral part.

Referring to FIG. 5F, the second sacrificial layer 300 is formed on the upper portion of the silicon oxide layer 249 filled in the post hole by chemical mechanical polishing (CMP). Flatten to form a post 250 until it coincides with the top of the.

As described above, when the silicon oxide layer 249 is formed on the second sacrificial layer 300 and the post hole, and then the planarization process is performed by chemical mechanical polishing, the conventional second sacrificial layer 300 and the post are formed. By planarizing the silicon oxide film formed on the upper portion of the hole by a chemical mechanical polishing method, the process time can be prevented from being extended and the level of the mirror can be prevented from being lowered. Therefore, the process time can be shortened and the light efficiency of light can be improved.

Subsequently, a reflective metal, preferably aluminum (Al), is deposited on the post 250 and the second sacrificial layer 300 by sputtering or chemical vapor deposition to form a mirror 260.

Subsequently, the second sacrificial layer 300 is removed at room temperature using xenon fluoride (XeF ₂ ), and the first sacrificial layer (XrF ₂ ) is used using xenon fluoride (XeF ₂ ) or bromine fluoride (BrF ₂ ). After removing 160), cleaning and drying are performed to complete the TMA element as shown in FIG. As such, when the first and second sacrificial layers 160 and 300 are removed, the first and second air gaps 165 and 310 are formed, respectively.

According to the manufacturing method of the thin film type optical path control device according to the present invention, after the silicon oxide is laminated on the second sacrificial layer and the post hole and patterned to form a silicon oxide layer on the periphery of the post hole and the post hole, the silicon oxide layer To form a post, and to form a mirror on top of the post and the second sacrificial layer, the planarization process time for forming the post can be shortened, and the planarity of the second sacrificial layer can be reduced by shortening the planarization process time. Can be prevented from being lowered, so that the horizontality of the mirror formed thereon can be improved. As a result, since the light efficiency of the light incident on the mirror can be improved, the image quality of the image projected on the screen can be improved.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be modified in various ways without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (1)

Providing an active matrix including a first metal layer having a MOS transistor embedded therein and having a drain pad extending from the drain of the transistor; A first layer, a lower electrode layer, a second layer and an upper electrode layer are formed on the active matrix, and the upper electrode layer, the second layer, and the lower electrode layer are patterned to form first and second upper electrodes, first and second electrodes. Forming an actuator including a second strained layer and a lower electrode; Patterning the first layer to form a support line, a support layer, and support means including first and second anchors; Applying a sacrificial layer on top of the support means and the actuator and patterning the sacrificial layer to form a post hole; Depositing silicon oxide on top of the post hole and the sacrificial layer and patterning the deposited silicon oxide to form a silicon oxide layer on top of the post hole and the periphery of the post hole; Planarizing the silicon oxide layer to form a post; And And forming a mirror on the post and the sacrificial layer.