KR20000024882A - Method for manufacturing thin film type actuated mirror arrays - Google Patents

Abstract

PURPOSE: A method for manufacturing an actuated mirror arrays(AMA) is provided to increase a light efficiency by forming a horizontal mirror on an upper portion of a second sacrificial layer through a deposition of a hard mask. CONSTITUTION: A second sacrificial layer(300) having an enough height to completely cover an actuator(210) is formed. A hard mask(320) is formed after a fourth photoresist (310) is coated on an upper portion of the second sacrificial layer(300). A patterning process is performed on the hard mask(320) and the patterned hard mark(320) is used as an etching mask. The second sacrificial layer(300) and the fourth photoresist (310) are removed, a first sacrificial layer(160) are removed. Washing and drying processes are carried out to obtain an actuated mirror arrays(AMA) device.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control device using thin-film micromirror array-actuated (TMA), and more particularly, to a thin film type optical path control device capable of increasing the optical efficiency of incident light by improving the horizontal level of a mirror. It relates to a manufacturing method.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, image processing apparatuses using such an optical modulator are classified into a direct view type image display device and a projection type image display device according to a method of displaying optical energy on a screen.

An example of a direct view type image display device is a CRT (Cathode Ray Tube), which is a so-called CRT device, which has excellent image quality but increases its weight and volume as the size of the screen increases, leading to an increase in manufacturing cost. There is. Examples of the projection image display apparatus include a liquid crystal display (LCD), a deformable mirror device (DMD), and an actuated mirror array (AMA). Such projection image display apparatuses can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmit light modulators, while DMD and AMA can be classified as reflected light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, the light efficiency is low due to the polarity of the light, there is a problem inherent in the liquid crystal material, for example, the response speed is slow and its inside is easy to overheat. In addition, the maximum light efficiency of existing transmission optical modulators is limited to a range of 1-2% and requires dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path control device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein into an active matrix in which transistors are built, and then processing it using a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the deformation layer is slow.

Accordingly, a thin film type optical path control device (TMA) that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 98-26319 filed by the applicant of the Korean Patent Office on June 30, 1998 have.

FIG. 1 is a perspective view of the thin film type optical path control device, and FIG. 2 is a cross-sectional view of the device of FIG. 1 taken along line A ₁ A ₂ .

1 and 2, the thin film type optical path control device includes an active matrix 16, a support element 18, an actuator 31, and a mirror 41.

Referring to FIG. 2, the active matrix 16 includes a substrate 1 in which M × N (M, N is a natural number) MOS transistors 5, a drain 2 and a source of the MOS transistor 5. 3) a first metal layer 8 formed on top of the substrate 1, a first passivation layer 9 formed on top of the first metal layer 8, a second metal layer 10, and a second passivation layer ( 12) and the etch stop layer (13).

Referring to FIG. 1, the support element 18 comprises a support layer 19, a support line 20, a first anchor 21 and second anchors 22a, 22b. The support line 20 and the support layer 19 are horizontally formed on the etch stop layer 13 via the first air gap 15, and the common electrode line 32 is formed on the support line 20. The support layer 19 is integrally formed along the direction orthogonal to the support line 20 in the shape of a rectangular ring on the same plane. A first anchor 21 is formed at a lower portion between two arms horizontally extending in a direction orthogonal to the support line 20 of the support layer 19 to be attached to the etch stop layer 13. Two second anchors 22a and 22b are attached to the etch stop layer 13 at an outer lower portion thereof. The support layer 19 is supported by the first anchor 21 in the center portion and supported by both anchors 22a and 22b. The first anchor 21 is formed at a portion of the etch stop layer 13 where the drain pad of the first metal layer 8 is positioned. A via hole 38 is formed from the central portion of the first anchor 21 to the drain pad of the first metal layer 8.

The actuator 31 includes a lower electrode 24, a first strained layer 26, a second strained layer 27, a first upper electrode 29, and a second upper electrode 30. The lower electrode 24 has a mirror-shaped 'c' shape spaced apart from the support line 20 by a predetermined distance, and protrudes stepped toward the first anchor 21 on one side of the lower electrode 24. Are formed corresponding to each other. The protrusions of the lower electrode 24 extend to the periphery of the via hole 38 formed in the first anchor 21, respectively.

The via contact 39 is formed from the drain pad of the first metal layer 8 to the protrusions of the lower electrode 24 through the via hole 38 to electrically connect the drain pad and the lower electrode 24. The two arms of the lower electrode 24 each have a shape of a rectangular plate, and the first and second deformable layers 26 and 27 respectively have a shape of a rectangular plate having a narrower area than the two arms of the lower electrode 24. And is formed on top of the two arms of the lower electrode 24. In addition, the first and second upper electrodes 29 and 30 have a shape of a rectangular flat plate having a smaller area than the first and second deformable layers 26 and 27, respectively, and the first and second deformable layers 26 and 27. It is formed at the top of the.

The first insulating layer 34 is formed from one side of the first upper electrode 29 to a part of the supporting layer 19, and the first insulating layer 34 and the supporting layer 19 from one side of the first upper electrode 29. The first upper electrode connecting member 36 is formed up to the common electrode line 32 through a portion of the upper electrode connecting member 36. In addition, a second insulating layer 35 is formed from one side of the second upper electrode 30 to a part of the support layer 19, and the second insulating layer 35 and the supporting layer (from one side of the second upper electrode 30) A second upper electrode connecting member 37 is formed up to the common electrode line 32 through a portion of 19.

The mirror 41 is supported on a portion of the mirror-shaped 'c'-shaped lower electrode 24 in which the first and upper electrodes 29 and 30 are not formed, that is, parallel to the support line 20. Post 40 is formed. The mirror 41 is centrally supported by the post 40, and both sides thereof are horizontally formed on the upper portion of the actuator 31 via the second air gap 43. The mirror 41 serves to reflect light incident from a light source (not shown) at a predetermined angle.

Hereinafter, a method of manufacturing the above-described thin film type optical path control device will be described.

3A to 3C are diagrams for describing a method of manufacturing the apparatus shown in FIG. 2. Referring to FIG. 3A, an isolation layer 6 is formed on a substrate 1, which is an n-type doped silicon wafer, by using a silicon partial oxidation method (LOCOS) to distinguish between an active region and a field region. Subsequently, a gate 4 made of a conductive material such as polysilicon is formed on the active region, and then p ⁺ source 3 and drain 2 are formed by an ion implantation process, thereby forming M on the substrate 1. N (M and N are natural numbers) P-MOS transistors 5 are formed.

After the insulating film 7 made of oxide is formed on the P-MOS transistor 5 formed thereon, openings are formed to expose the upper portions of one side of the source 3 and the drain 2 by photolithography. . Subsequently, a first metal layer 8 made of titanium, titanium nitride, tungsten, nitride, or the like is deposited on the resultant product on which the openings are formed, and then the first metal layer 8 is patterned. The patterned first metal layer 8 includes a drain pad extending from the drain 2 of the P-MOS transistor 5 to the bottom of the first anchor 21.

A first protective layer 9 is formed on the first metal layer 8 and on the substrate 1 to prevent the substrate 1 having the P-MOS transistor 5 therein from being damaged due to a subsequent process. The first protective layer 9 is formed to have a thickness of 8000 kPa by depositing silicate glass (PSG) by chemical vapor deposition (CVD).

The second metal layer 10 is formed on the first protective layer 9. The second metal layer 10 is formed by sputtering titanium to form a titanium layer having a thickness of 300 kPa, and depositing titanium nitride on the titanium layer by physical vapor deposition (PVD) to form a titanium nitride layer having a thickness of 1200 kPa. It is completed by forming. The second metal layer 10 also enters a portion other than the portion covered by the mirror 41 so that photocurrent flows through the active matrix 16 to prevent the device from malfunctioning. Subsequently, a portion of the second metal layer 10 formed after the drain pad of the first metal layer 8 under which the via hole 38 is to be formed is etched to etch a hole in the second metal layer 10 (not shown). To form.

The second protective layer 12 is stacked on the second metal layer 10. The second protective layer 12 is formed to have a thickness of about 2000 kPa by depositing the silicate glass by chemical vapor deposition. The second protective layer 12 prevents the substrate 1 and the resulting products formed on the substrate 1 from being damaged during subsequent processing.

On top of the second passivation layer 12, an etch stop layer 13 is deposited to prevent the second passivation layer 12 and the products on the substrate 1 from being etched during the subsequent etching process. The etch stop layer 13 is formed by depositing low temperature oxides (LTO) such as silicon oxide (SiO ₂ ) or phosphorus pentoxide (P ₂ O ₅ ) by low pressure chemical vapor deposition (LPCVD) to form 0.2 to 0.8 at a temperature of 350 to 450 ° C. It is formed to have a thickness of μm.

The first sacrificial layer 14 is stacked on the etch stop layer 13. The first sacrificial layer 14 is formed to have a thickness of 2.0 to 3.0 μm by depositing polysilicon at a temperature of 500 ° C. or less by low pressure chemical vapor deposition. Subsequently, the surface of the first sacrificial layer 14 is polished by chemical mechanical polishing (CMP) to planarize the surface of the first sacrificial layer 14 to have a thickness of 1.1 mu m. Subsequently, after applying and patterning a first photoresist (not shown) on top of the first sacrificial layer 14, the second metal layer 12 below the first sacrificial layer 14 is used as a mask. By etching a portion where the hole is formed and portions adjacent to both sides to expose a portion of the etch stop layer 13, thereby creating a position where the first anchor 21 and the second anchors 22a and 22b are to be formed and Remove the photoresist. Accordingly, the etch stop layer 13 is exposed in the shape of three squares spaced apart by a predetermined distance.

The first layer 17 is stacked on the exposed etch stop layer 13 and the first sacrificial layer 14 as described above. The first layer 17 is formed by depositing nitride by a low pressure chemical vapor deposition method to have a thickness of 0.1 ~ 1.0㎛. The lower electrode layer 23 is stacked on top of the first layer 17. The lower electrode layer 23 is formed to have a thickness of 0.1 to 1.0 μm by depositing a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta) by a sputtering method or a chemical vapor deposition method.

The second layer 25 made of a piezoelectric material is stacked on the lower electrode layer 23. The second layer 25 is formed by spin coating PZT prepared by the sol-gel method to have a thickness of 0.4 μm. Subsequently, the piezoelectric material constituting the second layer 25 is subjected to heat treatment by rapid thermal treatment (RTA) to cause phase shift. The upper electrode layer 28 is stacked on top of the second layer 25. The upper electrode layer 28 is formed by depositing a metal such as platinum, tantalum, silver, or platinum-tantalum by a sputtering method or a chemical vapor deposition method to have a thickness of 0.1 to 1.0 μm.

Referring to FIG. 3B, after applying and patterning a second photoresist (not shown) on the upper electrode layer 28, the upper electrode layer 28 has a rectangular flat shape using the mask as a mask. After patterning the first and second upper electrodes 29 and 30 spaced apart by a predetermined distance, the second photoresist is removed. A second signal (bias signal) is applied to the first and second upper electrodes 29 and 30 through a common electrode line 32 formed later from the outside, respectively.

Subsequently, the second layer 25 is patterned in the same manner as the patterning of the upper electrode layer 28 to form a rectangular flat plate, and the first and second strained layers 26 and 27 spaced apart by a predetermined distance from each other. ). In this case, as shown in FIG. 1, the first and second strained layers 26 and 27 are patterned to have a rectangular flat plate shape slightly wider than the first and second upper electrodes 29 and 30, respectively.

Subsequently, the lower electrode layer 23 has a mirror-shaped 'c' shape with respect to the support line 20 formed later by patterning the lower electrode layer 23, and has a lower electrode 24 having protrusions formed stepped toward the first anchor 21. ). In this case, the two arms of the lower electrode 24 have the shape of a rectangular flat plate having a larger area than the first and second deforming layers 26 and 27, respectively. In addition, when the lower electrode layer 23 is patterned, the common electrode line 32 is simultaneously formed on one side of the first layer 17 in a direction perpendicular to the lower electrode 24. The common electrode line 32 is formed to be spaced apart from the lower electrode 24 by a predetermined distance on the support line 20 formed later.

The first layer 17 is then patterned to form a support element 18 comprising a support layer 19, a support line 20, a first anchor 21 and second anchors 22a, 22b. At this time, both sides of the portion of the first layer 17 which contacts the etch stop layer 13 exposed in the three quadrangles are second anchors 22a and 22b, and the center portion of the first anchor 21 is do. Each of the first anchor 21 and the second anchors 22a and 2b has a rectangular box shape, and a hole of the second metal layer 10 and a hole of the first metal layer 8 are disposed below the first anchor 21. A drain pad is formed. Therefore, the first anchor 21 is formed below the lower electrode 24, and the second anchors 22a and 22b are formed below the outer side of the lower electrode 24, respectively.

Subsequently, a third photoresist (not shown) is applied and patterned on the support element 18 and the actuator 31 to form first and second upper portions from the common electrode line 32 formed on the support line 19. A part of the electrodes 29 and 30 are exposed respectively. At this time, even the protrusions of the lower electrode 24 are exposed together from the first anchor 21. Subsequently, the first insulating layer 34 is deposited from a part of the first upper electrode 29 to a part of the support layer 19 by depositing and patterning amorphous silicon or silicon oxide or phosphorus pentoxide, which is a low temperature oxide, on the exposed portion. At the same time, the second insulating layer 35 is formed from a part of the second upper electrode 30 to a part of the support layer 19. The first and second insulating layers 34 and 35 are formed to have a thickness of 0.2 to 0.4 µm, respectively, by low pressure chemical vapor deposition (LPCVD).

The first anchor 21, the etch stop layer 13, and the second anchor 21 are formed from a central portion of the first anchor 21, which is a portion where the hole of the second metal layer 10 and the drain pad of the first metal layer 8 are formed. After the protective layer 12 and the first protective layer 9 are etched to form the via hole 38 to the drain pad, the via contact is extended from the drain pad to the protrusions of the lower electrode 24 through the via hole 38. 39). At the same time, a portion of the second insulating layer 35 and the support layer 19 is removed from the first upper electrode connecting member 36 and the second upper electrode 30 from the first upper electrode 29 to the common electrode line 32. The second upper electrode connecting member 37 is formed to the common electrode line 32 through the second electrode.

The via contact 39 and the first and second upper electrode connecting members 36 and 37 are deposited by depositing platinum or platinum-tantalum to have a thickness of 0.1 to 0.2 μm by sputtering or chemical vapor deposition. Patterned metal is formed. The first and second upper electrode connecting members 36 and 37 connect the first and second upper electrodes 29 and 30 to the common electrode line 32, respectively, and the lower electrode 24 connects the via contact 39. It is connected to the drain pad through.

Referring to FIG. 3C, the second sacrificial layer 42 is formed by spin coating an acfloflo on top of the support element 18 and the actuator 31. Subsequently, in order to form the mirror 41 and the post 40, after applying and patterning a fourth photoresist (not shown) on the second sacrificial layer 42, the fourth photoresist is used as a mask. By etching a portion of the second sacrificial layer 42, a portion of the mirror-shaped 'c'-shaped lower electrode 24 that is not adjacent to the support line 20 but formed in parallel to the support line 20 (that is, the first portion thereon). And a portion where the second upper electrodes 29 and 30 are not formed.

Next, aluminum is deposited on a portion of the exposed lower electrode 24 and the second sacrificial layer 42 to a thickness of 0.1 to 1.0 μm using a sputtering method or a chemical vapor deposition method. By patterning to form a mirror 41 having a shape of a square flat plate and a post 40 for supporting the mirror 41 at the same time. After the second sacrificial layer 42 and the fourth photoresist are removed by plasma ashing, the first sacrificial layer 14 is replaced with xenon fluoride (XeF ₂ ) or bromine fluoride (BrF ₂ ). Removal, and washing and drying treatments are completed to complete the TMA device as shown in FIG.

However, in the above-described manufacturing method of the thin film type optical path control device, although the second sacrificial layer made of AccuFlu has an advantage of being flattened at the same time as the coating, the photoresist and AccuLop have similar etching characteristics, so that the second sacrificial layer When the photoresist is applied on the second sacrificial layer for patterning and the photoresist is exposed and developed, the photoresist is etched together while the accucu is etched together or the second sacrificial layer is etched to deform the photoresist pattern. Therefore, not only the second sacrificial layer may not be accurately patterned, but also the horizontality of the mirror formed thereon is greatly reduced. In addition, an outgasing phenomenon occurs while removing the second sacrificial layer and the photoresist, thereby causing a problem in that the edge portion of the mirror is bent. As a result, the horizontality of the mirror decreases, making it difficult to maintain a constant reflection angle of the light incident from the light source, resulting in low light efficiency, resulting in a problem of deterioration of the image quality of the image projected on the screen.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film type optical path control apparatus that can increase the light efficiency by forming a horizontal mirror by depositing a hard mask on the second sacrificial layer and forming a mirror thereon. .

1 is a perspective view of a thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is a cross-sectional view of the apparatus shown in FIG. _{1 taken along} lines A ₁ -A ₂ .

3A to 3C are manufacturing process diagrams of the apparatus shown in FIG. 2.

Figure 4 is a perspective view of a thin film type optical path control apparatus according to the present invention.

FIG. 5 is a cross-sectional view of the apparatus shown in FIG. _{4 taken along} line B ₁ -B ₂ .

6A to 6E are manufacturing process diagrams of the apparatus shown in FIGS. 4 and 5.

<Explanation of symbols for main parts of the drawings>

100: active matrix 101: substrate

120: transistor 135: first metal layer

140: first protective layer 145: second metal layer

150: second protective layer 155: etch stop layer

160: first sacrificial layer 170: support layer

171: first anchor 172a, 172b: second anchor

174: support line 175: support element

180: lower electrode 190, 191: first and second strained layers

200, 201: first and second upper electrodes 210: actuators

220, 221: first and second insulating layers

230 and 231: first and second upper electrode connecting members

250: Post 260: Mirror

270: Beer Hall 280: Beer Contact

300: second sacrificial layer 310: fifth photoresist

320: hard mask

In order to achieve the above object of the present invention, the present invention provides a method of manufacturing a thin film type optical path control device comprising the step of providing an active matrix, forming an actuator, forming a support element, and forming a mirror To provide. The active matrix includes a MOS transistor, and a first metal layer having a drain pad extending from the drain of the transistor is formed. The actuator and the support element may form and pattern a first sacrificial layer on the active matrix, and then form a first layer, a lower electrode layer, a second layer, and an upper electrode layer thereon, and then pattern the layers. Is formed. The actuator includes first and second upper electrodes, first and second deformable layers, and a lower electrode, wherein the support element includes a support line, a support layer integrally formed with the support line, and the support line among the support layers. First anchors and second anchors respectively contacting the active matrix below the adjacent portion. The forming of the mirror may include forming a second sacrificial layer on the support means and the actuator, forming a photoresist and a hard mask on the second sacrificial layer, and then patterning the hard mask. It is performed after etching a part of the second sacrificial layer using a patterned hard mask.

According to the present invention, after the photoresist and the hard mask are formed on the second sacrificial layer, the second sacrificial layer is patterned and a mirror is formed on the hard mask. Thus, since the second sacrificial layer is accurately patterned and the hard mask compensates for the stress generated during the deposition of the mirror, the horizontality of the mirror formed on the hard mask can be improved. In addition, since the hard mask is formed using the same metal as the mirror, the hard mask may serve as a seed layer for depositing the mirror layer, thereby easily forming the mirror, and the second sacrificial layer and Out gasing, which occurs when removing the photoresist, can prevent the edge portion of the mirror from bending. Accordingly, the light efficiency of the light incident on the mirror from the light source can be increased to improve the image quality of the image projected on the screen.

Hereinafter, a thin film type optical path control apparatus and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 4 shows a perspective view of the thin film type optical path control apparatus according to the present invention, Figure 5 shows a cross-sectional view of the device of Figure 4 cut line B ₁ -B ₂ .

Referring to FIG. 4, the thin film type optical path control device according to the present invention includes an active matrix 100, a support element 175 formed on the active matrix 100, and an actuator 210 formed on the support element 175. And a mirror 260 formed on the actuator 210.

4 to 5, the active matrix 100 includes a substrate 101 in which M × N (M and N are natural numbers) P-MOS transistors 120 and the P-MOS transistors 120. A first metal layer 135 formed on the substrate 101, a first passivation layer 140 formed on the first metal layer 135, and a first passivation layer extending from the drain 105 and the source 110. The second metal layer 145 formed on the upper portion of the 140, the second protective layer 150 formed on the second metal layer 145, and the etch stop layer 155 formed on the second protective layer 150 are disposed. Include. The first metal layer 135 includes a drain pad extending from the drain 105 of the P-MOS transistor 120 to transmit a first signal (image signal), and the second metal layer 145 includes a titanium layer and nitride. It consists of a titanium layer.

Referring to FIG. 4, the support element 175 includes a support line 174, a support layer 170, a first anchor 171, and second anchors 172a and 172b. The support line 174 and the support layer 170 are horizontally formed on the etch stop layer 155 via the first air gap 165. The common electrode line 240 is formed on the support line 174, and the support line 174 serves to support the common electrode line 240.

The support layer 170 has a rectangular ring shape, preferably a rectangular ring shape, and is integrally formed with the support line 174 in a direction orthogonal to the support line 174 on the same plane. The first anchor 171 is integrally formed with the two arms in the lower portion between the two arms horizontally extending in the direction orthogonal to the support line 174 of the square ring-shaped support layer 170 to form an etch stop layer ( 155, and two second anchors 172a and 172b are formed integrally with the two arms at an outer lower portion of the two arms and attached to the etch stop layer 155. The first anchor 171 and the second anchors 172a and 172b each have a shape of a rectangular box. The support layer 170 is supported by the first anchor 171 in the center portion and supported by both anchors 172a and 172b.

The first anchor 171 is formed on a portion of the etch stop layer 155 where the drain pad of the first metal layer 135 is located. In the central portion of the first anchor 171, the first metal layer may be formed through the etch stop layer 155, the second passivation layer 150, the holes (not shown) of the second metal layer 145, and the first passivation layer 140. The via hole 270 is formed to the drain pad of the 135.

The actuator 210 is formed on the support layer 170 in the shape of a mirror 'C' with respect to the support line 174. The actuator 210 includes a lower electrode 180, a first strained layer 190, a second strained layer 191, a first upper electrode 200, and a second upper electrode 201. The lower electrode 180 has a mirror-shaped 'c' shape spaced apart from the support line 174 by a predetermined distance, and protruding portions are stepped toward the first anchor 171 on one side of the lower electrode 180. Are formed corresponding to each other. The protrusions of the lower electrode 180 extend to the periphery of the via hole 270 formed in the first anchor 171, respectively.

The via contact 280 is formed from the drain pad of the first metal layer 135 to the protrusion of the lower electrode 180 through the via hole 280 to electrically connect the drain pad and the lower electrode 180.

The two arms of the '-' shaped lower electrode 180 each have a rectangular flat plate shape, and the first and second deformable layers 190 and 191 are respectively more than two arms of the lower electrode 180. It has a shape of a rectangular flat plate having a narrow area and is formed on the upper two arms of the lower electrode 180. In addition, the first and second upper electrodes 200 and 201 have a shape of a rectangular plate having a smaller area than the first and second deformable layers 190 and 191, respectively, and have the first and second deformed layers 190 and 191. It is formed at the top of the.

The first insulating layer 220 is formed from one side of the first upper electrode 200 to a part of the support layer 170 through the first deforming layer 190 and the lower electrode 180, and the first upper electrode 200. The first upper electrode connecting member 230 is formed from one side of the first through the first insulating layer 220 and the support layer 170 to the common electrode line 240. The first upper electrode connecting member 230 connects the first upper electrode 200 and the common electrode line 240 to each other, and the first insulating layer 220 may include the first upper electrode 200 and the lower electrode 180. It is connected to each other to prevent electrical shorts. In addition, a second insulating layer 221 is formed from one side of the second upper electrode 201 to a part of the support layer 170 through the second deformable layer 191 and the lower electrode 180. The second upper electrode connecting member 231 is formed from one side of the second upper electrode 201 to the common electrode line 240 through a portion of the second insulating layer 221 and the support layer 170. The second insulating layer 221 and the second upper electrode connecting member 231 are formed to be parallel to the first insulating layer 220 and the first upper electrode connecting member 230, respectively. The second upper electrode connecting member 231 connects the second upper electrode 201 and the common electrode line 240 to each other, and the second insulating layer 221 is formed by the second upper electrode 201 and the lower electrode 180. They are connected to each other to prevent electrical shorts.

A portion of the lower electrode 280 in which the first and second upper electrodes 200 and 201 are not formed, that is, a portion formed parallel to the support line 174, is disposed below the mirror 260 and the lower portion of the mirror 260. The post 250 supporting the hard mask 320 is formed. The mirror 260 and the hard mask 320 are centrally supported by the post 250, and both sides thereof are formed horizontally on the actuator 210 via the second air gap 310. The mirror 260 reflects light incident from a light source (not shown) at a predetermined angle so that the image is projected onto the screen.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the accompanying drawings.

6A to 6E are diagrams for describing a method of manufacturing the apparatus shown in FIGS. 4 and 5. In Figs. 6A to 6E, the same reference numerals are used for the same members as Figs. 4 and 5.

Referring to FIG. 6A, a device isolation layer 125 is formed on the substrate 101, which is an n-type doped silicon wafer, by using a silicon partial oxidation method (LOCOS). Subsequently, after forming the gate 115 made of a conductive material such as polysilicon of the active region, p ⁺ source 110 and drain 105 are formed by an ion implantation process, thereby forming M × N on the substrate 101. (M and N are natural numbers) P-MOS transistors 120 are formed.

After the insulating film 130 made of oxide is formed on the P-MOS transistor 120 formed thereon, the source 110 and the one side of the drain 105 of the transistor 120 by photolithography are respectively formed. Form openings that expose. Subsequently, after depositing the first metal layer 135 made of titanium, titanium nitride, tungsten, nitride, or the like on the resultant, the first metal layer 135 is patterned by photolithography. The patterned first metal layer 135 includes a drain pad extending from the drain 205 of the transistor 120 to the bottom of the first anchor 171 supporting the support layer 170.

A first passivation layer 140 made of an insulator glass (PSG) is stacked on the substrate 101 on which the first metal layer 135 and the transistor 120 are formed. The first protective layer 140 is formed to have a thickness of about 8000 kPa using a chemical vapor deposition (CVD) method. The first protective layer 140 prevents damage to the substrate 101 in which the P-MOS transistor 120 is embedded during a subsequent process.

A second metal layer 145 including a titanium layer and a titanium nitride layer is formed on the first protective layer 140. The titanium layer is formed to have a thickness of about 300 kW by the sputtering method, and the titanium nitride layer is formed to have a thickness of about 1200 kW by the physical vapor deposition (PVD) method on the titanium layer. Since the light incident from the light source (not shown) is incident on the second metal layer 145 not only to the mirror 260 but also to a portion other than the portion covered by the mirror 260, the light leakage current (not shown) is applied to the substrate 101. photo leakage current flows to prevent the device from malfunctioning. Subsequently, a portion of the second metal layer 145 in which the via hole 270 is to be formed in a subsequent process, that is, a portion in which the drain pad of the first metal layer 135 is formed is etched to form a hole in the second metal layer 145. (Not shown).

The second passivation layer 150 made of an insulated glass PSG is stacked on the second metal layer 145. The second protective layer 150 is formed to have a thickness of about 2000 kPa by chemical vapor deposition. The second protective layer 150 prevents the substrate 101 and the resulting products formed on the substrate 101 from being damaged during subsequent processing.

An etch stop layer 155 is stacked on the second passivation layer 150. The etch stop layer 155 prevents the second passivation layer 150 and the results on the substrate 101 from being etched and damaged during the subsequent etching process. The etch stop layer 155 is formed using low temperature oxide (LTO) such as silicon oxide (SiO ₂ ) or phosphorus pentoxide (P ₂ O ₅ ). The etch stop layer 155 is formed to have a thickness of about 0.2 to 0.8 μm at a temperature of about 350 to 450 ° C. by low pressure chemical vapor deposition (LPCVD). Accordingly, the substrate 101 having the transistor 120 embedded therein, the first metal layer 135, the first protective layer 140, the second metal layer 145, the second protective layer 150, and the etch stop layer 155 may be formed. The active matrix 100 is completed.

The first sacrificial layer 160 is stacked on the etch stop layer 155. The first sacrificial layer 160 serves to facilitate stacking of the thin films constituting the actuator 210. The first sacrificial layer 160 is formed to have a thickness of about 2.0 to 3.0 μm by using low pressure chemical vapor deposition (LPCVD) at a temperature of about 500 ° C. or less. Subsequently, the surface of the first sacrificial layer 160 is polished using a chemical mechanical polishing (CMP) method to planarize the surface of the first sacrificial layer 160 to have a thickness of about 1.1 μm.

6B is a plan view illustrating a state in which the first sacrificial layer 160 is patterned. 6A and 6B, after applying and patterning a first photoresist (not shown) on the first sacrificial layer 160, the first sacrificial layer 160 is formed using the first photoresist as a mask. The first anchor 171 supporting the support layer 170 formed later by etching a portion where the hole of the second metal layer 145 is formed below and portions adjacent to both sides to expose a portion of the etch stop layer 155. And the second anchors 172a and 172b are formed and the first photoresist is removed. Accordingly, the etch stop layer 155 is exposed in the shape of three squares spaced apart by a predetermined distance.

Referring to FIG. 6C, the first layer 169 is stacked on the exposed etch stop layer 155 and on the first sacrificial layer 160. The first layer 169 is formed to have a thickness of about 0.1 to 1.0 μm of a hard material such as nitride or metal by low pressure chemical vapor deposition (LPCVD). The first layer 169 is later patterned with a support element 275 that includes a support layer 170, a support line 174, and anchors 171, 172a, 172b.

The lower electrode layer 179 is stacked on top of the first layer 169. The lower electrode layer 179 is formed of a metal having electrical conductivity such as platinum, tantalum or platinum-tantalum to have a thickness of about 0.1 to 1.0 μm using a sputtering method or a chemical vapor deposition method. The lower electrode layer 179 is later applied with a first signal (image signal) from outside, and patterned as a mirror-shaped 'c' shaped lower electrode 180 having stepped protrusions formed on one side thereof.

The second layer 189 is formed on the lower electrode layer 179 by using a piezoelectric material such as PZT or PLZT. Preferably, the second layer 189 is formed by spin coating PZT prepared by the sol-gel method to have a thickness of about 0.4 μm. Subsequently, the piezoelectric material constituting the second layer 189 is subjected to heat treatment by a rapid thermal treatment (RTA) method to cause phase shift. The second layer 189 may be formed by the first strained layer 190 and the second upper electrode 201 and the lower portion which are deformed by a first electric field generated between the first upper electrode 200 and the lower electrode 180. It is patterned into a second strained layer 191 causing strain by a second electric field generated between the electrodes 180.

The upper electrode layer 199 is stacked on top of the second layer 189. The upper electrode layer 199 is formed of a metal having electrical conductivity such as platinum, tantalum, silver, or platinum-tantalum to have a thickness of about 0.1 to 1.0 μm using a sputtering method or a chemical vapor deposition method. The upper electrode layer 199 is later patterned with a first upper electrode 200 and a second upper electrode 201, each of which is applied with a second signal (bias signal) and spaced apart by a predetermined distance.

Referring to FIG. 6D, after applying and patterning a second photoresist (not shown) on the upper electrode layer 199, each of the upper electrode layers 199 may be formed using a second photoresist as a mask. The first upper electrode 200 and the second upper electrode 201 are formed in a shape, preferably, a rectangular flat plate and spaced apart from each other by a predetermined distance, and then the second photoresist is removed. The second signal is applied to the first and second upper electrodes 200 and 201 through the common electrode line 240 formed later from the outside, respectively.

Subsequently, the second deforming layer 190 is patterned in the same manner as the method of patterning the upper electrode layer 199, each having a shape of a rectangular flat plate, and separated from each other by a predetermined distance to form the first strained layer 190. And a second strained layer 191. In this case, as shown in FIG. 4, the first and second deformable layers 190 and 191 are patterned to have a rectangular flat plate having a slightly larger area than the first and second upper electrodes 300 and 301, respectively.

Subsequently, the lower electrode layer 179 has a mirror-shaped 'c' shape with respect to the support line 174 formed later, and has a lower electrode 180 having protrusions formed in a step toward the first anchor 171. To form. In this case, the two arms of the lower electrode 180 are formed to have the shape of a rectangular plate having a larger area than the first and second deformable layers 190 and 191, respectively. In addition, when the lower electrode layer 179 is patterned, the common electrode line 240 is formed simultaneously with the lower electrode 180 in a direction perpendicular to the lower electrode 180 on one side of the first layer 169. The common electrode line 240 is formed to be spaced apart from the lower electrode 180 by a predetermined distance on the support line 174 formed later. Accordingly, the actuator 210 including the first and second upper electrodes 200 and 201, the first and second strained layers 190 and 191, and the lower electrode 180 is completed.

Subsequently, the first layer 169 is patterned to form a support element 175 comprising a support layer 170, a support line 174, a first anchor 171 and second anchors 172a and 172b. . At this time, of the portions of the first layer 169 contacting the etch stop layer 155 exposed in the shape of the three quadrangles, both sides are the second anchors 172a and 172b, and the center portion is the first anchor ( 171). Each of the first anchor 171 and the second anchors 172a and 172b has a rectangular box shape, and a hole of the second metal layer 145 and a hole of the first metal layer 135 are disposed below the first anchor 171. The drain pad is located. The first and second deformable layers 190 and 191 are formed parallel to each other on two arms horizontally extending in a direction orthogonal to the support line 174 of the support layer 170, respectively. Accordingly, the first anchor 171 is formed below the mirror-shaped 'c' shaped lower electrode 180, and the second anchors 172a and 172b are formed below the outer electrode 180, respectively. do.

Subsequently, a third photoresist (not shown) is applied and patterned on top of the support element 175 and the actuator 210 to form the first and second upper portions from the common electrode line 240 formed on the support line 274. Portions of the electrodes 200 and 201 are exposed. At this time, the protrusions of the lower electrode 180 are also exposed together from the first anchor 171.

Subsequently, by depositing and patterning a low temperature oxide such as amorphous silicon or silicon oxide to phosphorus pentoxide on the exposed portion, a portion of the first upper electrode 200 is formed through the first strained layer 190 and the lower electrode 180. The first insulating layer 220 is formed to a part of the support layer 170, and at the same time, a part of the support layer 170 is formed from the part of the second upper electrode 201 through the second strained layer 191 and the lower electrode 180. Until the second insulating layer 221 is formed. The first and second insulating layers 220 and 221 are formed to have a thickness of about 0.2 to 0.4 μm, respectively, by low pressure chemical vapor deposition (LPCVD).

Next, the first anchor 171, the etch stop layer 155, and the etch stop layer 155 are formed from an upper portion of the center of the first anchor 171, which is a portion where the hole of the second metal layer 145 and the drain pad of the first metal layer 135 are formed. A portion of the second passivation layer 150 and the first passivation layer 140 is etched to form the via hole 270 up to the drain pad of the first metal layer 135, and then the lower electrode from the drain pad through the via hole 270. The via contact 280 is formed up to the protrusions of 180 (see FIG. 4). At the same time, the first upper electrode connecting member 230 is formed from the first upper electrode 200 to the common electrode line 240 through a portion of the first insulating layer 220 and the support layer 170, and the second upper electrode The second upper electrode connecting member 231 is formed from the 201 to the common electrode line 240 through a portion of the second insulating layer 221 and the support layer 170.

The via contact 280, the first and second upper electrode connection members 230 and 231 may each have a thickness of about 0.1 to 0.2 μm by sputtering or chemical vapor deposition using platinum, tantalum or platinum-tantalum. After deposition to have, the deposited metal is formed by patterning. The first and second upper electrode connecting members 230 and 231 connect the first and second upper electrodes 200 and 201 and the common electrode line 240, respectively, and the lower electrode 180 connects the via contact 280. It is connected to the drain pad of the first metal layer 135 through.

Referring to FIG. 6E, Accuflo, which has excellent deposition flatness on top of the actuator 210 and the support element 175, has a sufficient height to completely cover the actuator 210 using a spin coating method. The second sacrificial layer 300 is formed. Since the accucu has a property of being flattened at the same time as the application, when the second sacrificial layer 300 is formed using the accucu, a separate process for planarizing the surface of the second sacrificial layer 300 is not added. Accucu can be applied by spin coating and removed by plasma ashing, similar to photoresist.

Subsequently, after the fourth photoresist 310 is coated on the second sacrificial layer 300, the hard mask 320 is formed on the upper portion of the second sacrificial layer 300 to have a thickness of about 3000 Pa by sputtering. At this time, the hard mask 320 is formed by depositing aluminum in an operating pressure of about 2.3 mTorr, about 5 kW of power, and a flow rate of argon gas, which is a deposition medium, about 110 sccm.

Subsequently, after the hard mask 320 is patterned by a photolithography method, the fourth photoresist 310 and the second sacrificial layer 300 are patterned using the patterned hard mask 320 as an etching mask. As a result, a portion of the lower electrode 180 having a mirror-shaped 'c' shape parallel to the support line 174 (the first and second upper electrodes 200 and 201 are not formed thereon). Part).

Next, aluminum (Al), which is the same metal as the hard mask 320, is deposited on a portion of the exposed lower electrode 180 and on the patterned hard mask 320 by using a sputtering method or a chemical vapor deposition method. The deposited aluminum is patterned to simultaneously form a mirror 260 having a rectangular flat plate shape and a post 250 supporting the mirror 260.

Subsequently, the second sacrificial layer 300 and the fourth photoresist 310 are removed by a plasma ashing method, and the first sacrificial layer 160 is formed using xenon fluoride (XeF ₂ ) or bromine fluoride (BrF ₂ ). ) Is removed, followed by washing and drying to complete the AMA device as shown in FIG. 4. As such, when the second sacrificial layer 300 is removed, the second air gap 310 is formed at the position of the second sacrificial layer 300, and when the first sacrificial layer 160 is removed, the first sacrificial layer 160 is removed. The first air gap 165 is formed at the position.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal transmitted from the outside is the MOS transistor 120 embedded in the active matrix 100, the drain pad and the via contact 280 of the first metal layer 135. Is applied to the lower electrode 180, and at the same time, a second signal is applied to the first and second upper electrodes 200 and 201 through the common electrode line 240 from the outside, respectively, and thus, the first upper electrode 200 is applied. The first electric field is generated between the and the lower electrode 180 according to the potential difference, and the second electric field is generated between the second upper electrode 201 and the lower electrode 180 according to the potential difference. The first strained layer 190 formed between the first upper electrode 200 and the lower electrode 180 causes deformation by the first electric field, and simultaneously the second upper electrode 201 and the lower part by the second electric field. The second strained layer 191 formed between the electrodes 180 causes deformation.

As the first and second deformable layers 190 and 191 contract in a direction orthogonal to the first and second electric fields, respectively, the actuator 210 including the first and second deformable layers 190 and 191 is predetermined. Bend at the angle of. The mirror 260 reflecting light incident from the light source is inclined together with the actuator 210 because the mirror 260 is supported by the post 250 and is formed on the actuator 210. Accordingly, the mirror 260 reflects incident light at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after forming a photoresist and a hard mask on the second sacrificial layer, the second sacrificial layer is patterned and a mirror is formed on the hard mask. Thus, since the second sacrificial layer is accurately patterned and the hard mask compensates for the stress generated during the deposition of the mirror, the horizontality of the mirror formed on the hard mask can be improved. In addition, since the hard mask is formed using the same metal as the mirror, the hard mask may serve as a seed layer for depositing the mirror layer, thereby easily forming the mirror, and the second sacrificial layer and Out gasing, which occurs when removing the photoresist, can prevent the edge portion of the mirror from bending. Accordingly, the light efficiency of the light incident on the mirror from the light source can be increased to improve the image quality of the image projected on the screen.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be modified in various ways without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (2)

Providing an active matrix including a first metal layer having a MOS transistor embedded therein and having a drain pad extending from the drain of the transistor; Forming a first sacrificial layer on the active matrix, and then patterning the first sacrificial layer to expose portions of the active matrix in which the drain pads of the first metal layer are formed and both sides of the portions in which the drain pads are formed; ; Forming a first layer, a lower electrode layer, a second layer, and an upper electrode layer on the exposed active matrix and the first sacrificial layer; Patterning the upper electrode layer, the second layer, and the lower electrode to form an actuator including first and second upper electrodes, first and second strained layers, and a lower electrode; Patterning the first layer to form a support line formed on the active matrix, a support layer integrally formed with the support line, and a portion where the drain pad of the first metal layer is formed below the portion adjacent to the support line among the support layers and the drain Forming supporting means including first and second anchors, the first anchors and the second anchors respectively contacting the active matrixes at both sides of the pad-formed portion; Forming a second sacrificial layer on top of the support means and the actuator; Forming a photoresist and a hard mask on the second sacrificial layer; After patterning the hard mask, etching the photoresist and the second sacrificial layer using the patterned hard mask; And Method of manufacturing a thin film type optical path control device comprising the step of forming a mirror on top of the hard mask. The method of claim 1, wherein the forming of the hard mask is performed under deposition conditions in which a power of about 5 kW, an operating pressure of about 2.3 mTorr, and a flow rate of argon gas, which is a deposition medium, are about 110 sccm. Method of manufacturing the device.