KR102240408B9 - 반도체 패키지 - Google Patents

반도체 패키지

Info

Publication number
KR102240408B9
KR102240408B9 KR1020190045644A KR20190045644A KR102240408B9 KR 102240408 B9 KR102240408 B9 KR 102240408B9 KR 1020190045644 A KR1020190045644 A KR 1020190045644A KR 20190045644 A KR20190045644 A KR 20190045644A KR 102240408 B9 KR102240408 B9 KR 102240408B9
Authority
KR
South Korea
Prior art keywords
semiconductor package
package
semiconductor
Prior art date
Application number
KR1020190045644A
Other languages
English (en)
Other versions
KR102240408B1 (ko
KR20200079160A (ko
Inventor
정기조
조창용
오정식
이영모
김종헌
Original Assignee
주식회사 네패스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to US16/724,889 priority Critical patent/US11276632B2/en
Priority to CN201911338310.3A priority patent/CN111354700A/zh
Priority to TW108147467A priority patent/TWI788614B/zh
Publication of KR20200079160A publication Critical patent/KR20200079160A/ko
Application granted granted Critical
Publication of KR102240408B1 publication Critical patent/KR102240408B1/ko
Publication of KR102240408B9 publication Critical patent/KR102240408B9/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020190045644A 2018-12-24 2019-04-18 반도체 패키지 KR102240408B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US16/724,889 US11276632B2 (en) 2018-12-24 2019-12-23 Semiconductor package
CN201911338310.3A CN111354700A (zh) 2018-12-24 2019-12-23 半导体封装件
TW108147467A TWI788614B (zh) 2018-12-24 2019-12-24 半導體封裝件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020180168468 2018-12-24
KR1020180168468 2018-12-24

Publications (3)

Publication Number Publication Date
KR20200079160A KR20200079160A (ko) 2020-07-02
KR102240408B1 KR102240408B1 (ko) 2021-04-15
KR102240408B9 true KR102240408B9 (ko) 2021-12-07

Family

ID=71599355

Family Applications (4)

Application Number Title Priority Date Filing Date
KR1020190038610A KR102240409B1 (ko) 2018-12-24 2019-04-02 반도체 패키지 및 그 제조 방법
KR1020190045644A KR102240408B1 (ko) 2018-12-24 2019-04-18 반도체 패키지
KR1020190068803A KR102317208B1 (ko) 2018-12-24 2019-06-11 반도체 패키지 및 그의 제조 방법
KR1020210034854A KR102283061B1 (ko) 2018-12-24 2021-03-17 반도체 패키지 및 그 제조 방법

Family Applications Before (1)

Application Number Title Priority Date Filing Date
KR1020190038610A KR102240409B1 (ko) 2018-12-24 2019-04-02 반도체 패키지 및 그 제조 방법

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020190068803A KR102317208B1 (ko) 2018-12-24 2019-06-11 반도체 패키지 및 그의 제조 방법
KR1020210034854A KR102283061B1 (ko) 2018-12-24 2021-03-17 반도체 패키지 및 그 제조 방법

Country Status (1)

Country Link
KR (4) KR102240409B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102570496B1 (ko) * 2021-04-27 2023-08-24 주식회사 네패스 반도체 패키지 제조방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3400263B2 (ja) * 1996-09-19 2003-04-28 株式会社東芝 半導体装置、回路配線基板及び半導体装置実装構造体
JP3339384B2 (ja) * 1997-07-14 2002-10-28 イビデン株式会社 半田材料並びにプリント配線板及びその製造方法
JP4327656B2 (ja) * 2004-05-20 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2008016514A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP4597940B2 (ja) * 2006-10-26 2010-12-15 富士通セミコンダクター株式会社 外部接続端子
JP2013030498A (ja) * 2009-11-12 2013-02-07 Panasonic Corp 半導体装置
JP2012114148A (ja) * 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
KR102005350B1 (ko) * 2017-01-03 2019-07-31 삼성전자주식회사 팬-아웃 반도체 패키지

Also Published As

Publication number Publication date
KR20200079164A (ko) 2020-07-02
KR102240408B1 (ko) 2021-04-15
KR20200079160A (ko) 2020-07-02
KR102317208B9 (ko) 2021-12-07
KR102240409B1 (ko) 2021-04-15
KR102283061B1 (ko) 2021-07-28
KR20210035123A (ko) 2021-03-31
KR102317208B1 (ko) 2021-10-25
KR20200079158A (ko) 2020-07-02

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E701 Decision to grant or registration of patent right
G170 Publication of correction