KR102153413B9 - 반도체 패키지 - Google Patents

반도체 패키지

Info

Publication number
KR102153413B9
KR102153413B9 KR1020190038611A KR20190038611A KR102153413B9 KR 102153413 B9 KR102153413 B9 KR 102153413B9 KR 1020190038611 A KR1020190038611 A KR 1020190038611A KR 20190038611 A KR20190038611 A KR 20190038611A KR 102153413 B9 KR102153413 B9 KR 102153413B9
Authority
KR
South Korea
Prior art keywords
semiconductor package
package
semiconductor
Prior art date
Application number
KR1020190038611A
Other languages
English (en)
Other versions
KR102153413B1 (ko
KR20200079159A (ko
Inventor
조창용
한종호
정기조
김종헌
Original Assignee
주식회사 네패스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to KR1020190038611A priority Critical patent/KR102153413B1/ko
Priority to CN201911338310.3A priority patent/CN111354700A/zh
Priority to US16/724,889 priority patent/US11276632B2/en
Priority to TW108147467A priority patent/TWI788614B/zh
Publication of KR20200079159A publication Critical patent/KR20200079159A/ko
Application granted granted Critical
Publication of KR102153413B1 publication Critical patent/KR102153413B1/ko
Publication of KR102153413B9 publication Critical patent/KR102153413B9/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
KR1020190038611A 2018-12-24 2019-04-02 반도체 패키지 KR102153413B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020190038611A KR102153413B1 (ko) 2018-12-24 2019-04-02 반도체 패키지
CN201911338310.3A CN111354700A (zh) 2018-12-24 2019-12-23 半导体封装件
US16/724,889 US11276632B2 (en) 2018-12-24 2019-12-23 Semiconductor package
TW108147467A TWI788614B (zh) 2018-12-24 2019-12-24 半導體封裝件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020180168468 2018-12-24
KR1020190038611A KR102153413B1 (ko) 2018-12-24 2019-04-02 반도체 패키지

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020180168468 Division 2018-12-24 2018-12-24

Publications (3)

Publication Number Publication Date
KR20200079159A KR20200079159A (ko) 2020-07-02
KR102153413B1 KR102153413B1 (ko) 2020-09-08
KR102153413B9 true KR102153413B9 (ko) 2021-12-07

Family

ID=73004839

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020190038611A KR102153413B1 (ko) 2018-12-24 2019-04-02 반도체 패키지

Country Status (2)

Country Link
KR (1) KR102153413B1 (ko)
TW (1) TWI788614B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112466838A (zh) * 2020-10-13 2021-03-09 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
KR102570496B1 (ko) * 2021-04-27 2023-08-24 주식회사 네패스 반도체 패키지 제조방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4327656B2 (ja) * 2004-05-20 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2008016514A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2011165862A (ja) * 2010-02-09 2011-08-25 Sony Corp 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法
TWM397597U (en) * 2010-04-15 2011-02-01 Di-Quan Hu Package structure of integrated circuit
US20120098124A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having under-bump metallization (ubm) structure and method of forming the same
US20150147881A1 (en) * 2013-11-25 2015-05-28 Texas Instruments Incorporated Passivation ash/oxidation of bare copper
US20170179058A1 (en) * 2015-12-16 2017-06-22 Lite-On Semiconductor Corporation Bump structure having first portion of copper and second portion of pure tin covering the first portion, and interconnect structure using the same

Also Published As

Publication number Publication date
KR102153413B1 (ko) 2020-09-08
TWI788614B (zh) 2023-01-01
TW202025403A (zh) 2020-07-01
KR20200079159A (ko) 2020-07-02

Similar Documents

Publication Publication Date Title
SG10201905158TA (en) Semiconductor package
SG10201905587SA (en) Semiconductor package
ZAA201801488S (en) Packages
SG10201907662SA (en) Semiconductor package
SG10202001607VA (en) Semiconductor device
EP3534413A4 (en) SEMICONDUCTOR DEVICE HOUSING
SG10201905606YA (en) Semiconductor device
EP3474327A4 (en) SEMICONDUCTOR CHIP HOUSING
SG10201906230PA (en) Semiconductor Package
SG10201907297YA (en) Semiconductor Package
SG10201902032WA (en) Semiconductor Package
SG10201905607UA (en) Semiconductor device
ZAA201801502S (en) Packages
SG10201907599PA (en) Semiconductor package
SG10202003704XA (en) Semiconductor Devices
GB201814693D0 (en) Semiconductor devices
SG10201906019QA (en) Semiconductor Device
CA194973S (en) Package
SG10202003905SA (en) Semiconductor device
KR102304963B9 (ko) 반도체 패키지
SI3216722T1 (sl) Embalaža za pomivalno korito
GB2587854B (en) Semiconductor devices
SG10202007931RA (en) Semiconductor device
SG10202006114WA (en) Semiconductor device
KR102153413B9 (ko) 반도체 패키지

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
G170 Re-publication after modification of scope of protection [patent]