US20150147881A1 - Passivation ash/oxidation of bare copper - Google Patents

Passivation ash/oxidation of bare copper Download PDF

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Publication number
US20150147881A1
US20150147881A1 US14/552,925 US201414552925A US2015147881A1 US 20150147881 A1 US20150147881 A1 US 20150147881A1 US 201414552925 A US201414552925 A US 201414552925A US 2015147881 A1 US2015147881 A1 US 2015147881A1
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Prior art keywords
copper oxide
copper
semiconductor wafer
integrated circuit
forming
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US14/552,925
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Jennifer Jean McComb
Richard A. Faust
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US14/552,925 priority Critical patent/US20150147881A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAUST, RICHARD A., MCCOMB, JENNIFER JEAN
Publication of US20150147881A1 publication Critical patent/US20150147881A1/en
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms

Definitions

  • the invention is generally related to the field of fabricating integrated circuits and more specifically to a passivation ash of exposed copper at a surface of an integrated circuit.
  • the fabrication of integrated circuits often involves semiconductor device and interconnect fabrication on a wafer scale at one site (a semiconductor fab) and packaging of individual die at another site (assembly/test site).
  • an aluminum capping layer is used as the top metal of the wafer. The surface of the aluminum capping layer remains stable when shipping the wafers from the fab to the assembly/test site.
  • a semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged storage) is expected.
  • An advantage of the invention is preventing corrosion of the exposed Cu surface.
  • FIG. 1 is a cross-sectional diagram of a semiconductor wafer having a clean, high quality Cu oxide according to an embodiment
  • FIG. 2 is a flow diagram of a method according to an embodiment.
  • Integrated circuit die are fabricated on a semiconductor wafer.
  • Cu metallization is used, Cu is exposed at the surface at various points in the process. When Cu is exposed for extended periods of time, natural oxidation of the Cu occurs.
  • this native Cu oxide is of poor quality and is non-uniform.
  • other contaminants can collect on the Cu surface for example from poor air quality, outgassing from shipping container plastics, etc. The non-uniform native Cu oxide and other contaminants can result in corrosion and yield loss as well as poor adhesion and poor ohmic connections in subsequent processing/assembly/test.
  • An embodiment will now be described in conjunction with an integrated circuit fabrication process.
  • the embodiment may be applied to other integrated circuit fabrication processes involving Cu that may be exposed for an extended time such as Cu bond pads or Cu interconnect lines.
  • an integrated circuit 100 is formed using a semiconductor wafer 102 .
  • Transistors and other devices as well as various metal interconnect levels are formed on wafer 102 .
  • a Cu interconnect structure 106 is formed, for example using a damascene process, over the underlying structures 104 .
  • a protective overcoat 110 is formed over the Cu 106 .
  • Vias are formed in the protective overcoat and filled with Cu, forming Cu vias 112 .
  • FIG. 1 shows Cu surface 113 as being the surface of Cu vias extending through a protective overcoat 110 , Cu surface 112 could be any Cu surface that may be exposed for an extended period of time.
  • a clean, high quality Cu oxide 114 is formed on the Cu surface 113 .
  • an O 2 ash may be performed. An O 2 ash will burn off any contaminants already on the Cu surface and allow a pure Cu oxide 114 to form.
  • the Cu oxide may be in the range of 20-100 ⁇ thick.
  • Cu oxide 114 differs from a natively grown oxide in that it is cleaner (contains less contaminants) and more uniform.
  • Cu oxide 114 protects the Cu surface 113 for the extended period of time until subsequent fabrication steps are performed (extended non-fabrication process time).
  • Cu oxide 114 may protect the Cu surface 113 during shipment from a wafer fabrication facility to an assembly/test facility.
  • the extended non-fabrication process time may be a time in which the processed wafers are placed in storage.
  • the Cu oxide 114 may be removed prior to further processing steps such as packaging.
  • Cu oxide 114 may be removed using an H 2 -based plasma.
  • Sulfuric acid or citric acid cleans may also be used.
  • Other acids with low etch rate of Cu and the surrounding dielectrics could alternatively be used.
  • diluted HF could be used to remove the Cu oxide and not attack the PO too much. Further processing/assembly/test is then undertaken.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged storage) is expected.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of priority under U.S.C. §119(e) of U.S. Provisional Application 61/908,283 (Texas Instruments docket number TI-72691 PS, filed Nov. 25, 2013), hereby incorporated by reference.
    • FIELD OF THE INVENTION
  • The invention is generally related to the field of fabricating integrated circuits and more specifically to a passivation ash of exposed copper at a surface of an integrated circuit.
    • BACKGROUND OF THE INVENTION
  • The fabrication of integrated circuits often involves semiconductor device and interconnect fabrication on a wafer scale at one site (a semiconductor fab) and packaging of individual die at another site (assembly/test site). Conventionally, an aluminum capping layer is used as the top metal of the wafer. The surface of the aluminum capping layer remains stable when shipping the wafers from the fab to the assembly/test site.
    • SUMMARY OF THE INVENTION
  • It is desirable to ship wafers having exposed Cu on the surface to assembly/test sites. In accordance with an embodiment of the application, a semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged storage) is expected.
  • An advantage of the invention is preventing corrosion of the exposed Cu surface.
  • This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the drawings:
  • FIG. 1 is a cross-sectional diagram of a semiconductor wafer having a clean, high quality Cu oxide according to an embodiment; and
  • FIG. 2 is a flow diagram of a method according to an embodiment.
    •  DETAILED DESCRIPTION OF THE EMBODIMENTS
  • Integrated circuit die are fabricated on a semiconductor wafer. When Cu metallization is used, Cu is exposed at the surface at various points in the process. When Cu is exposed for extended periods of time, natural oxidation of the Cu occurs. Unfortunately, this native Cu oxide is of poor quality and is non-uniform. In addition, other contaminants can collect on the Cu surface for example from poor air quality, outgassing from shipping container plastics, etc. The non-uniform native Cu oxide and other contaminants can result in corrosion and yield loss as well as poor adhesion and poor ohmic connections in subsequent processing/assembly/test.
  • An embodiment will now be described in conjunction with an integrated circuit fabrication process. The embodiment may be applied to other integrated circuit fabrication processes involving Cu that may be exposed for an extended time such as Cu bond pads or Cu interconnect lines.
  • Referring to FIGS. 1 and 2, an integrated circuit 100 is formed using a semiconductor wafer 102. Transistors and other devices as well as various metal interconnect levels (shown collectively as 104) are formed on wafer 102. A Cu interconnect structure 106 is formed, for example using a damascene process, over the underlying structures 104. A protective overcoat 110 is formed over the Cu 106. Vias are formed in the protective overcoat and filled with Cu, forming Cu vias 112. Although FIG. 1 shows Cu surface 113 as being the surface of Cu vias extending through a protective overcoat 110, Cu surface 112 could be any Cu surface that may be exposed for an extended period of time.
  • If the Cu surface 113 would otherwise be exposed for an extended time (e.g., greater than 1 day), a clean, high quality Cu oxide 114 is formed on the Cu surface 113. For example, an O2 ash may be performed. An O2 ash will burn off any contaminants already on the Cu surface and allow a pure Cu oxide 114 to form. The Cu oxide may be in the range of 20-100 Å thick. Cu oxide 114 differs from a natively grown oxide in that it is cleaner (contains less contaminants) and more uniform.
  • Cu oxide 114 protects the Cu surface 113 for the extended period of time until subsequent fabrication steps are performed (extended non-fabrication process time). For example, Cu oxide 114 may protect the Cu surface 113 during shipment from a wafer fabrication facility to an assembly/test facility. Alternatively, the extended non-fabrication process time may be a time in which the processed wafers are placed in storage.
  • After the extended non-fabrication process time, the Cu oxide 114 may be removed prior to further processing steps such as packaging. Cu oxide 114 may be removed using an H2-based plasma. Sulfuric acid or citric acid cleans may also be used. Other acids with low etch rate of Cu and the surrounding dielectrics could alternatively be used. Alternatively, diluted HF could be used to remove the Cu oxide and not attack the PO too much. Further processing/assembly/test is then undertaken.
  • While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims (14)

1. A method of fabricating an integrated circuit, comprising the steps of:
processing a semiconductor wafer through the formation of a protective overcoat at a wafer fabrication facility;
forming copper vias through the protective overcoat;
forming a copper oxide on a surface of the copper vias, wherein the cooper oxide is a clean, high quality copper oxide;
shipping the semiconductor wafer from the wafer fabrication facility to an assembly/test facility;
removing the copper oxide at the assembly/test facility; and
packaging the integrated circuit.
2. The method of claim 1, wherein forming the copper oxide comprises a performing an O2 ash.
3. The method of claim 2, wherein the copper oxide is in the range of 20 ÅA-100 Å thick.
4. The method of claim 2, wherein the step of removing the copper oxide comprises an H2 plasma.
5. The method of claim 2, wherein the step of removing the copper oxide comprises exposing the copper oxide to sulfuric acid.
6. The method of claim 2, wherein the step of removing the copper oxide comprises exposing the copper oxide to citric acid.
7. A method of fabricating an integrated circuit, comprising the steps of:
processing a semiconductor wafer through the formation of at least one copper interconnect level such that the semiconductor wafer has a copper surface exposed;
forming a clean, high quality copper oxide on the copper surface;
performing no process steps on the semiconductor wafer for an extended period of time;
then, removing the copper oxide; and
then, packaging the integrated circuit.
8. The method of claim 7, wherein forming the copper oxide comprises a performing an O2 ash.
9. The method of claim 8, wherein the extended period of time is greater than one day.
10. The method of claim 8, wherein the step of performing no process steps comprises shipping the semiconductor wafer from a wafer fabrication facility to an assembly/test facility.
11. The method of claim 8, wherein the step of performing no process steps comprises placing the semiconductor wafer in storage.
12. The method of claim 8, wherein the step of removing the copper oxide comprises an H2 plasma.
13. The method of claim 8, wherein the step of removing the copper oxide comprises exposing the copper oxide to sulfuric acid.
14. The method of claim 8, wherein the step of removing the copper oxide comprises exposing the copper oxide to citric acid.
US14/552,925 2013-11-25 2014-11-25 Passivation ash/oxidation of bare copper Abandoned US20150147881A1 (en)

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US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
US11276632B2 (en) 2018-12-24 2022-03-15 Nepes Co., Ltd. Semiconductor package
KR102153413B1 (en) * 2018-12-24 2020-09-08 주식회사 네패스 Semiconductor package

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US20080079102A1 (en) * 2006-09-28 2008-04-03 Powerchip Semiconductor Corp. Image sensor structure and method of fabricating the same

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US20090108443A1 (en) * 2007-10-30 2009-04-30 Monolithic Power Systems, Inc. Flip-Chip Interconnect Structure
DE102007063268A1 (en) * 2007-12-31 2009-07-09 Advanced Micro Devices, Inc., Sunnyvale Wire bond with aluminum-free metallization layers through surface conditioning
US7915741B2 (en) 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure
US8580672B2 (en) * 2011-10-25 2013-11-12 Globalfoundries Inc. Methods of forming bump structures that include a protection layer
US8970035B2 (en) * 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package

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US20080079102A1 (en) * 2006-09-28 2008-04-03 Powerchip Semiconductor Corp. Image sensor structure and method of fabricating the same

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