KR102026506B1 - 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 - Google Patents

다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 Download PDF

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KR102026506B1
KR102026506B1 KR1020157020111A KR20157020111A KR102026506B1 KR 102026506 B1 KR102026506 B1 KR 102026506B1 KR 1020157020111 A KR1020157020111 A KR 1020157020111A KR 20157020111 A KR20157020111 A KR 20157020111A KR 102026506 B1 KR102026506 B1 KR 102026506B1
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single crystal
front surface
crystal silicon
silicon substrate
wafer
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Korean (ko)
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KR20150099847A (ko
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제프리 루이스 리버트
마이클 제이. 리에스
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글로벌웨이퍼스 씨오., 엘티디.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Recrystallisation Techniques (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
KR1020157020111A 2012-12-28 2013-12-23 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 Active KR102026506B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261746822P 2012-12-28 2012-12-28
US61/746,822 2012-12-28
PCT/US2013/077491 WO2014105828A1 (en) 2012-12-28 2013-12-23 Method for low temperature layer transfer in the preparation of multilayer semiconductor devices

Publications (2)

Publication Number Publication Date
KR20150099847A KR20150099847A (ko) 2015-09-01
KR102026506B1 true KR102026506B1 (ko) 2019-09-27

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KR1020157020111A Active KR102026506B1 (ko) 2012-12-28 2013-12-23 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법

Country Status (6)

Country Link
US (1) US9281233B2 (enExample)
JP (2) JP2016508291A (enExample)
KR (1) KR102026506B1 (enExample)
DE (1) DE112013006244B4 (enExample)
TW (1) TWI603387B (enExample)
WO (1) WO2014105828A1 (enExample)

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Publication number Priority date Publication date Assignee Title
DE102015210384A1 (de) * 2015-06-05 2016-12-08 Soitec Verfahren zur mechanischen Trennung für eine Doppelschichtübertragung
JP6632462B2 (ja) * 2016-04-28 2020-01-22 信越化学工業株式会社 複合ウェーハの製造方法
JP7123182B2 (ja) * 2018-06-08 2022-08-22 グローバルウェーハズ カンパニー リミテッド シリコン箔層の移転方法
CN110739217B (zh) * 2019-10-28 2025-10-10 沈阳硅基科技有限公司 一种降低soi硅片应力的制备方法
PL445432A1 (pl) * 2023-06-30 2025-01-07 Sieć Badawcza Łukasiewicz - Instytut Mikroelektroniki I Fotoniki Sposób modyfikacji podłoża z monokrystalicznego SiC, zmodyfikowane podłoże, urządzenie zawierające takie podłoże i zastosowanie takiego urządzenia

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010278342A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd Ｓｏｉ基板の製造方法

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Publication number Priority date Publication date Assignee Title
JP2617798B2 (ja) * 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2774511B1 (fr) * 1998-01-30 2002-10-11 Commissariat Energie Atomique Substrat compliant en particulier pour un depot par hetero-epitaxie
JP3456521B2 (ja) * 1998-05-12 2003-10-14 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
FR2797347B1 (fr) * 1999-08-04 2001-11-23 Commissariat Energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragililisation
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
KR100511656B1 (ko) * 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
FR2847075B1 (fr) 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
US20060240275A1 (en) * 2005-04-25 2006-10-26 Gadkaree Kishor P Flexible display substrates
FR2898431B1 (fr) 2006-03-13 2008-07-25 Soitec Silicon On Insulator Procede de fabrication de film mince
FR2914110B1 (fr) * 2007-03-20 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat hybride
US7575988B2 (en) * 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法
US7795111B2 (en) * 2007-06-27 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
JP4631946B2 (ja) * 2008-08-11 2011-02-16 住友電気工業株式会社 Ｉｉｉ族窒化物半導体層貼り合わせ基板の製造方法
US9257328B2 (en) 2008-11-26 2016-02-09 Corning Incorporated Glass-ceramic-based semiconductor-on-insulator structures and method for making the same
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010278342A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd Ｓｏｉ基板の製造方法

Also Published As

Publication number Publication date
KR20150099847A (ko) 2015-09-01
DE112013006244B4 (de) 2020-03-05
TWI603387B (zh) 2017-10-21
US9281233B2 (en) 2016-03-08
WO2014105828A1 (en) 2014-07-03
TW201435991A (zh) 2014-09-16
DE112013006244T5 (de) 2015-10-08
JP2016508291A (ja) 2016-03-17
JP2018085536A (ja) 2018-05-31
US20140187020A1 (en) 2014-07-03

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