KR102019353B1 - 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈 - Google Patents

팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈 Download PDF

Info

Publication number
KR102019353B1
KR102019353B1 KR1020170091475A KR20170091475A KR102019353B1 KR 102019353 B1 KR102019353 B1 KR 102019353B1 KR 1020170091475 A KR1020170091475 A KR 1020170091475A KR 20170091475 A KR20170091475 A KR 20170091475A KR 102019353 B1 KR102019353 B1 KR 102019353B1
Authority
KR
South Korea
Prior art keywords
fan
disposed
image sensor
package
layer
Prior art date
Application number
KR1020170091475A
Other languages
English (en)
Korean (ko)
Other versions
KR20180113885A (ko
Inventor
백용호
조정현
김민근
허영식
한태희
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to US15/828,993 priority Critical patent/US10644046B2/en
Priority to TW106143769A priority patent/TWI670841B/zh
Publication of KR20180113885A publication Critical patent/KR20180113885A/ko
Application granted granted Critical
Publication of KR102019353B1 publication Critical patent/KR102019353B1/ko
Priority to US16/844,717 priority patent/US11037971B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
KR1020170091475A 2017-04-07 2017-07-19 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈 KR102019353B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/828,993 US10644046B2 (en) 2017-04-07 2017-12-01 Fan-out sensor package and optical fingerprint sensor module including the same
TW106143769A TWI670841B (zh) 2017-04-07 2017-12-13 扇出型感測器封裝以及包含該封裝的光學指紋感測器模組
US16/844,717 US11037971B2 (en) 2017-04-07 2020-04-09 Fan-out sensor package and optical fingerprint sensor module including the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20170045502 2017-04-07
KR1020170045502 2017-04-07

Publications (2)

Publication Number Publication Date
KR20180113885A KR20180113885A (ko) 2018-10-17
KR102019353B1 true KR102019353B1 (ko) 2019-09-09

Family

ID=64099419

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020170091475A KR102019353B1 (ko) 2017-04-07 2017-07-19 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈

Country Status (2)

Country Link
KR (1) KR102019353B1 (zh)
TW (1) TWI670841B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370331B (zh) * 2018-12-26 2023-04-18 中芯集成电路（宁波）有限公司 摄像组件的封装方法
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
KR20200104463A (ko) * 2019-02-26 2020-09-04 삼성디스플레이 주식회사 표시 장치
KR20200124800A (ko) 2019-04-24 2020-11-04 삼성디스플레이 주식회사 표시 장치
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
CN110770745B (zh) * 2019-06-05 2023-09-05 深圳市汇顶科技股份有限公司 光学指纹装置和电子设备
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
CN112711150B (zh) * 2020-12-22 2022-11-22 业泓科技(成都)有限公司 显示装置
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005110896A (ja) * 2003-10-07 2005-04-28 Canon Inc 指センサ
CN106158772A (zh) * 2015-03-27 2016-11-23 蔡亲佳 板级嵌入式封装结构及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080191297A1 (en) * 2007-02-12 2008-08-14 Advanced Chip Engineering Technology Inc. Wafer level image sensor package with die receiving cavity and method of the same
US7498556B2 (en) * 2007-03-15 2009-03-03 Adavanced Chip Engineering Technology Inc. Image sensor module having build-in package cavity and the method of the same
KR20110068489A (ko) * 2009-12-16 2011-06-22 주식회사 동부하이텍 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
GB2489100A (en) * 2011-03-16 2012-09-19 Validity Sensors Inc Wafer-level packaging for a fingerprint sensor
TW201612704A (en) * 2014-09-25 2016-04-01 Wintek Corp Touch panel and display panel with function of fingerprint identification
KR20160132751A (ko) * 2015-05-11 2016-11-21 삼성전기주식회사 전자부품 패키지 및 그 제조방법
US20170062240A1 (en) * 2015-08-25 2017-03-02 Inotera Memories, Inc. Method for manufacturing a wafer level package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005110896A (ja) * 2003-10-07 2005-04-28 Canon Inc 指センサ
CN106158772A (zh) * 2015-03-27 2016-11-23 蔡亲佳 板级嵌入式封装结构及其制作方法

Also Published As

Publication number Publication date
TW201843824A (zh) 2018-12-16
KR20180113885A (ko) 2018-10-17
TWI670841B (zh) 2019-09-01

Similar Documents

Publication Publication Date Title
KR102019353B1 (ko) 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈
US11037971B2 (en) Fan-out sensor package and optical fingerprint sensor module including the same
JP6668403B2 (ja) ファン−アウト半導体パッケージ及びその製造方法
KR101942740B1 (ko) 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈
KR101963292B1 (ko) 팬-아웃 반도체 패키지
KR102081086B1 (ko) 팬-아웃 반도체 패키지 모듈
KR101942742B1 (ko) 팬-아웃 반도체 패키지
KR101942744B1 (ko) 팬-아웃 반도체 패키지
KR20180037529A (ko) 팬-아웃 반도체 패키지
KR102026132B1 (ko) 팬-아웃 반도체 패키지 모듈
KR101994750B1 (ko) 팬-아웃 반도체 패키지
KR102005351B1 (ko) 팬-아웃 센서 패키지
KR102039711B1 (ko) 팬-아웃 부품 패키지
KR101982047B1 (ko) 팬-아웃 반도체 패키지
KR102554017B1 (ko) 반도체 패키지
KR102524812B1 (ko) 반도체 패키지
KR102586890B1 (ko) 반도체 패키지
KR102621099B1 (ko) 반도체 패키지
KR101963278B1 (ko) 팬-아웃 반도체 패키지 및 그 제조방법
KR20190082603A (ko) 반도체 패키지
KR20200052066A (ko) 반도체 패키지
KR102584960B1 (ko) 반도체 패키지
KR102509644B1 (ko) 패키지 모듈
KR102570270B1 (ko) 반도체 패키지
KR102111302B1 (ko) 팬-아웃 반도체 패키지

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
N231 Notification of change of applicant
GRNT Written decision to grant