KR102017635B1 - 팬-아웃 반도체 패키지 - Google Patents

팬-아웃 반도체 패키지 Download PDF

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Publication number
KR102017635B1
KR102017635B1 KR1020160107695A KR20160107695A KR102017635B1 KR 102017635 B1 KR102017635 B1 KR 102017635B1 KR 1020160107695 A KR1020160107695 A KR 1020160107695A KR 20160107695 A KR20160107695 A KR 20160107695A KR 102017635 B1 KR102017635 B1 KR 102017635B1
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KR
South Korea
Prior art keywords
layer
fan
disposed
semiconductor package
semiconductor chip
Prior art date
Application number
KR1020160107695A
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English (en)
Korean (ko)
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KR20170112905A (ko
Inventor
이두환
김형준
변대정
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to US15/381,635 priority Critical patent/US10818621B2/en
Priority to TW105142116A priority patent/TWI655724B/zh
Priority to JP2016251102A priority patent/JP2017175112A/ja
Publication of KR20170112905A publication Critical patent/KR20170112905A/ko
Application granted granted Critical
Publication of KR102017635B1 publication Critical patent/KR102017635B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020160107695A 2016-03-25 2016-08-24 팬-아웃 반도체 패키지 KR102017635B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/381,635 US10818621B2 (en) 2016-03-25 2016-12-16 Fan-out semiconductor package
TW105142116A TWI655724B (zh) 2016-03-25 2016-12-20 扇出型半導體封裝
JP2016251102A JP2017175112A (ja) 2016-03-25 2016-12-26 ファン−アウト半導体パッケージ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20160036222 2016-03-25
KR1020160036222 2016-03-25
KR1020160077159 2016-06-21
KR20160077159 2016-06-21

Publications (2)

Publication Number Publication Date
KR20170112905A KR20170112905A (ko) 2017-10-12
KR102017635B1 true KR102017635B1 (ko) 2019-10-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160107695A KR102017635B1 (ko) 2016-03-25 2016-08-24 팬-아웃 반도체 패키지

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KR (1) KR102017635B1 (zh)
TW (1) TWI655724B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101982058B1 (ko) * 2017-12-06 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
KR102004243B1 (ko) 2017-12-14 2019-07-26 삼성전자주식회사 팬-아웃 반도체 패키지
KR102028715B1 (ko) 2017-12-19 2019-10-07 삼성전자주식회사 반도체 패키지
US10354978B1 (en) * 2018-01-10 2019-07-16 Powertech Technology Inc. Stacked package including exterior conductive element and a manufacturing method of the same
US11024603B2 (en) 2018-01-10 2021-06-01 Powertech Technology Inc. Manufacturing method and a related stackable chip package
KR102513078B1 (ko) * 2018-10-12 2023-03-23 삼성전자주식회사 반도체 패키지
KR102543188B1 (ko) * 2018-11-19 2023-06-14 삼성전자주식회사 유기 인터포저를 포함하는 반도체 패키지
CN114141726A (zh) * 2021-12-01 2022-03-04 甬矽电子(宁波)股份有限公司 扇出型封装方法和扇出型封装结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012039090A (ja) * 2010-07-15 2012-02-23 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US20130228897A1 (en) * 2012-03-01 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical Connections for Chip Scale Packaging

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387734B1 (en) * 1999-06-11 2002-05-14 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
JP4243117B2 (ja) * 2002-08-27 2009-03-25 新光電気工業株式会社 半導体パッケージとその製造方法および半導体装置
KR101362715B1 (ko) * 2012-05-25 2014-02-13 주식회사 네패스 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
US9704780B2 (en) * 2012-12-11 2017-07-11 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
US9685350B2 (en) * 2013-03-08 2017-06-20 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
US20150048515A1 (en) * 2013-08-15 2015-02-19 Chong Zhang Fabrication of a substrate with an embedded die using projection patterning and associated package configurations
US9449943B2 (en) * 2013-10-29 2016-09-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012039090A (ja) * 2010-07-15 2012-02-23 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US20130228897A1 (en) * 2012-03-01 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical Connections for Chip Scale Packaging

Also Published As

Publication number Publication date
TW201801265A (zh) 2018-01-01
TWI655724B (zh) 2019-04-01
KR20170112905A (ko) 2017-10-12

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