KR101879708B1 - 통합된 데이터 마스킹, 데이터 포이즈닝, 및 데이터 버스 반전 시그널링 - Google Patents

통합된 데이터 마스킹, 데이터 포이즈닝, 및 데이터 버스 반전 시그널링 Download PDF

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KR101879708B1
KR101879708B1 KR1020147016762A KR20147016762A KR101879708B1 KR 101879708 B1 KR101879708 B1 KR 101879708B1 KR 1020147016762 A KR1020147016762 A KR 1020147016762A KR 20147016762 A KR20147016762 A KR 20147016762A KR 101879708 B1 KR101879708 B1 KR 101879708B1
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data bits
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KR20140102703A (ko
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제임스 오코너
아론 니그렌
앤워 카쉼
워렌 크루거
브라이언 블랙
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
KR1020147016762A 2011-12-14 2012-12-13 통합된 데이터 마스킹, 데이터 포이즈닝, 및 데이터 버스 반전 시그널링 Active KR101879708B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/325,648 US8726139B2 (en) 2011-12-14 2011-12-14 Unified data masking, data poisoning, and data bus inversion signaling
US13/325,648 2011-12-14
PCT/US2012/069541 WO2013090599A1 (en) 2011-12-14 2012-12-13 Unified data masking, data poisoning, and data bus inversion signaling

Publications (2)

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KR20140102703A KR20140102703A (ko) 2014-08-22
KR101879708B1 true KR101879708B1 (ko) 2018-07-18

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US (1) US8726139B2 (enExample)
EP (1) EP2791809B1 (enExample)
JP (1) JP5947398B2 (enExample)
KR (1) KR101879708B1 (enExample)
CN (1) CN103988192B (enExample)
WO (1) WO2013090599A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12236104B2 (en) 2021-09-29 2025-02-25 Samsung Electronics Co., Ltd. Operation method of memory module, operation method of memory controller, and operation method of memory system

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677211B2 (en) * 2010-12-23 2014-03-18 International Business Machines Corporation Data bus inversion using spare error correction bits
US20130117593A1 (en) * 2011-11-07 2013-05-09 Qualcomm Incorporated Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects
US9529749B2 (en) 2013-03-15 2016-12-27 Qualcomm Incorporated Data bus inversion (DBI) encoding based on the speed of operation
US9864536B2 (en) * 2013-10-24 2018-01-09 Qualcomm Incorporated System and method for conserving power consumption in a memory system
US9383809B2 (en) * 2013-11-13 2016-07-05 Qualcomm Incorporated System and method for reducing memory I/O power via data masking
US9270417B2 (en) 2013-11-21 2016-02-23 Qualcomm Incorporated Devices and methods for facilitating data inversion to limit both instantaneous current and signal transitions
US9817738B2 (en) * 2015-09-04 2017-11-14 Intel Corporation Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory
US9922686B2 (en) * 2016-05-19 2018-03-20 Micron Technology, Inc. Apparatuses and methods for performing intra-module databus inversion operations
US10754970B2 (en) * 2017-01-27 2020-08-25 International Business Machines Corporation Data masking
US11237729B1 (en) 2020-10-13 2022-02-01 Sandisk Technologies Llc Fast bus inversion for non-volatile memory
KR20230121611A (ko) 2020-12-26 2023-08-18 인텔 코포레이션 시스템 메모리 신뢰성, 가용성 및 서비스 가능성(ras)을개선하기 위한 적응형 오류 정정
US11822484B2 (en) * 2021-12-20 2023-11-21 Advanced Micro Devices, Inc. Low power cache
US12050784B2 (en) * 2022-04-27 2024-07-30 Micron Technology, Inc. Data masking for memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6898648B2 (en) * 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US20100185897A1 (en) * 2007-03-26 2010-07-22 Cray Inc. Fault tolerant memory apparatus, methods, and systems
WO2011008394A2 (en) * 2009-07-13 2011-01-20 Rambus Inc. Encoding data using combined data mask and data bus inversion

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207942A (ja) * 2002-12-25 2004-07-22 Sony Corp データ転送装置とデータ転送方法
US8201071B2 (en) * 2006-11-15 2012-06-12 Qimonda Ag Information transmission and reception
US7616133B2 (en) * 2008-01-16 2009-11-10 Micron Technology, Inc. Data bus inversion apparatus, systems, and methods
US8363707B2 (en) * 2008-03-21 2013-01-29 Micron Technology, Inc. Mixed-mode signaling
US8223042B2 (en) * 2008-04-02 2012-07-17 Rambus Inc. Encoding data with minimum hamming weight variation
JP5588976B2 (ja) * 2008-06-20 2014-09-10 ラムバス・インコーポレーテッド 周波数応答バス符号化
US8271747B2 (en) 2008-07-31 2012-09-18 Rambus Inc. Mask key selection based on defined selection criteria
KR20100053202A (ko) * 2008-11-12 2010-05-20 삼성전자주식회사 Ｒｄｂｉ 기능을 지원하는 반도체 메모리 장치 및 그 테스트 방법
KR101688050B1 (ko) * 2009-12-22 2016-12-21 삼성전자 주식회사 반도체 장치 및 반도체 장치의 리드 또는 라이트 동작 수행 방법
US8260992B2 (en) * 2010-04-12 2012-09-04 Advanced Micro Devices, Inc. Reducing simultaneous switching outputs using data bus inversion signaling
US8706958B2 (en) * 2011-09-01 2014-04-22 Thomas Hein Data mask encoding in data bit inversion scheme
US8495437B2 (en) * 2011-09-06 2013-07-23 Samsung Electronics Co., Ltd. Semiconductor memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6898648B2 (en) * 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US7139852B2 (en) * 2002-02-21 2006-11-21 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US20100185897A1 (en) * 2007-03-26 2010-07-22 Cray Inc. Fault tolerant memory apparatus, methods, and systems
WO2011008394A2 (en) * 2009-07-13 2011-01-20 Rambus Inc. Encoding data using combined data mask and data bus inversion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12236104B2 (en) 2021-09-29 2025-02-25 Samsung Electronics Co., Ltd. Operation method of memory module, operation method of memory controller, and operation method of memory system

Also Published As

Publication number Publication date
CN103988192B (zh) 2018-02-09
US8726139B2 (en) 2014-05-13
US20130159818A1 (en) 2013-06-20
JP5947398B2 (ja) 2016-07-06
EP2791809A1 (en) 2014-10-22
WO2013090599A1 (en) 2013-06-20
KR20140102703A (ko) 2014-08-22
CN103988192A (zh) 2014-08-13
JP2015506039A (ja) 2015-02-26
EP2791809B1 (en) 2017-08-02

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