Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
  • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the present invention is generally directed to high speed memory systems. More particularly, the present invention is directed to improved signaling of data status within a computing system.
• a data bus is susceptible to cross talk, simultaneous switching noise, inter-symbol interference, and draws power based on the state of the data and/or frequency of data transition.
• One way to reduce these adverse effects and to prevent unnecessary power consumption s to encode the data is data bus inversion (DBI).
• DBI data bus inversion
• Implementation of DBI includes encoding circuitry at the transmitter that assesses the relationship between data bits to be transmitted across a data bus and then decides (based on a particular DBI algorithm) if it would be advantageous to invert some or all of the data bits prior to transmission. If the data bits are inverted, an additional signal, referred to as a DBI bit, is also set at the encoding circuitry to indicate that the data bits are inverted. Typically, an extra channel is needed so that the DBI bit may be transmitted in parallel with the data bits to inform the receiving circuitry which groups of data bits have been inverted. A receiver then uses the DBI bit. in conjunction with decoding circuitry to return the incoming group of data bits to their original state.
• DRAMs may be used for the main memory of a computer system, and also may be used in graphics applications.
• DRAMs may include a data masking function to mask data that is input via data input and output pins (typically called "DQ pins") from an external source.
• Data masking generally is performed in units of a single byte and is signaled through the use of a data masking bit or line. For example, in the case of a synchronous DRAM having a data path width of 16 bits, there are generally two data masking pins (typically called "DQM pins”) from which data masking signals are input.
• DQM pins data masking pins
• DQM pins comprise a lower DQM (LDQM) pin and an upper DQM (UDQM) pin.
• the LDQM pin masks data input via data input and output pins DQO through DQ7, e.g., the lower 8 bits of 16 bits that are input via 16 data input and output pins DQl through DQl 5.
• the UDQM pin masks the upper 8 bits, e.g., data input via data input and output pins DQ8 through DQl 5 where pins include any input/output structure for an integrated circuit (IC) device and can include pads, optical input/output structures and other conventional input/output structures.
• an IC memory device can include multiple pins, or lines, that indicate the status of data on a data bus, e.g., DBI and/or masking. Such a device may also use a single control line to indicate the status of a data bus, but utilize multiple clock cycles to convey multiple status states that are associated with the data.
• Embodiments of the disclosed invention in certain circumstances, provide a method of generating unified data signaling that includes setting a state of a single indicator signal and generating a data pattern in a plurality of data bits. Then, based on the state of the single indicator signal and the pattern of the plurality of data bits, the method signals that data bus inversion has been applied to the plurality of data bits, whether masking was applied, or if the data byte is poisoned.
• An embodiment of the disclosed invention provides a method of receiving a unified data signal that includes analyzing a state of a single indicator signal and analyzing a data pattern of a plurality of data bits. Then, based on the state of the single indicator signal and the pattern of the plurality of data bits, the method determines that data bus inversion has been applied to the plurality of data bits, whether masking was applied, or if the data byte is poisoned.
• Another embodiment of the disclosed invention provides a system that includes a memory device and a processing unit coupled to the memory device that sets a state of a single indicator signal and generates a data pattern in a plurality of data bits. Then, based on the state of the single indicator signal and the pattern of the plurality of data bits, the system signals that data bus inversion has been applied to the plurality of data bits, whether masking was applied, or if the data byte is poisoned.
• Yet another embodiment of the disclosed invention provides a system that includes a memory device and a processing unit coupled to the memory device that analyzes a state of a single indicator signal and analyzes a data pattern of a plurality of data bits. Then, based on the analysis of the state of the single indicator signal and the pattern of the plurality of data bits, the system determines that data bus inversion has been applied to the plurality of data bits, whether masking was applied, or if the data byte is poisoned.
• An additional embodiment of the disclosed invention provides a computer program product, that, in response to execution by a computing device, causes the computing device to perform operations that include setting a state of a single indicator signal and generating a data pattern in a plurality of data bits. Then, based on the state of the single indicator signal and the pattern of the plurality of data bits, signals whether data bus inversion has been applied to the plurality of data bits, whether masking was applied, or if the data byte is poisoned.
• FIG. 1 is an illustrative block diagram of a memory access system, according to an embodiment of the present invention.
• FIG. 2 is a flowchart for transmitting data with data base inversion enabled, according to an embodiment of the present invention.
• FIG. 3 is a flowchart for receiving data with data base inversion enabled, according to an embodiment of the present invention.
• FIG. 4 is a flowchart for transmitting data with data base inversion and data poisoning support enabled, according to an embodiment of the present invention.
• FIG. 5 is a flowchart for receiving data with data base inversion and poisoning support enabled, according to an embodiment of the present invention.
• FIG. 6 is a method flowchart for transmitting unified signals, according to an embodiment of the present invention.
• FIG. 7 is a method flowchart for receiving and analyzing unified signals, according to an embodiment of the present invention.
• references to "one embodiment,” “an embodiment,” “an example embodiment,” etc. indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
• FIG. 1 is an illustration of a unified signaling system 100 including a host system
• a storage system 120 and a data command bus 130 that includes data bus lines 132- 0 through 132-N and indicator line 134, a memory system 140, control lines 145 and an interface 150, according to an embodiment of the invention.
• Memory system 140 contains high speed memory, such as stacked DRAM or graphics double data rate memory (GDDR), but can contain any type of memory technology.
• memory system 140 contains logic for data bus inversion (DBI), as will be discussed in more detail later in this specification.
• DI data bus inversion
• Host system 1 10 can access data from storage system 120 and perform reads and writes of data in memory system 140.
• host system 110 accesses memory system 140 through multiple data lines, 132-0 through 132-N.
• the data carried on data lines 132-0 through 132-N can also be referred to as DQ signals, DQ byte, or DQ bits 0 through N.
• Host system 110 also monitors indicator line 134, which indicates, based on the state of an indicator signal present on indicator line 134, an attribute of the data present on data bus lines 132. Such an attribute includes that the data has been inverted, masked, or poisoned, as will be discussed in further detail.
• Interface 150 through control lines 145, controls how the data on data bus lines
• memory system 140 will perform various functions, such as examining the data on data bus lines 132 to ascertain if the data should be inverted when the input from interface 150 indicates data bus inversion is enabled.
• the indicator signal is sampled along with the DQ signals for each read and write to or from memory system 140.
• the state of the indicator signal in conjunction with special data patterns in the associated DQ byte can specify three special certain classes of data including that the data is inverted, masked, or poisoned.
• Data masking provides byte granularity data masking during a write access to memory.
• the mask suppresses an update to the memory.
• the use of data masking is controlled by interface 150 and will be further explained in relationship to data bus inversion and poisoning.
• DBI reduces the number of data signals that switch state (e.g., from low to high) on any given transfer of data, such as to and from memory system 150. If the number of data signals that switch states is minimized then the amount of necessary circuit power is reduced. This also improves signal integrity and generally reduces issues related to instantaneous current draw, e.g. di/dt, and also reduces noise due to state changes.
• DBi algorithms can limit the number of state changes to 50% of the data on the data bus. For example, for a DQ byte consisting of 8 bits/lines of data, the use of DBI can limit the number of changing states between two consecutive 8 bit DQ bytes to a maximum of 4 changing bits.
• interface 150 If DBI is disabled by interface 150 then any DBI signals over control lines 145 will not be asserted. Further, interface 150 can be configured to support either DBI-dc or DBI-ac modes.
• DBI DBI-dc
• each group of data signals, DQ byte, on data bus lines 132 and the indicator signal on indicator line 134 is examined each cycle. If 50% or more of the data signals on data bus lines 132 with a given indicator signal on indicator line 134 are driven high, then the indicator signal is enabled, or driven high, and the associated data signals on data bus lines 132 are inverted. Otherwise, indicator signal on indicator line 134 is disabled, driven low, and the associated data signals on data bus lines 132 are not inverted.
• the indicator signal is driven high and the DQ bits are inverted resulting in three high DQ bits and one high indicator signal, for a total of four high signals.
• DBI data is transmitted on data bus lines 132 and indicator signal is disabled, or equivalently set to 0. If DBI- ac is enabled on interface 150, then each group of data signals, DQ byte, on data bus lines 132 and indicator signal on indicator line 134 is examined each cycle. If 50% or more of the data signals on data bus lines 132 with a given indicator signal on indicator line 134 are to switch, e.g., the state of a DQ bit is to be driven to a different value than the signal held in the previous cycle, then the indicator signal is enabled, or driven high, and the associated data signals on data bus lines 132 are inverted.
• indicator signal on indicator line 134 is disabled, driven low, and the associated data signals on data bus lines 132 are not inverted.
• the DQ byte consists of 8 bits
• the indicator signal is driven high and the DQ bits are inverted resulting in three switched DQ bits and at most one switched indicator signal (if the previous indicator signal was not enabled), for a total switching of four signals.
• DBI-dc is enabled on interface 150, when host system 110 writes a masked plurality of data bits, e.g. the byte in question will not be written to memory, a special encoding is used where indicator signal on indicator line 134 is enabled, set high, and DQ bits on data bus lines 132 are set to the first half of the bits are set low and the second half of the bits are set high. For example, if there are eight bits in the DQ byte then the pattern can be shown as 000011 11. This encoding does not occur for any regular or unmasked data patterns.
• DBI-ac is enabled on interface 150, when host system 110 writes a masked data byte, e.g. the byte, or plurality of data bits, in question will not be written to memory, a special encoding is used where indicator signal on indicator line 134 is enabled, set high, and DQ bits on data bus lines 132 are set such that the first half of the bits are switched from their previous value.
• the pattern can be shown as 00001 1 1 1 which is generated by exclusive ORing the previous DQ data on data bus lines 132 with the current DQ data on data bus lines 132. This encoding does not occur for any regular or unmasked data patterns.
• Data poisoning is a system-level data integrity mechanism for storing data with uncorrectable errors.
• the poisoned state is returned to the host system 1 10 and indicates that the host stored the previously unreliable data.
• host system 1 10 is likely to maintain error-correcting code
• ECC ECC- protected write-back caches.
• ECC error-correctable write-back caches.
• this error may not be detected until the cache line is evicted.
• the data is corrupted, but the process that generated or requires this data may no longer be executing on host system 1 10.
• the desired behavior is to evict the corrupted data to memory and store the "poisoned state" of this data. Subsequent reads of this poisoned data from memory will signal an error to the process requesting this data.
• a write of data marked as poisoned causes the generated ECC bits to encode an uncorrectable error. This behavior will cause an uncorrectable error on any subsequent read of this data.
• Unmasked writes to the entire protected word can reset the poisoned state, as the corrupted data has effectively been overwritten.
• DBI-dc is enabled on interface 150, then each group of data signals on data bus lines 132 and the indicator signal on indicator line 134 is examined each cycle. If 50% or more of the data signals on data bus lines 132 with a given indicator signal on indicator line 134 are driven high, then the indicator signal is enabled, or driven high, and the associated data signals on data bus lines 132 are inverted. Otherwise, indicator signal on indicator line 134 is disabled, driven low, and the associated data signals on data bus lines 132 are not inverted.
• the indicator signal is driven high and the DQ bits are inverted resulting in three high DQ bits and one high indicator signal, for a total of four high signals.
• DBI DBI-ac
• each group of data signals on data bus lines 132 and indicator signal on indicator line 134 is examined each cycle. If 50% or more of the data signals on data bus lines 132with a given indicator signal on indicator line 134 are to switch, e.g., the state of a DQ bit is to be driven to a different value than the signal held in the previous cycle, then the indicator signal is enabled, or driven high, and the associated data signals on data bus lines 132 are inverted. Otherwise, indicator signal on indicator line 134 is disabled, driven low, and the associated data signals on data bus lines 132 are not inverted.
• the indicator signal is driven high and the DQ bits are inverted resulting in three switched DQ bits and at most one switched indicator signal (if the previous indicator signal was not enabled), for a total switching of four signals.
• DBI-dc is enabled on interface 150, when host system 110 writes a masked data byte, e.g. the byte, or plurality of data bits, in question will not be written to memory, a special encoding is used where indicator signal on indicator line 134 is enabled, set high, and DQ bits on data bus lines 132 are set so that the first half of the bits are set low and the second half of the bits are set high. For example, if there are eight bits in the DQ byte then the pattern can be shown as 00001 111. This encoding does not occur for any regular or unmasked data patterns.
• DBI-ac is enabled on interface 150
• host system 110 writes a masked data byte, e.g. the byte, or plurality of data bits, in question will not be written to memory
• a special encoding is used where indicator signal on indicator line 134 is enabled, set high, and DQ bits on data bus lines 132 are set such that the first half of the bits are switched from their previous value. For example, if there are eight bits in the DQ byte then the pattern can be shown as 000011 11 which is generated by exclusive ORing the previous DQ data on data bus lines 132 with the current DQ data on data bus 132. This encoding does not occur for any regular or unmasked data patterns.
• DBI-dc is enabled on interface 150
• host system 1 10 writes a poisoned data byte, or plurality of data bits
• a special encoding is used where indicator signal on indicator line 134 is enabled, set high, and DQ bits on data bus lines 132 are set so that the first half of the bits are set high and the second half of the bits are set low. If there are eight bits in the DQ byte then the pattern can be shown as 11 110000. This encoding does not occur for any regular or masked data patterns.
• DBI-ac is enabled on interface 150
• host system 1 10 writes a masked data byte e.g. the byte, or plurality of data bits, in question will not be written to memory
• a special encoding is used where indicator signal on indicator line 134 is enabled, set high, and DQ bits on data bus lines 132 are set such that the second half of the bits are switched from their previous value. For example, if there are eight bits in the DQ byte then the pattern can be shown as 11110000 which is generated by exclusive ORing the previous DQ data on data bus lines 132 with the current DQ data on data bus lines 132. This encoding does not occur for any regular or masked data patterns.
• FIG. 2 is a flowchart 200 for transmitting data with data base inversion enabled, e.g., by memory system 140 is response to a read command, according to an embodiment of the present invention.
• memory system 140 can tri-state the DQ and indicator signals, effectively holding the prior state. After issuing one or more read commands, prior to memory system 140 sending a write command or entering an idle state, memory system 140 drives the DQ data on data bus lines 132 and indicator signal on indicator line 134 low.
• this driving the DQ data on data bus lines 132 and indicator signal on indicator line 134 low can occur over two half-clock periods in order to ensure that no more than five data signals, in a group of eight data signals will switch in any transition, thus conserving power and minimizing noise.
• memory system 140 When memory system 140 is driving the signals due to a write command, the DBI behavior is similar. Between write commands, memory system 140 will hold the DQ and indicator signals. After issuing one or more write commands, prior to memory system 140 sending a read command or entering an idle state, memory system 140 will drive the DQ and indicator signals low over a two clock window.
• Flowchart 200 starts with a burst of data, setting the previous DQ byte to low.
• the next data DQ byte is compared to the previous DQ byte to count the number of bits that are different. Next, it is determined whether or not the data has been deemed to be masked. If the data is masked then the indicator signal is enabled, set to high. Further, the DQ signals are in a "do not care" state and the data is set such that the first half of the plurality of data bits is set low and the second half is set high. If the data is not masked, then the count of different bits is analyzed. If the count is greater than 50% of the number of bits in the DQ byte (the flowchart uses the example where the DQ byte consists of eight bits), then the indicator signal is set to high and the nest data is inverted. If the count is less than 50% of the number of bits in the DQ byte, then the indicator signal is set to low and the next data is not inverted.
• the flowchart continues by checking if the burst has ended, if not, then the process is repeated with the choice of whether the system is utilizing DBI-ac or DBI-dc. If DBI-ac is being used then flowchart continues by counting the number of different bits between the previous data and the next data. If DBI-dc is being used the previous data is first set to low, and then the number of different bits are counted between the previous data and the next data.
• FIG. 3 is a flowchart 300 for determining the correct data by a receiver, e.g., by memory systems 140 receiving data for a write command, according to an embodiment of the present invention.
• Flowchart 300 starts with a burst of data, setting the previous DQ byte to low. A data DQ byte and associated indicator signal are received and examined. The flowchart first determines if the indicator signal is high. If the indicator signal is low then the received data is not inverted.
• the previously received data is exclusively OR'ed with the current data to determine if the first half of the DQ byte is low and the second half of the DQ byte is set high. If it is not, then this indicates that the data is not masked, but that it should be inverted. If the data pattern does match a "masked" pattern, e.g., where the first half of the DQ byte is low and the second half of the DQ byte is high, then the data is masked.
• the data pattern indicating that the plurality of data bits is masked can be any predefined pattern, not just the example given above where the first half of the bits are low and the second half are high.
• the pattern of the plurality of data bits indicating that the bits are masked could consist of a subset of the plurality of data bits where at least one-half of the subset are set to an active state.
• data masking could be signaled where there are a certain number of bits that are set, e.g., exactly four bits are set, indicating that the plurality of data bits are masked.
• a pattern such as 00001 1110000111 1 would indicate that the plurality of data bits are masked.
• next step in the flowchart is to determine if the burst has ended, if it has then the flowchart also concludes. If the burst has not ended then the process continues with the next DQ byte.
• FIG. 4 and FIG. 5 are flowcharts that also include the ability to generate and analyze the indicator signal in conjunction with the DQ byte to determine if the DQ data is poisoned.
• FIG. 4 is a flowchart 400 for performing DBI where data poisoning support is enabled for data being transmitted, e.g., by memory systems 140 is response to a read command, according to an embodiment of the present invention.
• memory system 140 can tri-state the DQ and indicator signals, effectively holding the prior state. After issuing one or more read commands, prior to memory system 140 sending a write command or entering an idle state, memory system 140 drives the DQ data on data bus lines 132 and indicator signal on indicator line 134 low.
• this driving the DQ data on data bus lines 132 and indicator signal on indicator line 134 low can occur over two half-clock periods in order to ensure that no more than five data signals, in a group of eight data signals will switch in any transition, thus conserving power and minimizing noise.
• memory system 140 When memory system 140 is driving the signals due to a write command, the DBI behavior is similai-. Between write commands, memory system 140 will hold the DQ and indicator signals. After issuing one or more write commands, prior to memory system 140 sending a read command or entering an idle state, memory system 140 will drive the DQ and indicator signals low over a two clock window.
• Flowchart 400 starts with a burst of data, setting the previous DQ byte to low.
• the next data DQ byte is compared to the previous DQ byte to count the number of bits that are different. Next, it is determined whether or not the data has been deemed to be masked or poisoned. If the data is not masked or poisoned, then the count of different bits is analyzed. If the count is greater than 50% of the number of bits in the DQ byte (the flowchart uses the example where the DQ byte consists of eight bits), then the indicator signal is set to high and the nest data is inverted. If the count is less than 50% of the number of bits in the DQ byte, then the indicator signal is set to low and the next data is not inverted.
• the indicator signal is enabled, set to high.
• the DQ signals are in a "do not care" state but are patterned according to whether the DQ byte is determined to be masked or poisoned. In an embodiment, if the data is masked then the first half of the DQ byte is set low and the second half is set high (the flowchart illustrates an eight bit example where the DQ byte pattern would be 00001111). If the data is poisoned then the first half of the DQ byte is set high and the second half is set low (the flowchart illustrates an eight bit example where the DQ byte pattern would be 1 1 110000).
• data poisoning can be signaled by any predefined pattern, not just the example given above where the first half of the bits are high and the second half are low.
• the pattern of the plurality of data bits indicating that the bits are poisoned could consist of where at least one-half of the plurality of data bits are set that are not in a subset of the plurality of data bits that indicate that the plurality of data bits is masked.
• data poisoning could be signaled where there are a certain number of bits that are set, e.g., exactly five bits are set, indicating that the plurality of data bits are poisoned.
• a pattern such as 1 1 1 10000111 10000 would indicate that the plurality of data bits are poisoned
• the flowchart continues by checking if the burst has ended, if not, then the process is repeated with the choice of whether the system is utilizing DBI-ac or DBI-dc. If DBI-ac is being used then flowchart continues by counting the number of different bits between the previous data and the next data. If DBI-dc is being used the previous data is first set to low, and then the number of different bits are counted between the previous data and the next data.
• FIG. 5 is a flowchart 500 for determining the correct data by a receiver, e.g., by memory systems 140 receiving data for a write command where data poisoning support is enabled, according to an embodiment of the present invention.
• Flowchart 500 starts with a burst of data, setting the previous DQ byte to low. A data DQ byte and associated indicator signal are received and examined. The flowchart first determines if the indicator signal is high. If the indicator signal is low then the received data is not inverted.
• DQ byte is low and the second half of the DQ byte is set high (illustrated in the flowchart of FIG. 5 with an 8 bit DQ byte where the pattern is 0000111 1). If the pattern matches then that indicates that the DQ byte is masked.
• next step in the flowchart is to determine if the burst has ended, if it has the flowchart also concludes. If the burst has not ended then the process continues with the next DQ byte.
• FIG. 6 is a flowchart of an exemplary method 600 for the generation of unified signaling.
• method 600 is described with respect to the unified signaling system of FIG. 1 using the methodology described in FIGs. 2-5, but embodiments of the method are not limited thereto.
• Method 600 begins at step 602 with the setting a state of a single indicator signal.
• the indicator signal is set low to indicate that the next data is not to be inverted.
• the indicator signal is set high to indicate that either the next data is to be inverted, or that the plurality of data bits is masked or poisoned.
• step 604 The method continues at step 604 with the generating of a data pattern in a plurality of data bits.
• the method also relies on the pattern of the plurality of data bits to discern whether the plurality of data bits is masked or poisoned. If the data pattern is such that the first half of the plurality of data bits is set high and the second half is set low, then the plurality of data bits is considered poisoned. If the first half of the plurality of data bits is set low and the second half is set high, then the plurality of data bits is considered masked.
• step 606 by signaling, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.
• This step decodes the pattern of the plurality of data bits in conjunction with the state of the indicator signal to indicate the status of the plurality of data bits.
• FIG. 7 is a flowchart of an exemplary method 700 for the receiving and analyzing of unified signaling.
• method 700 is described with respect to the unified signaling system of FIG. 1 using the methodology described in FIGs. 2-5, but embodiments of the method are not limited thereto.
• Method 700 begins at step 702 with the analyzing a state of a single indicator signal. As discussed in regards to FIG. 4, when the indicator signal is low the next data is not inverted. When the indicator signal is set high the next data is inverted, masked or poisoned.
• step 704 The method continues at step 704 with the analyzing of a data pattern in a plurality of data bits.
• the method also relies on the pattern of the plurality of data bits to discern whether the plurality of data bits is masked or poisoned. If the data pattern is such that the first half of the plurality of data bits is set high and the second half is set low, then the plurality of data bits is considered poisoned. If the first half of the plurality of data bits is set low and the second half is set high, then the plurality of data bits is considered masked.
• step 706 decodes the pattern of the plurality of data bits in conjunction with the state of the indicator signal to indicate the status of the plurality of data bits.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Dram (AREA)
• Information Transfer Systems (AREA)
• Bus Control (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=47472088

Family Applications (1)

Country Status (6)

Cited By (2)

Families Citing this family (12)

Citations (3)

Family Cites Families (12)

• 2011
  • 2011-12-14 US US13/325,648 patent/US8726139B2/en active Active
• 2012
  • 2012-12-13 JP JP2014547436A patent/JP5947398B2/ja active Active
  • 2012-12-13 CN CN201280061408.9A patent/CN103988192B/zh active Active
  • 2012-12-13 WO PCT/US2012/069541 patent/WO2013090599A1/en not_active Ceased
  • 2012-12-13 EP EP12809487.7A patent/EP2791809B1/en active Active
  • 2012-12-13 KR KR1020147016762A patent/KR101879708B1/ko active Active

Patent Citations (3)

Also Published As

Similar Documents

Legal Events