JP5947398B2 - 統合データマスキング、データポイズニング及びデータバス反転シグナリング - Google Patents
統合データマスキング、データポイズニング及びデータバス反転シグナリング Download PDFInfo
- Publication number
- JP5947398B2 JP5947398B2 JP2014547436A JP2014547436A JP5947398B2 JP 5947398 B2 JP5947398 B2 JP 5947398B2 JP 2014547436 A JP2014547436 A JP 2014547436A JP 2014547436 A JP2014547436 A JP 2014547436A JP 5947398 B2 JP5947398 B2 JP 5947398B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- data bits
- state
- bits
- poisoned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/325,648 US8726139B2 (en) | 2011-12-14 | 2011-12-14 | Unified data masking, data poisoning, and data bus inversion signaling |
| US13/325,648 | 2011-12-14 | ||
| PCT/US2012/069541 WO2013090599A1 (en) | 2011-12-14 | 2012-12-13 | Unified data masking, data poisoning, and data bus inversion signaling |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015506039A JP2015506039A (ja) | 2015-02-26 |
| JP2015506039A5 JP2015506039A5 (enExample) | 2016-02-04 |
| JP5947398B2 true JP5947398B2 (ja) | 2016-07-06 |
Family
ID=47472088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014547436A Active JP5947398B2 (ja) | 2011-12-14 | 2012-12-13 | 統合データマスキング、データポイズニング及びデータバス反転シグナリング |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8726139B2 (enExample) |
| EP (1) | EP2791809B1 (enExample) |
| JP (1) | JP5947398B2 (enExample) |
| KR (1) | KR101879708B1 (enExample) |
| CN (1) | CN103988192B (enExample) |
| WO (1) | WO2013090599A1 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8677211B2 (en) * | 2010-12-23 | 2014-03-18 | International Business Machines Corporation | Data bus inversion using spare error correction bits |
| US20130117593A1 (en) * | 2011-11-07 | 2013-05-09 | Qualcomm Incorporated | Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects |
| US9529749B2 (en) | 2013-03-15 | 2016-12-27 | Qualcomm Incorporated | Data bus inversion (DBI) encoding based on the speed of operation |
| US9864536B2 (en) * | 2013-10-24 | 2018-01-09 | Qualcomm Incorporated | System and method for conserving power consumption in a memory system |
| US9383809B2 (en) * | 2013-11-13 | 2016-07-05 | Qualcomm Incorporated | System and method for reducing memory I/O power via data masking |
| US9270417B2 (en) | 2013-11-21 | 2016-02-23 | Qualcomm Incorporated | Devices and methods for facilitating data inversion to limit both instantaneous current and signal transitions |
| US9817738B2 (en) * | 2015-09-04 | 2017-11-14 | Intel Corporation | Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory |
| US9922686B2 (en) * | 2016-05-19 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for performing intra-module databus inversion operations |
| US10754970B2 (en) * | 2017-01-27 | 2020-08-25 | International Business Machines Corporation | Data masking |
| US11237729B1 (en) | 2020-10-13 | 2022-02-01 | Sandisk Technologies Llc | Fast bus inversion for non-volatile memory |
| KR20230121611A (ko) | 2020-12-26 | 2023-08-18 | 인텔 코포레이션 | 시스템 메모리 신뢰성, 가용성 및 서비스 가능성(ras)을개선하기 위한 적응형 오류 정정 |
| KR20230046362A (ko) | 2021-09-29 | 2023-04-06 | 삼성전자주식회사 | 메모리 모듈의 동작 방법, 메모리 컨트롤러의 동작 방법, 및 메모리 시스템의 동작 방법 |
| US11822484B2 (en) * | 2021-12-20 | 2023-11-21 | Advanced Micro Devices, Inc. | Low power cache |
| US12050784B2 (en) * | 2022-04-27 | 2024-07-30 | Micron Technology, Inc. | Data masking for memory |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6898648B2 (en) * | 2002-02-21 | 2005-05-24 | Micron Technology, Inc. | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing |
| JP2004207942A (ja) * | 2002-12-25 | 2004-07-22 | Sony Corp | データ転送装置とデータ転送方法 |
| US8201071B2 (en) * | 2006-11-15 | 2012-06-12 | Qimonda Ag | Information transmission and reception |
| US8245087B2 (en) | 2007-03-26 | 2012-08-14 | Cray Inc. | Multi-bit memory error management |
| US7616133B2 (en) * | 2008-01-16 | 2009-11-10 | Micron Technology, Inc. | Data bus inversion apparatus, systems, and methods |
| US8363707B2 (en) * | 2008-03-21 | 2013-01-29 | Micron Technology, Inc. | Mixed-mode signaling |
| US8223042B2 (en) * | 2008-04-02 | 2012-07-17 | Rambus Inc. | Encoding data with minimum hamming weight variation |
| JP5588976B2 (ja) * | 2008-06-20 | 2014-09-10 | ラムバス・インコーポレーテッド | 周波数応答バス符号化 |
| US8271747B2 (en) | 2008-07-31 | 2012-09-18 | Rambus Inc. | Mask key selection based on defined selection criteria |
| KR20100053202A (ko) * | 2008-11-12 | 2010-05-20 | 삼성전자주식회사 | Rdbi 기능을 지원하는 반도체 메모리 장치 및 그 테스트 방법 |
| EP2454672B1 (en) | 2009-07-13 | 2015-01-21 | Rambus Inc. | Encoding data using combined data mask and data bus inversion |
| KR101688050B1 (ko) * | 2009-12-22 | 2016-12-21 | 삼성전자 주식회사 | 반도체 장치 및 반도체 장치의 리드 또는 라이트 동작 수행 방법 |
| US8260992B2 (en) * | 2010-04-12 | 2012-09-04 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
| US8706958B2 (en) * | 2011-09-01 | 2014-04-22 | Thomas Hein | Data mask encoding in data bit inversion scheme |
| US8495437B2 (en) * | 2011-09-06 | 2013-07-23 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
-
2011
- 2011-12-14 US US13/325,648 patent/US8726139B2/en active Active
-
2012
- 2012-12-13 JP JP2014547436A patent/JP5947398B2/ja active Active
- 2012-12-13 CN CN201280061408.9A patent/CN103988192B/zh active Active
- 2012-12-13 WO PCT/US2012/069541 patent/WO2013090599A1/en not_active Ceased
- 2012-12-13 EP EP12809487.7A patent/EP2791809B1/en active Active
- 2012-12-13 KR KR1020147016762A patent/KR101879708B1/ko active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR101879708B1 (ko) | 2018-07-18 |
| CN103988192B (zh) | 2018-02-09 |
| US8726139B2 (en) | 2014-05-13 |
| US20130159818A1 (en) | 2013-06-20 |
| EP2791809A1 (en) | 2014-10-22 |
| WO2013090599A1 (en) | 2013-06-20 |
| KR20140102703A (ko) | 2014-08-22 |
| CN103988192A (zh) | 2014-08-13 |
| JP2015506039A (ja) | 2015-02-26 |
| EP2791809B1 (en) | 2017-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5947398B2 (ja) | 統合データマスキング、データポイズニング及びデータバス反転シグナリング | |
| KR102350538B1 (ko) | Ddr 메모리 에러 복구 | |
| KR102426619B1 (ko) | 영구 메모리 시스템 등을 위한 데이터 무결성 | |
| US7916553B2 (en) | Memory system and method having volatile and non-volatile memory devices at same hierarchical level | |
| TW202223903A (zh) | 適應性內部記憶體錯誤刷洗及錯誤處置 | |
| KR102460513B1 (ko) | 통합 패키지 후 복구 | |
| US10002043B2 (en) | Memory devices and modules | |
| TWI518512B (zh) | 使用資料匯流排反轉訊號以減少同時之切換輸出之裝置與方法 | |
| US9158616B2 (en) | Method and system for error management in a memory device | |
| US8738993B2 (en) | Memory device on the fly CRC mode | |
| US8527836B2 (en) | Rank-specific cyclic redundancy check | |
| CN112349342B (zh) | 维护ddr5内存子系统的维护装置、方法、设备和存储介质 | |
| CN114840137B (zh) | 用于在动态随机存取存储器上执行写入训练的技术 | |
| CN105373345A (zh) | 存储器设备和模块 | |
| US11429481B1 (en) | Restoring memory data integrity | |
| CN101868788B (zh) | 基于周转事件的调度 | |
| CN104281545B (zh) | 一种数据读取方法及设备 | |
| KR102334739B1 (ko) | 메모리 모듈, 시스템, 및 그것의 에러 정정 방법 | |
| US20250130877A1 (en) | Handling Faulty Usage-Based-Disturbance Data | |
| WO2025122888A1 (en) | Variable burst length for a memory device | |
| CN118732946A (zh) | 一种持久内存设备和系统 | |
| CN117472644A (zh) | 错误确定方法及系统、处理器、内存 | |
| WO2020015134A1 (zh) | 一种随机内存使用纠错码校验可配置功能设置分区的方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151207 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20151207 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20151207 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20151225 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160112 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160411 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160510 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160602 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5947398 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |