KR101840240B1 - 마이크로 전자 패키지 - Google Patents
마이크로 전자 패키지 Download PDFInfo
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- KR101840240B1 KR101840240B1 KR1020147012161A KR20147012161A KR101840240B1 KR 101840240 B1 KR101840240 B1 KR 101840240B1 KR 1020147012161 A KR1020147012161 A KR 1020147012161A KR 20147012161 A KR20147012161 A KR 20147012161A KR 101840240 B1 KR101840240 B1 KR 101840240B1
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- G—PHYSICS
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- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2924/301—Electrical effects
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (9)
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US201161542553P | 2011-10-03 | 2011-10-03 | |
US201161542488P | 2011-10-03 | 2011-10-03 | |
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US201261600361P | 2012-02-17 | 2012-02-17 | |
US61/600,361 | 2012-02-17 | ||
US13/439,286 | 2012-04-04 | ||
US13/439,286 US8525327B2 (en) | 2011-10-03 | 2012-04-04 | Stub minimization for assemblies without wirebonds to package substrate |
PCT/US2012/057554 WO2013052345A1 (en) | 2011-10-03 | 2012-09-27 | Stub minimization for assemblies without wirebonds to package substrate |
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KR20140084131A KR20140084131A (ko) | 2014-07-04 |
KR101840240B1 true KR101840240B1 (ko) | 2018-05-04 |
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KR1020147012162A KR101901218B1 (ko) | 2011-10-03 | 2012-10-01 | 패키지 기판에 대한 와이어본드를 갖지 않는 어셈블리를 위한 스터브 최소화 |
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US10886228B2 (en) * | 2015-12-23 | 2021-01-05 | Intel Corporation | Improving size and efficiency of dies |
US10410963B1 (en) * | 2018-06-07 | 2019-09-10 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Deformed layer for short electric connection between structures of electric device |
EP3837611A4 (en) * | 2018-08-14 | 2022-05-11 | Rambus Inc. | PACKAGED INTEGRATED DEVICE |
CN112687614A (zh) | 2019-10-17 | 2021-04-20 | 美光科技公司 | 包含多个装置堆叠的微电子装置组合件和封装体以及相关方法 |
US11393794B2 (en) * | 2019-10-17 | 2022-07-19 | Micron Technology, Inc. | Microelectronic device assemblies and packages including surface mount components |
CN112687615A (zh) | 2019-10-17 | 2021-04-20 | 美光科技公司 | 微电子装置组合件、封装体和相关方法 |
Citations (3)
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JP2002083897A (ja) | 2000-09-05 | 2002-03-22 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20030089982A1 (en) | 2001-08-16 | 2003-05-15 | Robert Feurle | Sharing of multiple-access signal line in a printed circuit board |
US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
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JPS6193694A (ja) * | 1984-10-15 | 1986-05-12 | 松下電器産業株式会社 | 集積回路装置 |
JPS63232389A (ja) * | 1987-03-20 | 1988-09-28 | 株式会社日立製作所 | 面実装パツケ−ジの配線方式 |
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US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
JP3179420B2 (ja) * | 1998-11-10 | 2001-06-25 | 日本電気株式会社 | 半導体装置 |
JP3914651B2 (ja) * | 1999-02-26 | 2007-05-16 | エルピーダメモリ株式会社 | メモリモジュールおよびその製造方法 |
JP2000340737A (ja) * | 1999-05-31 | 2000-12-08 | Mitsubishi Electric Corp | 半導体パッケージとその実装体 |
DE10055001A1 (de) * | 2000-11-07 | 2002-05-16 | Infineon Technologies Ag | Speicheranordnung mit einem zentralen Anschlussfeld |
SG118103A1 (en) * | 2001-12-12 | 2006-01-27 | Micron Technology Inc | BOC BGA package for die with I-shaped bond pad layout |
JP3742051B2 (ja) * | 2002-10-31 | 2006-02-01 | エルピーダメモリ株式会社 | メモリモジュール、メモリチップ、及びメモリシステム |
TWI221664B (en) * | 2002-11-07 | 2004-10-01 | Via Tech Inc | Structure of chip package and process thereof |
DE10259221B4 (de) | 2002-12-17 | 2007-01-25 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben |
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JP4058642B2 (ja) * | 2004-08-23 | 2008-03-12 | セイコーエプソン株式会社 | 半導体装置 |
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JP4906047B2 (ja) | 2005-11-28 | 2012-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JP2009200101A (ja) * | 2008-02-19 | 2009-09-03 | Liquid Design Systems:Kk | 半導体チップ及び半導体装置 |
KR20100046760A (ko) * | 2008-10-28 | 2010-05-07 | 삼성전자주식회사 | 반도체 패키지 |
-
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- 2012-09-27 KR KR1020147012161A patent/KR101840240B1/ko active IP Right Grant
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Patent Citations (3)
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JP2002083897A (ja) | 2000-09-05 | 2002-03-22 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20030089982A1 (en) | 2001-08-16 | 2003-05-15 | Robert Feurle | Sharing of multiple-access signal line in a printed circuit board |
US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
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WO2013052398A2 (en) | 2013-04-11 |
TW201324731A (zh) | 2013-06-16 |
JP5881833B2 (ja) | 2016-03-09 |
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EP2764542A2 (en) | 2014-08-13 |
KR101901218B1 (ko) | 2018-11-08 |
JP2015502652A (ja) | 2015-01-22 |
EP2764541A1 (en) | 2014-08-13 |
WO2013052398A3 (en) | 2013-08-22 |
JP5895059B2 (ja) | 2016-03-30 |
TWI491016B (zh) | 2015-07-01 |
JP2014535165A (ja) | 2014-12-25 |
KR20140081857A (ko) | 2014-07-01 |
TWI459518B (zh) | 2014-11-01 |
WO2013052347A1 (en) | 2013-04-11 |
TW201322416A (zh) | 2013-06-01 |
KR20140084131A (ko) | 2014-07-04 |
TWI489611B (zh) | 2015-06-21 |
TW201330187A (zh) | 2013-07-16 |
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