WO2013052398A3 - Stub minimization for assemblies without wirebonds to package substrate - Google Patents

Stub minimization for assemblies without wirebonds to package substrate Download PDF

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Publication number
WO2013052398A3
WO2013052398A3 PCT/US2012/058229 US2012058229W WO2013052398A3 WO 2013052398 A3 WO2013052398 A3 WO 2013052398A3 US 2012058229 W US2012058229 W US 2012058229W WO 2013052398 A3 WO2013052398 A3 WO 2013052398A3
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WO
WIPO (PCT)
Prior art keywords
columns
central region
microelectronic
face
wirebonds
Prior art date
Application number
PCT/US2012/058229
Other languages
French (fr)
Other versions
WO2013052398A2 (en
Inventor
Richard Dewitt Crisp
Wael Zohni
Belgacem Haba
Frank Lambrecht
Original Assignee
Invensas Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/439,354 external-priority patent/US8629545B2/en
Application filed by Invensas Corporation filed Critical Invensas Corporation
Priority to KR1020147012162A priority Critical patent/KR101901218B1/en
Priority to JP2014534620A priority patent/JP5895059B2/en
Priority to EP12783713.6A priority patent/EP2764542A2/en
Publication of WO2013052398A2 publication Critical patent/WO2013052398A2/en
Publication of WO2013052398A3 publication Critical patent/WO2013052398A3/en

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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/3011—Impedance

Abstract

A system (1500) or microelectronic assembly (300) can include one or more microelectronic packages (100) each having a substrate (102) and a microelectronic element (130) having a face (134) and one or more columns (138, 140) of contacts (132) exposed thereat which face and are joined to corresponding contacts on a surface (120) of the substrate. An axial plane (140) may intersect the face along a line in the first direction (142) and centered relative to the columns of element contacts. Columns (104A, 104B) of package terminals can extend in the first direction. First terminals exposed at a central region (112) of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region (112) may have a width (152) not more than three and one-half times a minimum pitch (150) between the columns of package terminals. The axial plane can intersect the central region.
PCT/US2012/058229 2011-10-03 2012-10-01 Stub minimization for assemblies without wirebonds to package substrate WO2013052398A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020147012162A KR101901218B1 (en) 2011-10-03 2012-10-01 Stub minimization for assemblies without wirebonds to package substrate
JP2014534620A JP5895059B2 (en) 2011-10-03 2012-10-01 Minimizing stubs in assemblies without wire bonds to the package substrate
EP12783713.6A EP2764542A2 (en) 2011-10-03 2012-10-01 Stub minimization for assemblies without wirebonds to package substrate

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201161542488P 2011-10-03 2011-10-03
US201161542553P 2011-10-03 2011-10-03
US61/542,488 2011-10-03
US61/542,553 2011-10-03
US201261600361P 2012-02-17 2012-02-17
US61/600,361 2012-02-17
US13/439,354 US8629545B2 (en) 2011-10-03 2012-04-04 Stub minimization for assemblies without wirebonds to package substrate
US13/439,354 2012-04-04

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WO2013052398A2 WO2013052398A2 (en) 2013-04-11
WO2013052398A3 true WO2013052398A3 (en) 2013-08-22

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PCT/US2012/057563 WO2013052347A1 (en) 2011-10-03 2012-09-27 Memory module in a package and its pin configuration
PCT/US2012/057554 WO2013052345A1 (en) 2011-10-03 2012-09-27 Stub minimization for assemblies without wirebonds to package substrate
PCT/US2012/058229 WO2013052398A2 (en) 2011-10-03 2012-10-01 Stub minimization for assemblies without wirebonds to package substrate

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PCT/US2012/057563 WO2013052347A1 (en) 2011-10-03 2012-09-27 Memory module in a package and its pin configuration
PCT/US2012/057554 WO2013052345A1 (en) 2011-10-03 2012-09-27 Stub minimization for assemblies without wirebonds to package substrate

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EP (2) EP2764541A1 (en)
JP (2) JP5881833B2 (en)
KR (2) KR101840240B1 (en)
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10886228B2 (en) * 2015-12-23 2021-01-05 Intel Corporation Improving size and efficiency of dies
US10410963B1 (en) * 2018-06-07 2019-09-10 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Deformed layer for short electric connection between structures of electric device
US11742277B2 (en) 2018-08-14 2023-08-29 Rambus Inc. Packaged integrated device having memory buffer integrated circuit asymmetrically positioned on substrate
US11362070B2 (en) 2019-10-17 2022-06-14 Micron Technology, Inc. Microelectronic device assemblies and packages including multiple device stacks and related methods
CN112687615A (en) 2019-10-17 2021-04-20 美光科技公司 Microelectronic device assemblies, packages, and related methods
CN112687614A (en) 2019-10-17 2021-04-20 美光科技公司 Microelectronic device assemblies and packages including multiple device stacks and related methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027019A1 (en) * 2000-09-05 2002-03-07 Seiko Epson Corporation Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument
EP1205977A2 (en) * 2000-11-07 2002-05-15 Infineon Technologies AG Memory device with central connecting area
US20030089982A1 (en) * 2001-08-16 2003-05-15 Robert Feurle Sharing of multiple-access signal line in a printed circuit board
US20060004981A1 (en) * 2004-06-30 2006-01-05 Bains Kuljit S Apparatus and method for initialization of a double-sided dimm having at least one pair of mirrored pins
US20100102428A1 (en) * 2008-10-28 2010-04-29 Samsung Electronics Co., Ltd Semiconductor package

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193694A (en) * 1984-10-15 1986-05-12 松下電器産業株式会社 Ic device
JPS63232389A (en) * 1987-03-20 1988-09-28 株式会社日立製作所 Wiring system of surface mount package
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
JP3179420B2 (en) * 1998-11-10 2001-06-25 日本電気株式会社 Semiconductor device
JP3914651B2 (en) * 1999-02-26 2007-05-16 エルピーダメモリ株式会社 Memory module and manufacturing method thereof
JP2000340737A (en) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp Semiconductor package and body mounted therewith
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
SG118103A1 (en) * 2001-12-12 2006-01-27 Micron Technology Inc BOC BGA package for die with I-shaped bond pad layout
JP3742051B2 (en) * 2002-10-31 2006-02-01 エルピーダメモリ株式会社 Memory module, memory chip, and memory system
TWI221664B (en) * 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
DE10259221B4 (en) 2002-12-17 2007-01-25 Infineon Technologies Ag Electronic component comprising a stack of semiconductor chips and method of making the same
JP4058642B2 (en) * 2004-08-23 2008-03-12 セイコーエプソン株式会社 Semiconductor device
US7745944B2 (en) * 2005-08-31 2010-06-29 Micron Technology, Inc. Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
JP4906047B2 (en) 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 Semiconductor device
US7518226B2 (en) * 2007-02-06 2009-04-14 Stats Chippac Ltd. Integrated circuit packaging system with interposer
JP2009200101A (en) * 2008-02-19 2009-09-03 Liquid Design Systems:Kk Semiconductor chip and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027019A1 (en) * 2000-09-05 2002-03-07 Seiko Epson Corporation Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument
EP1205977A2 (en) * 2000-11-07 2002-05-15 Infineon Technologies AG Memory device with central connecting area
US20030089982A1 (en) * 2001-08-16 2003-05-15 Robert Feurle Sharing of multiple-access signal line in a printed circuit board
US20060004981A1 (en) * 2004-06-30 2006-01-05 Bains Kuljit S Apparatus and method for initialization of a double-sided dimm having at least one pair of mirrored pins
US20100102428A1 (en) * 2008-10-28 2010-04-29 Samsung Electronics Co., Ltd Semiconductor package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2764542A2 *

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JP2015502652A (en) 2015-01-22
KR20140084131A (en) 2014-07-04
WO2013052347A1 (en) 2013-04-11
TWI459518B (en) 2014-11-01
WO2013052398A2 (en) 2013-04-11
JP2014535165A (en) 2014-12-25
KR20140081857A (en) 2014-07-01
TW201330187A (en) 2013-07-16
EP2764541A1 (en) 2014-08-13
TW201324731A (en) 2013-06-16
KR101840240B1 (en) 2018-05-04
JP5895059B2 (en) 2016-03-30
WO2013052345A1 (en) 2013-04-11
KR101901218B1 (en) 2018-11-08
TWI489611B (en) 2015-06-21
EP2764542A2 (en) 2014-08-13
TW201322416A (en) 2013-06-01
JP5881833B2 (en) 2016-03-09
TWI491016B (en) 2015-07-01

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