TWI459518B - Stub minimization for assemblies without wirebonds to package substrate - Google Patents

Description

Short-term minimization of assemblies for wireless bonding to package substrates

The subject matter of this application is directed to microelectronic packages and assemblies incorporating microelectronic packages.

This application is a continuation application filed in the U.S. Application Serial No. 13/439,286, filed on Apr. 4, 2012, which is hereby incorporated by The right to file the filing date of US Provisional Application Nos. 61/542,488 and 61/542,553, filed on October 3, 2011. The disclosures of all of these applications are hereby incorporated by reference.

Semiconductor wafers are typically provided as individual pre-packaged units. A standard wafer has a flat rectangular body having a large front surface with contacts that are connected to internal circuitry of the wafer. Each individual wafer is typically contained in a package having an external terminal, which in turn is electrically coupled to a circuit such as a printed circuit board and the contacts of the wafer are connected to the conductor of the circuit panel. In many conventional designs, the chip package occupies one area of the circuit panel that is much larger than the area of the wafer itself. As used in the present invention, reference is made to a flat wafer having a front side, and "area of the wafer" is understood to mean the area of the front side.

In a flip chip design, the front side of the wafer faces a face of the packaged dielectric component (ie, the substrate of the package), and the contacts on the wafer are directly bonded to the substrate by solder bumps or other connecting components. Contact parts. Then, the substrate is bonded to a circuit panel through a terminal covering the surface of the substrate. The The "Cladding" design provides a relatively compact configuration. In some cases, each package can be a "wafer-level package" that occupies one area of the circuit panel that is equal to or slightly larger than the area of the front side of the wafer, such as, for example, a US patent that is commonly assigned. No. 5,148,265; 5,148,266; and 5,679,977, the disclosure of each of which is incorporated herein by reference. Specific innovative mounting techniques provide a compactness that is approximately equal to or equivalent to conventional flip chip bonding. An important consideration in any physical configuration of the size wafer. With the rapid development of portable electronic devices, it has become increasingly more and more demanding that the physical configuration of the wafers is more compact. By way of example only, devices commonly referred to as "smart phones" use powerful data processors, memory and devices such as GPS receivers, electronic cameras and LAN connections along with high-resolution displays and associated images. The auxiliary device for processing the chip integrates the function of a cellular phone. Such devices can provide all of a one-pocket sized device such as a full network connection, entertainment with full resolution video, navigation, e-banking and more. Complex portable devices need to package a large number of wafers into a small space. In addition, some of these wafers have a number of input and output connections, commonly referred to as "I/O." These I/Os must be interconnected with I/Os of other chips. These interconnects should be shorted to minimize signal propagation delay. The components that form the interconnects should not significantly increase the size of the assembly. For example, similar requirements arise in other applications, such as those used in Internet search engines that require increased performance and reduced size.

Semiconductor wafers containing memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips, are typically packaged in multiple wafers In the package and assembly. Each package has a plurality of electrical connections for carrying signals, power and ground between the terminals (ie, the external connection points of the package) and the wafers therein. The electrical connectors may comprise different kinds of conductors, such as horizontal conductors (eg, traces, beam leads, etc.) extending in a horizontal direction relative to a contact bearing support surface of a wafer, in a vertical direction A vertical conductor (such as a via) extending relative to a surface of the wafer and a wire bond extending in a horizontal direction and a vertical direction with respect to a surface of the wafer.

Conventional microelectronic packages can have microelectronic components that primarily have one of the memory storage array functions, i.e., microelectronic components that implement more active devices to provide memory storage array functionality in addition to any other functionality. The microelectronic component can be or comprise a dynamic random access memory (DRAM) wafer or a stacked electrical interconnect assembly of such semiconductor wafers. Typically, all of the terminals of the package are placed in a set of rows adjacent to one or more peripheral edges of one of the package substrates on which the microelectronic component is mounted. For example, in one of the conventional microelectronic packages 12 shown in FIG. 1, three rows 14 of terminals can be disposed adjacent one of the first peripheral edges 16 of the package substrate 20, and the other three rows 18 of terminals can be placed. Adjacent to one of the second peripheral edges 22 of the package substrate 20. One of the central regions 24 of the package substrate 20 in the conventional package does not have any row of terminals. 1 further shows a semiconductor wafer 11 in the package having element contacts 26 on one of its faces 28 that extend through one of the apertures in the central region 24 of the package substrate 20. Wire bonds 30 (e.g., bonding windows) are electrically interconnected with the rows 14, 18 of the terminals of the package 12. In some cases, it may be on the face 28 of the microelectronic component 11 An adhesive layer 32 is disposed between the substrate 20 to enhance the mechanical connection between the microelectronic component and the substrate, wherein the wire bonds extend through one of the openings in the adhesive layer 32.

In view of the foregoing, particular improvements can be made to locating terminals on a microelectronic package to improve the electrical performance of assemblies including, in particular, such packages and one of which can be electrically interconnected.

A microelectronic package in accordance with one aspect of the present invention can include a microelectronic component having the functionality of a memory storage array. In one example, the microelectronic component can implement more active devices to provide memory storage array functionality in addition to any other functionality. The microelectronic component can have one or more rows of component contacts exposed at one of the faces of the microelectronic component, each row extending along a face of the microelectronic component in a first direction. An axis plane normal to the face of the microelectronic component can intersect a face of the microelectronic component along a line extending in the first direction and be centered relative to the one or more rows of component contacts. The microelectronic package can include a substrate having a first opposing surface and a second opposing surface and a plurality of substrate contacts exposed to the component contacts and bonded to the component contacts. A plurality of parallel rows exposed to the terminals of the second surface may extend along the second surface of the substrate in the first direction. The terminals are electrically connectable to the substrate contacts and configured to connect the microelectronic package to one of the components external to the microelectronic package.

The terminals can include a first terminal exposed at a second surface of the substrate in a central region of the second surface of the substrate. The first terminals can be The configuration is configured to carry address information that can be used by circuitry within the package to determine an addressable memory location from all available addressable memory locations within the microelectronic component from a memory storage array. In one example, the central region of the second surface can have a width along a second surface of the substrate in a second direction transverse to the first direction, wherein the width can be no greater than any of the parallel terminals of the rows Three and a half times the minimum spacing between two adjacent rows. In this example, the axis plane can intersect the central region.

In one example, the terminals can be configured to carry all of the address information that can be used by circuitry within the package to determine the addressable address of the addressable memory.

In an example, the first terminals can be configured to carry information that controls an operational mode of the microelectronic component.

In an example, the first terminals can be configured to carry all of the command signals transmitted to the microelectronic package, the command signals being write enable signals, column address strobe signals, and row address selection Pass signal.

In an example, the first terminals can be configured to carry clock signals transmitted to the microelectronic package, the microelectronic packages configured to use the clock signals to sample receive and carry the The signal at the terminal of the address information.

In an example, the first terminals can be configured to carry all of the reservoir address signals transmitted to the microelectronic package.

In an example, the first terminals can be disposed in no more than two rows of the terminal rows.

In an example, the first terminals can be disposed in a single row of the terminal rows.

In an example, component contacts connected to the first terminals can be placed In a single row of component contacts.

In an example, the component contacts can include redistribution contacts exposed at the front side of the microelectronic component. Each of the redistribution contacts is electrically connectable to one of the microelectronic component contact pads via at least one of a trace or a via. At least some of the redistribution contacts are displaceable from the component contacts along the face of the microelectronic component in at least one direction.

In an example, the substrate can have a first opposing edge and a second opposing edge each extending between the first opposing surface and the second opposing surface. The first opposing edge and the second opposing edge may extend in the first direction. The second surface may have a first peripheral region and a second peripheral region adjacent to the first opposing edge and the second opposing edge, respectively. In this example, the central region separates the first peripheral region from the second peripheral region. The terminals can include a plurality of second terminals exposed at a second surface of at least one of the peripheral regions. At least some of the second terminals can be configured to carry information other than the address information.

In an example, at least some of the second terminals can be configured to carry a data signal.

In one example, the microelectronic component can include a first semiconductor wafer having contacts thereon coupled to the substrate contacts and a surface of the first surface overlying the first semiconductor wafer away from the substrate and The first semiconductor wafer is electrically interconnected with at least one second semiconductor wafer.

In an example, the first wafer can be configured to receive at least some of the address information from the first terminals and to generate the at least some of the address information for transmission to the at least one second wafer. In one example, the at least one second crystal The slice may implement more active devices to provide memory storage array functionality in addition to any other functionality.

In an example, the first terminals can be configured to carry information that controls an operational mode of the microelectronic component. The first wafer can be configured to perform at least one of: regenerating or at least partially decoding information that controls the mode of operation.

In one example, the first wafer can include a plurality of through vias that electrically connect the at least one second wafer to the first wafer.

In one example, at least some of the electrical interconnections between the first wafer and the at least one second wafer are performed by wire bonding.

In one example, the at least one second wafer can be flipped through a surface of the second contact exposed to one surface of the second wafer and connected to a surface of the first contact exposed to the first wafer. An electrical interconnect is electrically interconnected with the first wafer. In this example, the surface of the first wafer can face away from the first surface of the substrate.

In an example, the first wafer can be configured to buffer at least some of the address information received at the first terminals for transmission to each second wafer, and each second wafer can be non-configured as Buffer the address information.

In an example, the first wafer can be configured to at least partially decode address information received at the first terminals for transmission to each second wafer, and each second wafer can be non-configured to be completely Decode the address information.

In an example, the second semiconductor wafer can be a plurality of stacked second semiconductor wafers.

In one example, the first wafer and the at least one second wafer of the wafer At least some of them may be electrically connected to each other by a plurality of through holes.

In one example, at least one of the at least one second wafer can be configured to perform at least one of: partially or completely decoding information received at one of the contacts, or regenerating a contact received therewith The information is transmitted to at least one of the first wafer or the other of the at least one second wafer.

In one example, at least some of the electrical interconnections between the first wafer and the second wafer are permeable to conductive traces extending along at least one edge of the microelectronic component.

In one example, at least some of the electrical interconnections between the first wafer and the second wafer are permeable to wire bonding. In this example, one of the at least one second wafer faces away from the first wafer. At least some of the wire bonds may connect the first wafer to a contact exposed at a face of the at least one second wafer.

In one example, at least some of the electrical interconnections between the first wafer and the second wafer are permeable to wire bonding. In this example, one of the at least one second wafer faces the first wafer. At least some of the wire bonds may connect the first wafer to a contact exposed at a face of the at least one second wafer.

In this example, at least one of the first wafers or the at least one second wafer can include a dynamic random access memory ("DRAM") storage array.

In one example, at least one of the first wafers or the at least one second wafer can be implemented in a NAND flash memory, a resistive RAM (RRAM), a phase change memory (PCM), Magnetic random access memory (MRAM), spin torque RAM or content addressable memory technology.

A microelectronic package in accordance with one aspect of the present invention can comprise a microelectronic component having a memory storage array. The microelectronic component can implement more active devices to provide memory storage array functionality in addition to any other functionality. The microelectronic component can have one or more rows of component contacts exposed at one of the faces of the microelectronic component. Each row may extend along a face of the microelectronic element in a first direction. An axis plane normal to the face of the microelectronic component can intersect a face of the microelectronic component along a line extending in the first direction. The axis plane can be centered relative to the one or more rows of component contacts.

The microelectronic package can include a substrate having a first opposing surface and a second opposing surface and a plurality of substrate contacts exposed to the component contacts and bonded to the component contacts. A plurality of rows of parallel terminals exposed to the second surface may extend at the second surface of the substrate in the first direction. The terminals are electrically connectable to the substrate contacts and are configurable to connect the microelectronic package to one of the components external to the microelectronic package. The terminals can include a first terminal exposed at a second surface in a central region of the second surface of the substrate. The first terminals can be configured to carry a bit that can be used by circuitry within the package to determine an addressable memory location from all available addressable memory locations within the microelectronic component from a memory storage array Information. In one example, the central region can have a width along a second surface transverse to the first direction along a second surface of the substrate, the width being no greater than any two adjacent rows of parallel rows of the rows One and a half times the minimum spacing between the two. The axis plane can intersect the central area.

In this example, the first terminals can be configured to carry the seal The circuitry within the device is used to determine at least three-quarters of the address information for the addressable memory location.

In view of the illustrative conventional microelectronic package 12 described with respect to FIG. 1, the inventors have recognized that improvements can be made in electrical performance that can be improved and packaged with one of the memory storage array wafers and with one of the packages. .

An improvement may be made particularly for a microelectronic package when a microelectronic package is provided in an assembly such as that shown in Figures 2 through 4, in which a package 12A is mounted to one of the surface of a circuit panel. Where another identical package 12B is oppositely mounted to an opposite surface of the circuit panel. The packages 12A, 12B are typically functionally and mechanically equivalent to each other. Other pairs of 12C and 12D; and 12E and 12F functional and mechanical equivalent packages are typically also mounted to the same circuit panel 34. The circuit panel and the package assembled to the circuit panel can form part of one of the assemblies commonly referred to as a dual in-line memory module ("DIMM"). The contacts in each pair of oppositely mounted packages (eg, packages 12A, 12B) that are connected to opposite surfaces of the circuit panel are such that the packages in each pair typically overlap each other by more than 90% of their respective areas. The area wiring within the circuit panel 34 connects terminals (e.g., terminals labeled "1" and "5" on each package) to the global wiring on the circuit panel. The global wiring includes signal conductors for conducting some of the signals to the busbars 36 of one of the connection locations on the circuit panel 34, such as locations I, II, and III. For example, the packages 12A, 12B are electrically connected to the bus bar 36 by a region wiring coupled to a connection portion I, and the packages 12C, 12D are electrically connected to the bus bar by a region wiring coupled to a connection portion II, and sealed. The package 12E, 12F is electrically connected to the bus bar by a region wiring coupled to the connection portion III.

The circuit panel 34 electrically interconnects the terminals of the respective packages 12A, 12B using area interconnect wiring that appears similar to one of the terminals labeled "1" near one of the edges 16 of the package 12A through the circuit panel. 34 is connected to a cross or "lace" pattern of one of the terminals of package 12B labeled "1" near the same edge 16 of package 12B. However, the edge 16 of the package 12B as assembled to the circuit panel 34 is remote from the edge 16 of the package 12A. 2 through 4 further illustrate that one of the terminals labeled "5" near one edge 22 of the package 12A is connected through the circuit panel 34 to one of the terminals of the package 12B labeled "5" near the same edge 22 of the package 12B. In assembly 38, edge 22 of package 12A is remote from edge 22 of package 12B.

The connections through the circuit panels between the terminals on each package (eg, package 12A) to the corresponding terminals on the package (eg, package 12B) that are relatively mounted to the circuit panel are relatively long. As further shown in FIG. 3, in such an assembly as microelectronic packages 12A, 12B, when the same signal is transmitted from the busbar 36 to each package, the circuit panel 34 can signal one of the busbars. The conductor is electrically interconnected with a terminal of the package 12A labeled "1" and a corresponding terminal of the package 12B labeled "1." Similarly, the circuit panel 34 can electrically interconnect another signal conductor of the bus bar 36 with a terminal of the package 12A labeled "2" and a corresponding terminal of the package 12B labeled "2." The same connection configuration can also be applied to other signal conductors of the busbar and corresponding terminals of each package. A pair of packages (eg, packages) of the busbars 36 on the circuit panel 34 and the connection locations I at one of the circuit boards The area wiring between each package of 12A, 12B (Fig. 2) can be in the form of an unterminated stub. This area routing can affect the performance of assembly 38 as discussed below in some cases. In addition, the circuit board 34 also requires the area wiring to be used for other packages: the pair of packages 12C and 12D and the specific terminals of the pair of packages 12E and 12F are electrically interconnected to the global wiring of the bus bar 36, and the wiring can also be affected in the same manner. The effectiveness of the assembly.

Figure 4 further illustrates microelectronics assigned to carry a number of pairs of terminals of signals "1", "2", "3", "4", "5", "6", "7" and "8" The interconnection between the packages 12A, 12B. As shown in FIG. 4, because the rows 14, 18 of the terminals are respectively adjacent the edges 16, 22 of each of the packages 12A, 12B, they are transverse in a direction 40 transverse to the direction 42 in which the rows 14, 18 of the terminals extend. The wiring required across the circuit panel 34 can be quite long. When the length of the cognitive DRAM wafer can be in the range of 10 millimeters on each side, the same signal is routed to one of the two relative installations in one of the circuit panels 34 of one of the assemblies 38 shown in FIGS. 2 through 4. The length of the area wiring required for the corresponding terminals of the packages 12A, 12B can be in the range between 5 mm and 10 mm, and can typically be about 7 mm.

In some cases, the length of the circuit panel wiring required to connect the terminals of such relatively mounted microelectronic packages does not necessarily seriously affect the electrical performance of the assembly. However, when the signal carried by one of the packages 12A, 12B is connected to the connected terminal, the signal is used to carry address information or other information (such as a memory for sampling a plurality of packages connected to the circuit panel). The inventor recognizes that the short lines extend from the bus bar 36 to each of the signals of one of the bus bars 36 when the body storage array function operates a common address information. The length of the wiring of the terminals on a package can significantly affect performance. When the interconnect wiring is relatively long, a more serious effect occurs, which can increase the settling time, ringing effect, jitter, or intersymbol interference of the transmitted signal to an unacceptable level.

In a particular embodiment, the bus 36 for carrying address information may be a command address bus 36 configured to carry command information, address information, repository address information, and time information. In a particular embodiment, the command information can be transmitted as a command signal on a respective signal conductor on the circuit panel. The address information can also be transmitted as an address signal on the respective signal conductor. For example, the repository address information can also be transmitted as a storage address address signal on the respective signal conductor, and the clock information can also be transmitted as Clock signals on the respective signal conductors. In a particular implementation having one of the microelectronic components of a memory storage array such as a DRAM wafer, the command signals that can be carried by the bus 36 can be write enable, column address strobe, and row position The address strobe signal, and the clock signal that can be carried by the bus 36 can be a clock signal for at least sampling an address signal carried by the bus 36.

Accordingly, certain embodiments of the invention described herein provide a microelectronic package configured to be on an opposing surface of a circuit panel (eg, a circuit board, a modular board or a module card or a flexible circuit panel) Mounting the first and second packages opposite each other allows for a reduction in the length of the stub on the circuit panel. And the assembly of the first microelectronic package and the second microelectronic package electrically connected to the circuit panel at a position of the circuit panel can significantly reduce the short length between the respective packages. Reduce the shortness of these assemblies The line length can be improved in electrical performance, such as by reducing one or more of settling time, ringing effects, jitter, or intersymbol interference. In addition, other benefits may be obtained, such as simplifying the structure of the circuit panel or reducing the complexity and cost of designing or fabricating the circuit panel, or reducing the complexity and cost of designing and fabricating the circuit panel.

Thus, a microelectronic package 100 in accordance with one embodiment of the present invention is illustrated in FIGS. 5 and 6A. As shown therein, the package 100 can include one of the microelectronic components 130 having a memory storage array function. In an example, the microelectronic component can be configured to primarily provide a memory storage array function, wherein the microelectronic component can have more active configurations configured to provide memory storage array functionality in addition to any other functionality A device, such as a transistor.

As further shown, the package can include a substrate 102 having a first opposing surface 120 and a second opposing surface 110. The first opposing surface and the second opposing surface face in opposite directions, and thus are opposite each other, and are "opposing surfaces." A plurality of first terminals 104 and a plurality of second terminals 106 are exposed at the second surface 110 of the substrate 102. As used herein, a conductive element "exposed" to one of the surfaces of a structure indicates that the conductive element is in contact with a theoretical point of movement from the exterior of the structure toward the surface in a direction perpendicular to one of the surfaces. Thus, one of the terminals or other conductive elements exposed to one of the surfaces of a structure may protrude from the surface; may be flush with the surface; or may be recessed relative to the surface and exposed through a hole or pit in the structure .

The substrate can comprise a sheet-like dielectric component, which in some cases can consist essentially of a polymeric material (eg, a resin or polyimide, etc.). Alternatively, the substrate may comprise a glass growth having, for example, a BT resin One of the strong epoxy resin composite structures or one of the FR-4 dielectric components. In another example, the substrate can comprise a support member having a material having a thermal expansion coefficient ("CTE") of less than 12 parts per million per degree Celsius, the terminals and other conductive structures disposed over the support member. For example, the low CTE element can consist essentially of a glass, ceramic or semiconductor material or a liquid crystal polymer material or a combination of such materials.

The first terminals 104 can be disposed at positions within a plurality of parallel rows 104A, 104B extending in a first direction, and the second terminals 106 can be disposed at a plurality of locations exposed to a surface 110 of the substrate At the locations within rows 106A and 106B. In the example shown in FIG. 5, rows 104A and 104B can each contain some first terminals disposed in a central region 112 of the surface 110, and rows 106A, 106B can each have respective perimeters disposed outside of the central region. Some of the terminals 114A, 114B. The central region has a width in a second direction transverse to the first direction. As shown and described further below with respect to FIG. 7B, the central region is no wider than three and a half times the minimum spacing between adjacent rows of parallel terminals of the rows. As indicated above, the first terminals can be configured to carry address information transmitted to the microelectronic package. In a particular embodiment, the address information is received by the first terminal from a busbar 36 (eg, a command address bus) on the circuit panel. The address information can be received as individual address signals (eg, signals A0 through A15 on respective first terminals), or some or all of the address information can be received as a voltage received on more than one first terminal A combination of levels (for example, information in the form of a code when received). In a particular embodiment, some or all of the address information is used to sample the One of the information may be received on one or more of the first terminals when one of the clocks is rising (ie, the clock transitions from one of the first states of the higher voltage to one of the second states of the lower voltage) Or some or all of the address information may be received at a falling transition of the clock (ie, the clock transitions from a second state of the lower voltage to a first state of the higher voltage) One or more of the first terminals. In yet another example, some of the address information may be received on one or more of the first terminals when one of the clocks is rising, and some of the address information may be at the clock. A falling transition is received on one or more of the first terminals.

As described above, the second terminals 106 can be disposed at one or more of the first peripheral region 114A and the second peripheral region 114B of the substrate surface 110, and can be disposed in the row 106A as shown. At the location within 106B. As shown in FIG. 5, in some cases the first peripheral region and the second peripheral region can be adjacent to the first opposing edge 116 and the second opposing edge 118 of the surface 110. The central region 112 is disposed between the first peripheral region 114A and the second peripheral region 114B. In an example, the second terminals can be disposed at locations that each have one or more rows 106A, 106B of the plurality of second terminals.

In a specific example, when the microelectronic component includes or is a DRAM semiconductor wafer, the first terminal in the central region can be configured to carry address information transmitted to the microelectronic package, the address information The circuitry within the package (e.g., by a column address decoder and row address decoder and bank selection circuitry (if present)) for use in all of the available components within a microelectronic component from a memory storage array Determining an addressable record in the address memory location Recall the body position. Generally, when the microelectronic component includes a DRAM chip, the address information in an embodiment may include all address information transmitted from one component (for example, a circuit panel) of the package to the package, the address. The information can be used to determine a random access addressable memory location within a memory storage array within the microelectronic package for read access, or read or write access.

In a particular embodiment, such as when the microelectronic component is of a type that receives a address signal from a command address bus on the circuit panel, the first terminals can be configured to carry the address signal The storage address signal, the specific command signal, and the pulse signal are used to sample the clock of the address signals. Although the clock signals can be of various types, in one embodiment, the clock signal carried by the terminals can be received as one of the differential clock signal or the actual clock signal and the complementary clock signal. Pair or more pairs of differential clocks. In this case, the "command signal" may be one of a write enable signal, a column address strobe signal, and a row address strobe signal by one of the microelectronic components in the microelectronic package. For example, in one particular example as shown in FIG. 5, the first terminals may include clock signals CK and CKB, column address strobe RAS, row address strobe CAS, and write enable signal WE and include Address signals A0 to A15 and bank address signals BA0, BA1 and BA2.

As shown in the cross-sectional view of FIG. 6A, one of the microelectronic components 130 within the microelectronic package 100 has a component contact 132 exposed at one of the faces 134 of the microelectronic component 130. The component contacts 132 face the corresponding substrate contacts 136 exposed at a surface 120 of a substrate 102, and the component contacts Connect to the substrate contacts. For example, the contacts of the microelectronic component can be flip-chip bonded to the contacts of the substrate using a bonding metal such as solder, tin, indium, gold, eutectic or other conductive bonding metal or bonding material. Alternatively, in an appropriate case, another technique such as metal to metal bonding may be used, for example, one of the copper bumps may be utilized on one or both of the component contacts 132 and the corresponding substrate contacts 136. Connected with copper.

In the example shown in FIGS. 5-6A, a microelectronic package 100 has rows 104A, 104B including terminals of a first terminal 104 exposed at a surface 110 of a substrate 102 in a central region 112 of the surface 110 of the substrate. . As further shown in FIG. 6B, the component contacts 132 exposed at one of the faces 134 of the microelectronic component 130 can be disposed in a first row 138 that each extends over a face 134 of the microelectronic component in a first direction 142. And at the position in the second line 139. As in the case of row 138, one row of contacts on the microelectronic component can be completely filled, or as in the case of row 139, a row of contacts can have only contacts at some locations within the row. As shown in FIGS. 6A-6B, one of the axial planes 140 of the microelectronic element 130 intersects the face 134 of the microelectronic element 130 along a line extending in the first direction 142, and the axis plane 140 is also normal. Extending in a second direction of one of the faces 134 of the microelectronic component. In the case of the microelectronic component 130 shown in FIG. 6B, the axial plane 140 can be centered (eg, equidistant) between the rows 138, 139 of the component contacts and the microelectronic component 134 intersects. As further shown in FIG. 6B, since the rows 138, 139 of the component contacts are typically not accurately centered between the opposite edges 146, 148 of the microelectronic component, the axial plane 140 can pass A center line 144 extending from the first direction 142 is often displaced along the face 134 in a vertical direction 143 and is accurately centered between the opposing edges 146, 148. However, in a particular embodiment, when the positions of the rows 138, 139 are so positioned that the centerline 144 is centered between the rows, the axis plane 140 can coincide with the centerline 144.

As further shown in FIG. 6B, in addition, the microelectronic element 130 can include a plurality of peripheral contacts adjacent one or more of the peripheral edges 146, 148. These peripheral contacts can be used to connect to a power source, ground, or can be used as a contact that can be used in contact with a detector such as one that can be used to test. In this case, the intersection of the axial plane 140 with the face 134 of the microelectronic element can be centered only relative to the contact rows 138, 139 that are adjacent to each other disposed near the center of the microelectronic component. When determining that the axis plane 140 intersects the microelectronic element 130, omitting other ones disposed adjacent one of the edges 146 or 148 of the microelectronic element and configured to connect to a power source, ground, or detection device Contact 192.

Thus, the contacts of the microelectronic component can include the one or more rows of contacts 138, 139 that are the first contacts and that contain a majority of the contacts. The contact of the microelectronic component can further include a second contact 192 disposed adjacent the one or more edges of the face exposed to the face of the microelectronic component. The second contacts 192 are less than the number of first contacts in any of the rows. In a particular example, each of the second contacts can be configured to connect to a power source, a ground, or be configured to connect to a detection device. In a complete package 100, the contacts may not be electrically connected to the substrate 102 or, in some cases, may be electrically connected only to the Corresponding power or ground conductor on the substrate. In this example, regardless of the location of the second contacts 192, the intersection of the axis plane 140 with the face 134 of the microelectronic element 130 can be relative to the rows of the first contacts (eg, as in Figure 6B). Lines 138, 139) shown are centered.

6C illustrates a contact pad 332 in which the microelectronic component can be placed in the vicinity of the center of the microelectronic element 330 in one or two rows 338, 339 (eg, adjacent one of the central axes 140 of the microelectronic component). Yet another example. In this example, the component contacts that are coupled to corresponding contacts 136 (FIG. 6A) of the substrate can be redistribution contacts 145, 147 on the microelectronic component. Some or all of the redistribution contacts 145, 147 electrically coupled to the contact pads 332 can be displaced from the contact pads 332 along one of the microelectronic elements in one or more directions 142, 143. . In an example, the redistribution contacts can be disposed in a plurality of rows 135, 137 that are closer to the edges 146, 148 of the microelectronic component than rows 338, 339 of the contact pads 332. In a particular example, the redistribution contacts can be distributed in an array of regions exposed at the surface of the microelectronic element. In another particular example, the redistribution contacts can be distributed along one or more peripheral edges 146, 148 of a microelectronic element extending in a first direction 142, or second along a direction transverse to direction 142 One or more peripheral edges 151, 153 of the microelectronic element extending in direction 143 are distributed. In yet another example, the redistribution contacts can be distributed along two or more of the peripheral edges 146, 148, 151, 153 of the microelectronic element. In any of these examples, the redistribution contacts 145, 147 can be disposed on the same face of the microelectronic component as the contact pads 332, or can be placed in contact with the contacts The pad is opposite the face of the microelectronic component. In one example, each contact pad can be coupled to a redistribution contact. In another example, there may be no redistribution contacts connected to one or more contact pads. The one or more contact pads 332 that are not connected to the redistribution contacts may or may not be electrically connected to one or more corresponding terminals of the package.

Referring to FIG. 6A, the axial plane 140 intersects a central region 112 of the surface 110 of the substrate 102 of the microelectronic package 100. Thus, the axis plane is configured to carry a command address address bus or command bit that is configured to carry the aforementioned address information of the aforementioned address or (in a particular embodiment) configured to carry command address The row 104A, 104B of the terminal of the address bus signal intersects the central region 112 of the substrate surface 110. In the following, it should be understood that reference to the first terminal refers to terminals that are exposed in the central region 112 of the substrate surface, wherein, in general, whether the first terminals are configured to carry the circuitry used in the microelectronic package To determine all or at least a majority (or in one instance, three-quarters or more) of the address information of an addressable memory location within a memory storage array, the terminals are configured to carry The pass can be used by circuitry within the microelectronic package to determine address information for an addressable memory location from all available addressable memory locations within the memory array of the microelectronic package. In some embodiments, the first terminals can also be configured to carry additional information or also carry signals, such as the write enable, column address strobe, and row address strobe described above. Function command information or command signal, repository address information, and timely information.

As further shown in FIG. 6A, a bonding metal (eg, solder, tin, Bonding elements 154A, 154B of indium or eutectic or other electrically conductive bonding material can be bonded to the terminals 104A, 104B so that the terminals of the package 100 can be bonded to one of the components of the package, such as a circuit panel Corresponding contacts.

As further shown in FIG. 7A, in some cases, a microelectronic element 230 can have only one row 238 containing a plurality of contacts exposed at the face 134, in which case the axis plane 240 extends through the contacts. Trip 238. As shown in FIG. 7B, since the axis plane 240 is incorporated into the microelectronic package 200, the axis plane 240 can intersect the central region 112 of the substrate surface at a location between the rows 104A, 104B of the terminal, wherein the axis Each of the plane 240 and the rows 104A, 104B extends in a first direction 142 in which one of the rows 238 of the contacts of the microelectronic element extends. Alternatively, in another example (not shown), the axis plane 240 can intersect the center region 112 along a line extending in the first direction, wherein the line intersects one of the rows 104A or 104B of the terminals .

As further shown in Figure 7B, there is a minimum pitch 150 as the minimum distance between any two adjacent terminal rows on the substrate. The minimum spacing is defined as the minimum distance between the lines extending through the respective adjacent rows in direction 162.

The minimum spacing is in a direction 143 that is perpendicular to a direction 142 of the terminals in a particular row (e.g., row 104A). In the example shown in FIG. 7B, the minimum spacing occurs between rows 104A, 104B that are closest to each other between edge 116 and edge 118 of substrate 110. With further reference to FIG. 7B, the central region 112 is in the direction 143 of the pitch (ie, in the lateral direction) In the second direction of the first direction 142) along the substrate surface 110 has a maximum width 152 that is no greater than the minimum spacing between any two adjacent terminal rows (eg, rows 104A, 104B of the terminals) Three and a half times.

7C illustrates a microelectronic package 300 of a first microelectronic package 100A and a second microelectronic package 100B, each of which is a microelectronic package 100 as described above with reference to FIGS. 5-6B. They are mounted to the opposite first surface 350 and the opposite second surface 352 of a circuit panel 354. The circuit panel can be of various types, such as a printed circuit board for a dual in-line memory module ("DIMM"), a circuit board or a circuit panel or a module connected to other components in a system. Mother board and so on. The circuit panel has contacts that are configured to electrically connect to the microelectronic package. In a particular embodiment, the circuit panel can include one of the elements having a thermal expansion coefficient ("CTE") of less than 12 parts per million ("ppm/° C.") per degree Celsius, wherein the first surface and the second The panel contacts at the surface are connected by through holes extending through the component. For example, the component can consist essentially of a semiconductor, glass, ceramic or liquid crystal polymer material.

The first microelectronic package 100A and the second microelectronic package 100B can be mounted to corresponding panel contacts 360, 362 exposed at the first surface 350 and the second surface 352 of the circuit panel 354. In the example shown in FIG. 7C, the first terminals 104-1 and 104-2 can be disposed at a location in one of the grids 105 on the first package 100A. The first terminals 104-1 and 104-2 of the second package 100B may also be disposed at a position within one of the grids 105 on the second package. Each grid of terminals can be completely filled, i.e., one terminal occupies each position of each grid. Or one or more locations per grid are not necessarily Occupied by a terminal. As shown in FIG. 7C, the grids may be aligned with one another in a spacing between the balls in the x and y orthogonal directions parallel to the surface 350 of the circuit panel, the spacing between the balls being no more than any two parallels on either package. The minimum spacing between one of the terminal rows. In a particular example, at least half of the locations of the grids of the first package and the second package can be aligned with each other in an x and y orthogonal direction parallel to the first surface of the circuit panel.

In a particular example, the grids can be aligned with one another in the x and y directions such that at least some of the first terminals on the first microelectronic package and the second microelectronic package overlap each other. As used herein, when the first package terminals "coincident" with each other at opposite surfaces of a circuit panel, the alignment may be within custom manufacturing tolerances, or may be less than each other in parallel with the first circuit panel surface and The tolerance between the inter-ball spacing is as described above in one of the tolerances of one of the inter-ball spacings in the x and y orthogonal directions of the surface of the second circuit panel.

As shown, the wiring within the circuit panel 354 electrically connects one of the terminals 104-1 of one of the terminals 104A of the package 100A to one of the terminals 104-1 of one of the terminals 104A of the package 100B. The dashed line 320 in Figure 7C schematically shows the wiring forming the electrical connections, as this particular view may be hidden in the particular view provided in Figure 7C. Similarly, the wiring within the circuit panel 354 electrically connects one of the terminals 104-2 of one of the terminals 104B of the package 100A with one of the terminals 104-2 of one of the terminals 104B of the package 100B, and the dotted line 322 in FIG. 7C schematically Shows the electrical interconnection between these terminals.

Further, in a particular example as shown in FIG. 7C, when there are two rows 104A, 104B containing the first terminal in each grid and the grids are aligned with each other within at least one inter-ball spacing, The circuit panel 354 is sealed The wiring required to connect one of the first terminals labeled "A" of 100A to one of the first terminals labeled "A" of package 100B can be relatively short. In particular, when each of the grids 105 on each package has two rows 104A, 104B and the grids 105 are aligned in the manner described above, the first row 104A of the first package 100A is parallel to the circuit panel. The x and y orthogonal directions of the first surface 350 are aligned with the second row 104B of the second package within a ball pitch, and the second row 104B of the first package 100A is parallel to the first of the circuit panels. The x and y orthogonal directions of surface 350 are aligned with the first row 104A of the second package within a ball pitch.

Therefore, the electrical length of the short circuit connecting the first terminal 104-1 of the first package 100A and the corresponding first terminal 104-1 of the second package 100B on the circuit board 354 can be less than that on each package. 7 times the minimum pitch of one of the first terminals, for example, less than 7 times the distance 150 between the rows 104A, 104B of the first terminal in FIG. 7B. For example, in other words, the connection is exposed to the first surface and the second surface of the circuit panel such that one of the first panel contact and the second panel contact is electrically interconnected with one of the conductors of one of the bus bars on the circuit panel The total combined length of the electrically coupled first panel contacts and the second panel contacts may be less than 7 times the minimum spacing of one of the panel contacts. In addition, the length of the short line of at least one of the electrical connectors between the first terminal of the first microelectronic package and the corresponding one of the first terminals of the second microelectronic package may be less than the first length One of the first terminals of the microelectronic package has a minimum pitch of 7 times. In a particular embodiment, when the first terminals are configured to carry the aforementioned command address bus signal, the connections are exposed at the first surface and the second surface of the circuit panel Electrically coupling the first panel contact and the second panel contact to one of the corresponding command address bus signals on the circuit panel to electrically couple the first panel contact and the second panel contact The total combined length of the conductive elements can be less than the minimum spacing of one of the panel contacts. In yet another example, the electrical length of the connector between the first terminal 104-1 of the first package 100A and the corresponding first terminal 104-1 of the second package 100B can be approximated to the circuit board. 354 is the same thickness 356 between the first surface 350 and the second surface 352.

Reducing the length of the electrical connectors reduces the length of the stubs in the circuit panel and the assembly, thereby contributing to improved electrical performance, such as reducing carrier transport by the first terminals and transmitting to the The settling time, ringing effect, jitter or intersymbol interference of the above-mentioned signals of the microelectronic components in both the package and the second package.

In addition, other benefits can be obtained, such as simplifying the structure of the circuit panel or reducing the complexity and cost of designing or manufacturing the circuit panel. That is, the connectors on the circuit panel may require fewer wiring layers to interconnect the first terminals of each package to the busbars on the circuit panel, such as the busbar or command of the carrier address information discussed above. Address bus.

In addition, it is sometimes possible to reduce the global routing layer of conductors required to route signals from the signals (eg, address information or command address bus signals) carried by the first terminals (ie, along a general The number of wirings that extend upward in parallel with at least one of the surfaces of one of the circuit panels. For example, a connection portion connecting one of the first pair of microelectronic packages 100A, 100B is connected to a different connection portion of one of the other microelectronic packages. For example, the number of such global routing layers between junctions II and III (FIG. 7D) on the microelectronic package may be reduced when constructing microelectronic packages attached to such global routing layers in accordance with the principles herein. . In particular, in some cases, the number of global routing layers required to route such signals along a circuit panel can be reduced to two or fewer routing layers. In a specific example, there may be a global routing between a connection point connecting one of the first microelectronic package and the second microelectronic package and a different connection point electrically connecting one of the at least one third microelectronic package 100A or 100B None of the above address or command address bus signals exceeds one routing layer. However, on the circuit panel, there may be more global routing layers for carrying signals other than the address or command address bus signals described above. Figure 7D illustrates a microelectronic assembly of a plurality of microelectronic packages, such as, for example, a DIMM or the like, having a circuit panel and a plurality of microelectronic packages mounted opposite the first and second opposing surfaces of the circuit panel. As shown in FIG. 7D, a plurality of pairs of microelectronic packages 100A, 100B can be connected to a bus bar 36 (eg, an address bus or command address bus on the circuit panel or board 354). The address signal or the command address bus signal is routed in at least one direction 143 between the connection locations I, II or III on the opposite side of the circuit panel. The signals of this bus bar 36 arrive at each pair of packages at slightly different times at the respective connection locations I, II or III. The at least one direction 143 can extend in one direction 142 transversely or orthogonally to at least one row 138 of the plurality of contacts on at least one of the microelectronic elements within each of the packages 100A or 100B. In this manner, in some cases, the signal conductors of the busbars 36 on the circuit panel 354 (ie, on the circuit panel 354 or within the circuit panel 354) may be parallel to the connection. One of the at least one row 138 of the contacts on one of the microelectronic components in one of the package 100A or 100B of the circuit panel is separated from each other in a direction 142. This configuration can help simplify the use of the circuit panel, particularly when the first terminals 104-1, 104-2 of each microelectronic package are disposed at positions within one or more rows extending in this direction 142. Routing the signal conductors of one or more global routing layers of the signal of the bus 36. For example, routing of command address bus signals on a circuit panel can be simplified when relatively few first terminals are placed at the same vertical layout location on each package. Thus, in the example shown in FIG. 5, only two first terminals 104 are disposed at the same vertical layout location on each package, such as the first terminal 104 configured to receive the address signals A3 and A1.

In an exemplary embodiment, the microelectronic assembly 354 can have a second microelectronic component 358 that can include a microelectronic package 100A configured to perform transfer to the assembly 354, At least some of the signals of 100B are buffered by one of the semiconductor wafers. In a particular embodiment, the second microelectronic component can be configured to primarily perform one of a logic function, such as a solid state drive controller, and one or more of the microelectronic components 358 in the microelectronic packages 100A, 100B Each may include a memory storage element such as a non-volatile flash memory. In one example, the second microelectronic component 358 can include a memory storage component configured to self-supervise the transfer of data to the microelectronic component 130 and dissipate data from the memory storage component 130. A dedicated processor, such as one of the central processing units of system 1500 (Fig. 19). Such a microelectronic component 358 comprising a solid state drive controller can be provided to a motherboard such as one of the systems of the system 1500 (eg, Figure 19) Direct memory access to one of the data busses on circuit panel 1502) and direct memory access from the data bus. In a particular embodiment, the microelectronic element 358 can have a buffering function. The microelectronic component 358 can be configured to facilitate providing components of the microelectronic component 130 of the microelectronic packages 100A, 100B relative to the microelectronic assembly 354 or external components of the system 1500 (FIG. 19). Impedance isolation.

In a particular embodiment, the first terminal 104 of the microelectronic package can be configured to carry information that controls an operational mode of the microelectronic component 101. More specifically, the first terminals can be configured to carry all of the set of command signals and/or clock signals transmitted to the microelectronic package 100. In an embodiment, the first terminals 104 can be configured to carry all of the command signals, address signals, and reservoir address signals and pulse signals transmitted from an external component to the microelectronic package 100, wherein The command signals include column address strobe, row address strobe, and write enable. In this embodiment, the first wafer can be configured to regenerate information that controls the mode of operation. Alternatively, or in addition, the first wafer can be configured to partially or fully decode information that controls the mode of operation of the microelectronic component. In this embodiment, each second wafer may or may not be configured to decode all of the address information, command information, or information that controls the mode of operation of one of the microelectronic components.

A microelectronic package with other terminal configurations can be provided. For example, in the microelectronic package 400 illustrated in Figure 8, four rows 404A, 404B, 404C, and 404D of terminals are disposed in a central region 112 of the substrate surface, the rows containing configurations configured to carry the commands Signal, address signal, reservoir address signal, and all of the clock signals used to sample the address signals One terminal. In another example (not shown), the first terminal of a microelectronic package can also be placed at three locations.

In the microelectronic package 500 illustrated in Figures 9A and 9B, a first terminal 504 is disposed at a location in a single row 505 disposed in a central region 512 of the substrate surface, the single row 505 being parallel to the microelectronic package The edges 516, 518 extend in one direction. Although the second terminals are shown in FIG. 9A, the second terminals are omitted for clarity in FIG. 9B.

In the particular example shown in Figure 9A, the minimum spacing between any two terminal rows on the substrate is disposed 552 between the adjacent rows 506B and 506C of the second terminals in the peripheral region 514B of the substrate surface. The width 554 of the central region is no more than three and a half times the minimum spacing 552 between the terminal rows 506B and 506C.

As further shown in FIG. 9B, the microelectronic component 530 in the microelectronic package 500 can have a single row of component contacts 538 on the face 534 of the microelectronic component. In this case, the internal electrical connection between the component contact 538 of the microelectronic package 500 and the first terminal 504 can be particularly short. For example, in the microelectronic package 500 shown in FIG. 9C, the connection between the component contact 538A and the first terminals 504 may in one case only or primarily be in the row 538A of the component contacts at the microelectronic component. One of the extensions 530 extends over the first direction 542. In another case, the connection between component contact 538B and the first terminals 504 may in one case extend only in one of the vertical directions of the contacts 538B such that at least some of the packages 500 are at least first Terminal 504 can at least partially overlap component contact 538 that electrically connects the contacts 538B.

FIG. 10 illustrates a microelectronic package 600 in accordance with one particular example in which microelectronic element 630 includes one of a plurality of vertically stacked electrically interconnected semiconductor wafers 632 and 634. In this case, the microelectronic element 630 includes one of the component contacts 636 having a substrate contact 640 that faces one of the first surfaces 610 of the substrate on one of the faces 638 and that is coupled to the substrate contacts 640. First semiconductor wafer 632. The microelectronic component also includes one or a plurality of second semiconductor wafers 634 overlying one side 642 of the first semiconductor wafer 632 opposite the first semiconductor wafer face 638, the face 642 being away from the first surface of the substrate 602 610. The one or more second semiconductor wafers 634 are electrically interconnected with the first semiconductor wafer 632. For example, as shown in FIG. 10, there are three vertically stacked second semiconductor wafers 634 with their equal faces overlapping each other.

In the microelectronic package 600 shown in FIG. 10, each of the first semiconductor wafer 632 and the second semiconductor wafer 634 can have a memory storage array function. In one example, each of the first semiconductor wafer and the second semiconductor wafer can be configured such that each of the semiconductor wafers implements more active devices to provide memory storage array functionality in addition to any other functionality. For example, each of the first semiconductor wafer and the second semiconductor wafer may include a memory storage array and all circuitry required to input data to and output data from the memory storage array. For example, when a memory storage array in each semiconductor wafer is writable, each of the semiconductor wafers can include circuitry configured to receive external data input from terminals of the package and configured to The data output of the semiconductor wafer is transferred to the circuitry of the terminals of the package. Therefore, every first semiconductor The chip 632 and each of the second semiconductor wafers 634 can be a dynamic random access memory ("DRAM") chip or can input and output data from the memory storage array in the semiconductor chip and receive the data and transmit the data. Other memory chips to one of the components external to the microelectronic package. In this case, in other words, there is no need to buffer the signals from the memory storage array in each DRAM wafer or other memory chip and the signals from the memory storage array by an additional semiconductor wafer in the microelectronic package.

Alternatively, in another example, the one or more semiconductor wafers 634 can implement more active devices to provide memory storage array functionality in addition to any other functionality, but the first semiconductor wafer 632 can be a different type Wafer. In this case, the first semiconductor wafer 632 can be configured (eg, designed, constructed, or built) to buffer the signal, ie, regenerate signals received at the terminals for transmission to the one or more second A semiconductor wafer 634, or a signal received from one or more of the second semiconductor wafers 634 for transmission to the terminals, or a signal transmitted in two directions: from the terminals to the one Or a plurality of second semiconductor wafers 634; and terminals from the one or more semiconductor wafers to the microelectronic package.

Alternatively, or in addition to generating a signal as described above, in an example, the first wafer in the composite microelectronic component can be configured to partially or fully decode information that controls the mode of operation of the microelectronic component. In a specific example, the first semiconductor wafer of the composite microelectronic component can be configured to partially or fully decode at least address information or command information received at the terminals (such as at the first terminals) One. The first wafer can be outputted The result of this partial or complete decoding is transmitted to the one or more second semiconductor wafers 634.

In a particular example, the first semiconductor wafer can be configured to buffer the address information or, in an example, buffer a command signal, an address signal, and a pulse signal transmitted to the one or more second semiconductor wafers. For example, the first semiconductor wafer 632 can be embodied with more active devices to provide a buffering function in addition to any other function in transmitting signals to other devices (eg, the one or more second semiconductor wafers 634). A buffer wafer. Next, the functional wafer of the one or more second semiconductor wafers may be reduced, the functional wafers having a memory storage array but omitting circuits common to the DRAM wafers, such as buffer circuits, decoders or pre-decoders or word lines Drive and more. In this case, the first wafer 632 can be used as a "master" wafer in the stack and control operations in each of the second semiconductor wafers 634. In a particular example, the second semiconductor wafers can be configured such that they are unable to perform the buffering function. In this case, the stacked configuration of the first semiconductor wafer and the second semiconductor wafer is configured such that a buffer function required in the microelectronic package can be performed by the first semiconductor wafer and cannot be configured by the stack Executing any of the semiconductor wafers of the second semiconductor wafer.

In any of the embodiments described herein, the one or more second semiconductor wafers can be implemented in one or more of the following technologies: DRAM, NAND flash memory, RRAM ("resistive RAM" or "Resistive random access memory"), static random access memory (SRAM), phase change memory ("PCM"), magnetic random access memory, for example, many Embodiments tunneling junction devices, spin torque RAM or content addressable memory, and the like.

10 further illustrates that the one or more second semiconductor wafers 634 extend in the direction of one of the thicknesses 652 between the first opposing face 638 and the second opposing face 642 thereof by the first semiconductor wafer 632. A through-via via ("TSV") 650 is electrically coupled to the first semiconductor wafer 632 by one of the specific examples of the microelectronic package 600. As shown in FIG. 10, in an example, the TSVs 650 can be electrically coupled to the component contacts 636 of the first semiconductor wafer 632 by, for example, a trace 654 extending along a face 638 of the first semiconductor wafer 632. connection. Although any electrical connection can be made between the first semiconductor wafer and the second semiconductor wafer in this manner, the connections are also sufficiently suitable for distributing power and ground to the first semiconductor wafer and the second semiconductor wafer.

For example, a TSV route connected to an internal circuit can be regenerated by a first semiconductor wafer 632 operating as one of the buffer elements and then transmitted to the one or more second semiconductor wafers. As further shown in FIG. 10, the microelectronic package can also include a through via 650 that extends partially or completely through one or more of the second semiconductor wafers 634. The TSV 650 is not necessarily directly connected to the substrate 602, but may terminate on circuitry included in the semiconductor wafer 632.

FIG. 11A further illustrates a microelectronic package 700 in accordance with a variation of the embodiment shown in FIG. In this case, the first semiconductor wafer 732 is interconnected with the substrate 702 in the same manner as described above with respect to FIG. However, one or more second semiconductor wafers 734 are through wire bonding The first semiconductor wafer 732 is electrically interconnected.

In the example shown in FIG. 11A, the second semiconductor wafers 734 are placed such that their front faces and contacts 731 face up, i.e., face away from the first semiconductor wafer 732. However, in another variation shown in FIG. 11B, another way in which the first semiconductor wafer 832 and the second semiconductor wafer 834 can be mounted together in a microelectronic package is to place each of the second semiconductor wafers 834. The front side and the contact member 831 are faced downward, that is, toward the substrate 602. In this manner, the contacts 831 can be electrically connected to the corresponding contacts 841 on the front side 838 of the first semiconductor wafer 832 via wire bonds 836. In this case, the contacts 841 can be electrically coupled to the component contacts 636 on the first semiconductor wafer 832 by, for example, traces 838 extending along the front side 838 of the first semiconductor wafer 832, where The connection between component contact 636 and the substrate contacts 640 is as described above with respect to FIG.

Figure 12 illustrates a microelectronic package in accordance with a further variation of the embodiment described above with respect to Figure 10, wherein the connection between the contacts of one or more of the second semiconductor wafer 934 and the first semiconductor wafer 932 can comprise Traces 936 extend along one or more edges of microelectronic element 930 (i.e., along the edges of semiconductor wafers 932, 934 within the microelectronic element). The electrical connections between the semiconductor wafers 932, 934 can further include traces 938, 940 extending along the front side of the first semiconductor wafer 932 and the second semiconductor wafer 934, respectively. As further shown in FIG. 12, the front side 942 of the second semiconductor wafer can face upwardly away from the substrate 602 or face down toward the substrate 602. Furthermore, in the above structure (FIGS. 10 to 11A), the first semiconductor The TSV within the wafer 932 may extend partially or completely through one of the thicknesses of the first semiconductor wafer 932, or some of the TSVs in the first semiconductor wafer 932 may extend partially through its thickness while other TSVs of the TSVs The thickness of the first semiconductor wafer 932 may extend completely.

FIG. 13A illustrates a microelectronic package in accordance with yet another variation of the embodiment described above with respect to FIG. 10, wherein a second semiconductor wafer 954 has a corresponding contact 948 that faces a face 950 of the first semiconductor wafer 952. Contact 946, such as contacts 946, 948, for example, joined together by a metal, bonding metal or other conductive material to form a flip chip connection between the first semiconductor wafer 952 and the second semiconductor wafer 954 .

Figure 13B illustrates a variation of the microelectronic package shown in Figure 13A. Unlike the package shown in FIG. 13A, the semiconductor wafer 964 that can be configured to reproduce or at least partially decode address information or other information (eg, regenerate signals for transmission to other semiconductor wafers in the package) is not positioned as Adjacent to the first surface 108 of the substrate 902. In this case, the semiconductor wafer 964 can instead be disposed at one of the locations of the package overlying one or more other semiconductor wafers. For example, as shown in FIG. 13B, the wafer 964 at least partially overlaps the semiconductor wafer 962 disposed adjacent the first surface 108 of the substrate 902 and at least partially overlies the semiconductor wafers 963A and 963B disposed on top of the semiconductor wafer 962. Or at least partially overlying the semiconductor wafer 962.

In one example, the semiconductor wafers 962, 963A, and 963B can comprise a memory storage array. In the examples described above, the wafers 962, 963A, and 963B can each be configured to buffer (eg, temporarily store) data written to or read from the wafer or both. Electricity road. Alternatively, the wafers 962, 963A, and 963B may be more limited in functionality and may be required to be configured to temporarily store data written to or read from the wafer or at least one other of the two. The wafers are used together.

The semiconductor wafer 964 can be electrically connected to the terminals of the microelectronic package via a conductive structure (eg, TSVs 972a and 972b (collectively referred to as TSV 972) that are connected to contacts exposed at the first surface 108 of the substrate 902) (eg, Connected to the grid in which the first terminals 904 and the second terminals 906 are disposed). The conductive structures (e.g., the TSVs 972) can pass through the contacts 938 on the wafer 964 and pass through the face 943 along the wafer 964 or along one of the opposing faces 931 of the wafer 963A or along the wafers 963A, 964 A conductor (not shown) extending over the faces 931, 943 is electrically coupled to the semiconductor wafer 964. As indicated above, the semiconductor wafer 964 can be configured to regenerate or at least partially decode signals or information received through the conductive structures (e.g., TSVs 972 such as TSVs 972a and 972b), and can be configured to be regenerated The at least partially decoded signal or information is transmitted to other wafers within the package, such as to the wafers 962, 963A, and 963B.

As further shown in FIG. 13B, the semiconductor wafers 962, 963A, and 963B can be extended through one, two, or three or more of a plurality of through-holes ("TSV") of the wafers. 972, 974, and 976 are electrically connected to the semiconductor wafer 964 and electrically connected to each other. Each of the TSVs can be electrically coupled to wiring within the package (eg, two or more conductive pads or traces of the semiconductor wafers 962, 963A, 963B, and 964). In a specific example, the signal or information may be from the base along a first subset of TSV 972A Board 902 is transferred to the wafer 964 and signals or information can be transmitted from the wafer 964 to the substrate along a second subset TSV 972B. In an embodiment, at least a portion of the TSVs 972 can be configured to transmit signals or information in either direction between the wafer 964 and the substrate 902 depending on the particular signal or information. In an example (not shown), the through vias may extend through all of the semiconductor wafers 962, 963A, and 963B, even though each of the through vias does not necessarily electrically connect through each of the semiconductor wafers through which they extend. thickness.

As further shown in FIG. 13B, a heat sink or heat sink 968, which may include a plurality of fins 971, may be thermally coupled to the semiconductor, such as through a thermally conductive material 969 such as a thermal adhesive, thermally conductive tallow or solder. One side of the wafer 964 (eg, one back 933 of the semiconductor wafer 964).

The microelectronic assembly 995 shown in FIG. 13B can be configured to operate as a memory module, the memory module being capable of transmitting a first terminal and a second terminal for the memory module on the substrate. A specified number of data bits are cyclically transmitted onto or from the microelectronic package to transmit the data bits. For example, the microelectronic assembly can be configured to transfer a number of data bits (such as 32 data bits, 64 data bits, or 96 data bits, etc.) to, for example, such The first terminal 904 and the second terminals 906 are electrically connected to or from one of the external components of the circuit panel. In another example, when the bit transferred to and from the package contains error correction code bits, the number of bits transferred to or from the package per cycle may be a different number, such as (for example) 36 bits, 72 bits or 108 bits. Other data widths than those specifically described herein are possible.

14, 15A and 15B illustrate a microelectronic package 1100 in accordance with a further variation of one or more of the above-described embodiments. As shown in FIG. 14, the package 1100 includes a first microelectronic component 1130 and a second microelectronic component 1131, each having a corresponding substrate contact 1140 that faces and is coupled to a first surface 1120 of the substrate 1102. Contact 1138. Then, some of the substrate contacts 1140 are electrically coupled to the first terminal 1142 in a central region 1112 of the second surface 1110 through, for example, conductive traces 1144. In some embodiments, some of the substrate contacts 1138 can be electrically coupled to the second terminal 1162 of one or more of the peripheral regions 1164 of the second surface.

This and other embodiments have more than one microelectronic component as described above. A multi-chip package can reduce the connection of a wafer therein to a circuit panel (eg, the package can be electrically and mechanically connected through a terminal array such as a ball grid array, a platform grid array, a pin grid array, etc.) The amount of area or space required for the printed wiring board. This connection space is particularly limited in small or portable computing devices such as "smart phones" or handheld devices that typically combine the functionality and wireless connectivity of a personal computer into a wider range. . Multi-chip packages are particularly useful for fabricating a large number of relatively inexpensive memories that can be used in a system, such as, for example, advanced high performance dynamic random access memory ("DRAM") chips (eg, DDR3 DRAM chips and their next generation). in).

In certain instances, the amount of area of the circuit panel required to connect the multi-chip package to the circuit panel can be reduced by providing a common terminal on the package through which at least some of the signals travel to the package Two or more wafers within or travel from the two or more wafers. Thus, in the example illustrated in Figures 14 and 15A-15B, corresponding contacts of a plurality of wafers within the package can be electrically coupled to a single common terminal of the package, the common terminal being configured to One of the components external to the package, such as a circuit panel (eg, a printed circuit board, external microelectronic component, or other component), is electrically coupled.

As in the above embodiment, the central region 1112 of the substrate surface 1110 has a width 1154 that is no more than three and a half times the minimum pitch 1152 between any two adjacent terminal rows 1142 on the package, wherein Each of the two adjacent rows has a plurality of terminals therein.

One of the axial planes 1150 extending in a direction orthogonal to one of the faces of the microelectronic elements extends in each row of the plurality of component contacts and the component contacts of the first microelectronic component 1130 and the second microelectronic component 1131 All of the rows 1138 extend in the same first direction that is centered. The axial plane intersects (extends through the central region) the central region of the substrate in a direction normal to the surface 1110. In one example, the axial plane can intersect the substrate along a line centered between adjacent edges 1134, 1135 of the microelectronic elements 1130, 1131. Referring to FIGS. 15A and 15B, one or more rows of the first terminals 1142 can be disposed in the central region and the adjacent edges 1134, 1135 of the first microelectronic component and the second microelectronic component as shown therein. In one of the regions aligned, or although not shown, one or more of the rows 1142 of the first terminals may overlap the first microelectronic component 1130 and the face 1136 of the second microelectronic component 1131. One or more. As in the above embodiment, there is no need to have a single line in the central area. Terminal 1142. Typically, there will be no more than four rows of terminals 1142 in the central region. As further shown in FIG. 14, the first microelectronic component and the second microelectronic component face 1136 can extend within a single plane 1146 that is parallel to the first surface 1120 of the substrate 1102.

16A-16B illustrate a microelectronic package 1200 in accordance with one variation of the embodiment illustrated in FIGS. 14, 15A-15B, except having microelectronic package 1100 as described above (FIG. 14, FIG. 15A to FIG. 15B) In addition to the first configuration and electrical interconnection of the first microelectronic component 1230 and the second microelectronic component 1231 in the package 1200, the microelectronic package 1200 further includes a third microelectronic component 1233 and a fourth microelectronic component 1235. . The third microelectronic component and the fourth microelectronic component can each implement more active devices to provide memory storage array functionality in addition to any other functionality. For example, the first microelectronic component and the second microelectronic component, the third microelectronic component 1233 and the fourth microelectronic component 1235 are coupled to the substrate and are flip-chip bonded to the substrate, such as described above with reference to FIG. 15A. The component contacts 1238 of the corresponding substrate contacts on one of the first surfaces 1120 (FIG. 14) are electrically interconnected with the terminals 1242 of the package.

As noted above, the first terminal 1243 of the microelectronic package can be disposed within a central region 1254 having a line that is no more than three and a half times the minimum pitch between the plurality of terminal rows. As further shown in FIG. 16A, the axis plane 1250 can be parallel to the first microelectronic component, the second microelectronic component, the third microelectronic component, and the fourth microelectronic component on the face 1236 of the package 1200. All rows 1238 of the component contacts are centered in all of the rows 1238. In the example shown in Figure 16A, the axis plane 1250 is parallel to it. The row 1242 having the first terminal extends in one of the directions extending in the first direction.

In a manner similar to that described above with respect to FIG. 14 and FIG. 15A through FIG. 15B, the faces 1236 of the microelectronic components 1230, 1231, 1233, and 1235 may be disposed within the package 1200 such that all of the faces 1236 are coplanar, That is, it extends in a single plane (i.e., such as a single plane 1146 as illustrated in Figure 14).

16B illustrates a possible signal assignment for a terminal on the package 1200 in which a first terminal is disposed in one or more rows 1242 of the central region and a second terminal 1244 is disposed in a plurality of regions proximate to the The locations of the peripheral edges 1260, 1261, 1262, and 1263 of the package. In this case, some of the second terminals may be disposed at locations such as within one of the grids of grids 1270, and some of the second terminals may be disposed at locations such as within one of the grids of grids 1272. Additionally, some of the second terminals may be disposed at locations within a grid such as grid 1274, and some of the second terminals may be disposed at a location within grid 1276.

Again, as shown in FIG. 16B, the signal class assignment of the second terminal in grid 1274 can be symmetric about vertical axis 1250, and the signal class assignment of the second terminal in grid 1276 can be symmetric about the vertical axis 1250. As used herein, if two signal classes are assigned in the same assigned class, even if the digital index is within the class, the signal class assignments may be symmetric with respect to each other. An exemplary signal class assignment can include a data signal, a data strobe signal, a data strobe complementary signal, and a data mask signal. In a particular example, in grid 1274, even if the second terminals with signal assignments DQSH# and DQSL# have different signal assignments, the second terminals are also related to the vertical axis 1250. Symmetrical with respect to its equal signal class assignment (which is complementary to the data strobe).

As further shown in FIG. 16B, the assignment of the data signal to the spatial position of the second terminal on the microelectronic package (such as for, for example, data signals DQ0, DQ1, ...) may have modulo X symmetry about the vertical axis 1250. . The modulo X symmetry can help maintain signal integrity in one of the assemblies 300 or 354, such as shown in Figures 7C and 7D, in Figures 7C and 7D, one or more pairs of first and second packages Mounted to a circuit panel opposite each other, and the circuit panel is electrically coupled to pairs of corresponding second terminals of the first and second packages of each of the oppositely mounted package pairs. When the signal assignment of the terminal has "mode X symmetry" with respect to one axis, the terminal carrying the signal having the same value "modulo X" is placed at a position symmetrical about the axis. Thus, in such assembly 300 or 354, such as in Figures 7C, 7D, modulo X symmetry may allow electrical connection through the circuit panel such that one of the terminals of the first package DQ0 is electrically connected to the same through the circuit panel The terminal DQ8 of the second package of the value of the modulo X (in this case, the X-series 8) is such that the connection can be made in a direction that is substantially erected through (i.e., normal to) the thickness of the circuit panel.

In an example, "X" can be a value of 2 ⁿ (n power of 2), where n is greater than or equal to 2, or X can be 8 x N, N is 2 or greater. Thus, in one example, X can be equal to half a byte (4 bits), a byte (8 bits), multiple bytes (8 x N, N series 2 or greater), one The number of bits in a block (32 bits) or multiple blocks. In this manner, in one example, when there is modulo 8 symmetry as shown in FIG. 16B, the signal assignment in the grid 1274 configured to carry one of the packaged data signals DQ0 to package the terminal DQ0 is related to the vertical axis 1250. The signal assignment modulo 8 is symmetric with the other package terminal DQ8 configured to carry the data signal DQ8. In addition, the same applies to the signal assignment of the package terminals DQ0 and DQ8 in the grid 1276. As further shown in FIG. 16B, the signal assignments of package terminals DQ2 and DQ10 in the grid 1274 have symmetry about the mode 8 of the vertical axis, and are equally applicable to package terminals in grid 1276. The modulo 8 symmetry, such as described herein, can be seen in the grids 1274, 1276 with respect to each of the signal assignments of the package terminals DQ0 through DQ15.

It is important to note that although not shown, the modulus "X" can be a value other than 2 ⁿ (n power of 2) and can be any value greater than two. Therefore, the modulo X based on its symmetry may depend on how many bits are present in the data size of one of the packages constructed or configured. For example, when the data size is 10 bits instead of 8 bits, the signal assignments may have modulo 10 symmetry. The modulus X may have this value even when the data size has an even number of bits.

17A-17B illustrate a microelectronic package 1300 having a central region in which a row 1341 containing a first terminal is disposed, in accordance with one variation of the embodiment 1200 described above with respect to FIGS. 16A and 16B. One of the substrate surfaces 1310 of 1312. As shown therein, the first microelectronic component 1330 and the second microelectronic component 1331 are disposed on the substrate in a manner similar to the configuration of the microelectronic components 1130, 1131 of the microelectronic package 1100 (FIGS. 14, 15A-15B). At 1302, the component contacts on the microelectronic components are disposed at locations within the row 1338 that extend in the same first direction 1342. However, as shown in FIG. 17A, the third microelectronic element 1332 and the fourth microelectronic element 1333 have component contacts disposed at locations within the row 1340, the rows 1340 being transverse to the first direction 1342. One direction 1344 extends along the faces of the microelectronic elements 1332, 1333. Typically, the other direction 1344 is perpendicular to the first direction 1342.

As further shown in Figures 17A-17B, each of the microelectronic elements 1330, 1331, 1332, and 1333 typically have the same direction extending in the same direction as the one or more rows of contacts on the respective microelectronic element. Two first parallel edges 1360 and two second parallel edges 1362 extending transversely to one of the directions in which the first edges extend. In some cases, the first edge 1360 of a respective microelectronic component can have a length that is greater than the second edge 1362 of the microelectronic component. However, in other cases, the second edges 1362 can have a length greater than the first edges 1360. In the particular package shown in FIG. 17A, any one of the first edges 1360 of at least one of the microelectronic elements 1330, 1331, 1332, or 1333 and the plane 1370 of the face of the microelectronic element is The edge 1360 of another microelectronic component within the package 1300 intersects. As shown in Figure 17A, the axial plane 1370 containing the edge 1360 of the microelectronic element 1333 extends in direction 1344 and intersects the edge 1360 of the microelectronic element 1330 within the package. In the example shown in Figure 17A, the plane 1370 intersects only the edge 1360 of one of the other microelectronic components within the package. The microelectronic elements can be configured to include a first edge 1360 of one of the microelectronic elements 1330, 1331, 1332, or 1333 and normal to a plane 1370 of the face of the microelectronic element and the package 1300 The edge 1360 of another microelectronic component within it intersects.

Moreover, as further shown in FIG. 17A, the central region 1312 can be further limited. In particular, Figure 17A shows that there is a minimal rectangular area 1372 on the surface 1310 of the substrate 1302 that will accommodate the Microelectronic components 1330, 1331, 1332, 1333 disposed on the substrate surface 1310, and the first microelectronic component 1330, the second microelectronic component 1331, the third microelectronic component 1332, and the fourth microelectronic component None of the faces of 1333 extend beyond the rectangular area 1372. In the microelectronic package 1300 depicted in Figures 17A-17B, the central region 1312 does not extend beyond either edge of the rectangular region 1372. 17B further illustrates a possible configuration of one of the terminals within the microelectronic package 1300 in which the first terminals 1341 are disposed between opposite edges 1316, 1318 of the package (ie, orthogonal In one of the opposite edges 1316, 1318) of the package, spans within a central region 1312 that is no more than one-half and a half times the minimum pitch between two adjacent rows of the closest adjacent ones of the terminals of the package. The peripheral region occupies the remaining area of the surface 1310 of the substrate 1302 to span the width 1356, 1357 between the edge of the central region and the opposite edges 1316, 1318 of the package, respectively.

Figure 18A illustrates a microelectronic package 1400 in accordance with one variation of one or more of the above-described embodiments. In this case, the substrate can be omitted such that the microelectronic package 1400 can be in the form of a microelectronic component 1430 having a package comprising an electrically conductive redistribution layer overlying the front side 1428 of the overlay microelectronic component 1430. structure. The redistribution layer has conductive metal vias 1440 extending through one of the dielectric layers 1442 of the package to the contacts 1438 of the microelectronic component. The redistribution layer can include a terminal 1446 and a trace 1448 electrically connected to the terminals 1446 such that the terminals pass through, for example, the metal vias 1440 or the metal vias 1440 and the conductive traces 1448 and the like Contact 1438 is electrically connected. In this case, the package may be referred to as "having Wafer-level packaging of repeated distribution layers."

18B illustrates that the microelectronic package 1400 is similar to the one or more rows 1450 of the second terminal that can be disposed on one or more of the edges 1432, 1434 of the microelectronic component 1430 that extend beyond the dielectric layer 1442. A microelectronic package 1410. In this case, the package 1410 may be referred to as a "fan-out wafer level package having a redistribution layer thereon."

Each of the above variations and embodiments may also be applicable to the package shown in FIG. 18A or FIG. 18B, and the above-described assembly shown and described above with respect to FIG. 7C may be combined with the microelectronic package shown in FIG. 18A or FIG. 18B. .

The above structure can be used to construct a diversity electronic system. For example, as shown in FIG. 19, system 1500 in accordance with a further embodiment of the present invention includes a microelectronic package or structure 1506 as described above in connection with other electronic components 1508 and 1510. In the depicted example, component 1508 can be a semiconductor wafer or microelectronic package, while component 1510 is a display screen, although any other components can be used. Of course, although only two additional components are depicted in FIG. 19 for clarity of illustration, the system can include any number of such components. Structure 1506 as described above can be, for example, a microelectronic package as discussed above in connection with any of the above-described embodiments. In a further variation, more than one package may be provided and any number of such packages may be used. Package 1506 and components 1508 and 1510 are mounted in a common housing 1501 that is schematically depicted in phantom, and electrically interconnected to each other as needed to form the desired circuitry. In the exemplary system shown, the system includes a circuit panel 1502, such as a flexible printed circuit panel or circuit board, and the circuit panel includes a plurality of conductors 1504 interconnecting the components to each other, only depicted in FIG. One of the conductors 1504. However, this is merely exemplary; any suitable structure for making electrical connectors can be used. The housing 1501 is depicted as being usable, for example, in a portable housing of the type of a cellular telephone or a personal digital assistant, and the screen 1510 is exposed at the surface of the housing. If the structure 1506 includes a photosensitive element such as an imaging wafer, a lens 1511 or other optical device for routing light to the structure may also be provided. Moreover, the simplified system shown in FIG. 19 is exemplary in nature; other systems including systems (such as desktops, routers, etc.) that are generally considered to be fixed structures can be fabricated using such structures.

The various features of the above-described embodiments of the invention may be combined in other ways than those specifically described above without departing from the scope or spirit of the invention. The present invention is intended to cover all such combinations and variations of the embodiments of the invention described above.

11‧‧‧Semiconductor wafer

12‧‧‧Microelectronics package

12A‧‧‧ package

12B‧‧‧Package

12C‧‧‧ package

12D‧‧‧ package

12E‧‧‧ package

12F‧‧‧ package

14‧‧‧

16‧‧‧First perimeter edge

18‧‧‧

20‧‧‧Package substrate

22‧‧‧Second perimeter edge

24‧‧‧Central area

26‧‧‧Component contacts

28‧‧‧ Surface of semiconductor wafer

30‧‧‧ Wire bonding

32‧‧‧Adhesive layer

34‧‧‧Circuit panel

36‧‧‧Command address bus

38‧‧‧assembly

40‧‧‧ Direction

42‧‧‧ Direction

100‧‧‧Microelectronics package

100A‧‧‧First microelectronic package

100B‧‧‧Second microelectronic package

101‧‧‧Microelectronic components

102‧‧‧Substrate

104‧‧‧First terminal

104-1‧‧‧First terminal

104-2‧‧‧First terminal

104A‧‧‧

104B‧‧‧

105‧‧‧Grid

106‧‧‧second terminal

106‧‧‧second terminal

106A‧‧‧

106B‧‧‧

108‧‧‧The first surface of the substrate

110‧‧‧Second relative surface/substrate surface

112‧‧‧The central area of the second surface

114A‧‧‧First surrounding area

114B‧‧‧Second surrounding area

116‧‧‧ first relative edge

118‧‧‧ second relative edge

120‧‧‧Substrate surface / first opposite surface

130‧‧‧Microelectronic components

132‧‧‧Component contacts

134‧‧‧ Faces of microelectronic components

135‧‧‧ terminals

136‧‧‧Substrate contacts

137‧‧‧terminal

138‧‧‧First terminal

139‧‧‧ second line

140‧‧‧Axis plane / central axis

142‧‧‧ first direction

143‧‧‧Vertical/second direction

144‧‧‧ midline

145‧‧‧Redistributed contacts

146‧‧‧ peripheral edge

147‧‧‧Redistributed contacts

148‧‧‧ peripheral edge

150‧‧‧Minimum spacing

151‧‧‧ peripheral edge

152‧‧‧Width

153‧‧‧ peripheral edge

154A‧‧‧Connecting components

154B‧‧‧Connecting components

192‧‧‧second contact

230‧‧‧Microelectronic components

238‧‧‧

240‧‧‧Axis plane

300‧‧‧Microelectronics assembly

310‧‧‧Substrate surface

312‧‧‧Central area

320‧‧‧ dotted line

322‧‧‧dotted line

330‧‧‧Microelectronic components

332‧‧‧Contact pad

338‧‧‧

339‧‧‧

350‧‧‧ Relative to the surface of the first surface/circuit panel

352‧‧‧ relative second surface

354‧‧‧ circuit panel

356‧‧‧ thickness between the first surface and the second surface

358‧‧‧Second microelectronic components

360‧‧‧ Panel contacts

362‧‧‧ Panel contacts

400‧‧‧Microelectronics package

404A‧‧‧

404B‧‧‧

404C‧‧‧

404D‧‧‧

500‧‧‧Microelectronics package

500A‧‧‧Microelectronics package

500B‧‧‧Microelectronics package

504‧‧‧First terminal

505‧‧‧

506A‧‧‧

506B‧‧‧

506C‧‧‧

512‧‧‧Central area

514A 514B‧‧‧ Surrounding area

Edge of 516‧‧

518‧‧‧ edge

530‧‧‧Microelectronic components

534‧‧‧ Faces of microelectronic components

538‧‧‧Component contacts

538A‧‧‧

538B‧‧‧Contacts

542‧‧‧First direction

552‧‧‧ spacing

554‧‧‧Width of the central area

556‧‧‧Width of the central area

600‧‧‧Microelectronics package

602‧‧‧Substrate

610‧‧‧ first surface

630‧‧‧Microelectronic components

632‧‧‧First semiconductor wafer

634‧‧‧Second semiconductor wafer

636‧‧‧Component contacts

638‧‧‧ first opposite

640‧‧‧Substrate contacts

642‧‧‧ second opposite

650‧‧‧through through hole

652‧‧‧ Thickness between the first opposing face and the second opposing face

654‧‧‧ Traces

656‧‧‧ Thickness between the first opposing face and the second opposing face

700‧‧‧Microelectronics package

702‧‧‧Substrate

731‧‧‧Contacts

732‧‧‧First semiconductor wafer

734‧‧‧Second semiconductor wafer

800‧‧‧Microelectronics package

802‧‧‧ substrate

831‧‧‧Contacts

832‧‧‧First semiconductor wafer

834‧‧‧Second semiconductor wafer

836‧‧‧ Wire bonding

838‧‧‧Front of the first semiconductor wafer

841‧‧‧Contacts

902‧‧‧Substrate

904‧‧‧First terminal

906‧‧‧second terminal

930‧‧‧Microelectronic components

Opposite to the 931‧‧‧ wafer

932‧‧‧First semiconductor wafer

933‧‧‧The back of the semiconductor wafer

934‧‧‧Second semiconductor wafer

936‧‧‧ Traces

938‧‧‧ Traces

940‧‧‧ Traces

942‧‧‧The front side of the second semiconductor wafer

943‧‧‧ Face of the wafer

946‧‧‧Contacts

948‧‧‧Contacts

950‧‧‧ Face of the first semiconductor wafer

952‧‧‧First semiconductor wafer

954‧‧‧Second semiconductor wafer

962‧‧‧Semiconductor wafer

963A‧‧‧Semiconductor wafer

963B‧‧‧Semiconductor wafer

964‧‧‧Semiconductor wafer

968‧‧‧ radiator

969‧‧‧thermal materials

971‧‧‧ wing

972A‧‧‧through through hole

972B‧‧‧through through hole

974‧‧‧through through hole

976‧‧‧through through hole

995‧‧‧Microelectronics assembly

1100‧‧‧Microelectronics package

1102‧‧‧Substrate

1110‧‧‧ second surface

1112‧‧‧The central area of the second surface

1120‧‧‧ First surface of the substrate

1130‧‧‧First microelectronic components

1131‧‧‧Second microelectronic components

1134‧‧‧ Adjacent edges of microelectronic components

1135‧‧‧Adjacent edges of microelectronic components

1136‧‧‧ Surface of microelectronic components

1138‧‧‧Substrate contacts

1140‧‧‧Substrate contacts

1142‧‧

1144‧‧‧ conductive traces

1146‧‧‧ single plane

1150‧‧‧Axis plane

1152‧‧‧Minimum spacing

1154‧‧‧Width of the central area

1162‧‧‧second terminal

1164‧‧‧ surrounding area

1200‧‧‧Microelectronics package

1230‧‧‧First microelectronic components

1231‧‧‧Second microelectronic components

1233‧‧‧ Third microelectronic component

1235‧‧‧4th microelectronic component

1236‧‧‧Package surface

1238‧‧‧

1242‧‧‧The first terminal trip

1243‧‧‧First terminal

1244‧‧‧second terminal

1250‧‧‧Axis plane

1254‧‧‧Central area

1260‧‧‧The peripheral edge of the package

1261‧‧‧The peripheral edge of the package

1262‧‧‧The peripheral edge of the package

1263‧‧‧The peripheral edge of the package

1270‧‧‧ Grid

1272‧‧‧Grid

1274‧‧‧ Grid

1276‧‧‧Grid

1300‧‧‧Microelectronics package

1302‧‧‧Substrate

1310‧‧‧ substrate surface

1312‧‧‧Central area

1316‧‧‧The opposite edge of the package

1318‧‧‧ The opposite edge of the package

1330‧‧‧First microelectronic components

1331‧‧‧Second microelectronic components

1332‧‧‧ Third microelectronic components

1333‧‧‧4th microelectronic component

1334‧‧‧

1338‧‧‧

1340‧‧

1341‧‧‧First terminal

1342‧‧‧First direction

1344‧‧ Direction

1356‧‧‧ Width between opposite edges

1357‧‧‧ Width between opposite edges

1360‧‧‧first parallel edge

1362‧‧‧second parallel edge

1370‧‧‧ Plane

1372‧‧‧Rectangular area

1400‧‧‧Microelectronics package

1410‧‧‧Microelectronics package

1428‧‧‧ Positive side of microelectronic components

1430‧‧‧Microelectronic components

4132‧‧‧ Edge of microelectronic components

1434‧‧‧ Edge of microelectronic components

1438‧‧‧Contacts

1440‧‧‧conductive metal through hole

1442‧‧‧ dielectric layer

1446‧‧‧ Terminal

1448‧‧‧ Traces

1450‧‧‧

1500‧‧‧ system

1501‧‧‧ Shell

1502‧‧‧ circuit panel

1504‧‧‧Conductor

1506‧‧‧Structure/package

1508‧‧‧Electronic components

1510‧‧‧Electronic components/screens

1511‧‧‧ lens

Figure 1 is a cross-sectional view illustrating one of the conventional microelectronic packages containing a DRAM wafer.

2 is a diagram illustrating a circuit panel and a microelectronic assembly (eg, a DIMM module) of a plurality of microelectronic packages mounted to the first opposing surface and the second opposing surface of the circuit panel. Schematic diagram.

3 is a cross-sectional view further illustrating one electrical interconnection, such as between a first microelectronic package and a second microelectronic package and a circuit panel, in one of the assemblies shown in FIG. 2.

Figure 4 is a further illustration of the first of the assemblies shown in Figure 2 One of the electrical interconnections between the microelectronic package and the second microelectronic package is a plan view.

5 is a diagrammatic plan view of one of a terminal configuration and signal assignment in a microelectronic package in accordance with an embodiment of the present invention.

Figure 6A is a cross-sectional view taken through line 6A-6A of Figure 5, which further illustrates the microelectronic package shown in Figure 5.

6B is a plan view further illustrating one of the possible configurations and contact types of one of the component contacts on a microelectronic component in one of the microelectronic packages in accordance with any of the embodiments claimed herein, in FIGS. 5 and 6A. This embodiment is shown.

6C is a plan view further illustrating one of the possible configurations and contact types of one of the component contacts on a microelectronic component in one of the microelectronic packages in accordance with any of the embodiments claimed herein, in FIGS. 5 and 6A. This embodiment is shown.

7A is a plan view further illustrating another possible configuration of component contacts of a microelectronic component in a microelectronic package in accordance with the embodiment of FIGS. 5 and 6A.

Figure 7B is a plan view further illustrating one of the configurations of the terminals in accordance with the embodiment shown in Figures 5 and 6A.

7C is a cross-sectional view of a microelectronic package and a first microelectronic package and a second microelectronic package electrically interconnected with the microelectronic assembly, in accordance with an embodiment of the present invention.

7D illustrates a microelectronic package (eg, a memory) including a circuit panel and electrically connected to the circuit panel, in accordance with an embodiment of the present invention. A schematic diagram of one of the microelectronic assemblies of a module, etc.).

Figure 8 is a plan view showing an alternative configuration of one of the terminals on a microelectronic package in accordance with one variation of the embodiment shown in Figures 5 and 6A.

9A is a plan view and FIG. 9B is a cross-sectional view taken through line 9B-9B of FIG. 9A, which illustrates a microelectronic package in accordance with a variation of the embodiment shown in FIGS. 5 and 6A.

Figure 9C is a plan view showing one of the arrangement of component contacts and electrical connections between a microelectronic component and a substrate in one embodiment of a microelectronic package as shown in Figures 9A-9B.

Figure 10 is a cross-sectional view illustrating one of the microelectronic packages of a stacked electrical connection assembly including a semiconductor wafer in accordance with an embodiment of the present invention.

Figure 11A is a cross-sectional view illustrating one of the microelectronic packages of a stacked electrical connection assembly including a semiconductor wafer in accordance with an embodiment of the present invention.

Figure 11B is a cross-sectional view illustrating one of the microelectronic packages of a stacked electrical connection assembly including a semiconductor wafer in accordance with an embodiment of the present invention.

Figure 12 is a cross-sectional view illustrating one of the microelectronic packages of a stacked electrical connection assembly including a semiconductor wafer in accordance with an embodiment of the present invention.

Figure 13A is a cross-sectional view illustrating one of the microelectronic packages of a stacked electrical connection assembly including a semiconductor wafer in accordance with an embodiment of the present invention.

Figure 13B illustrates the inclusion of a half in accordance with an embodiment of the present invention. A cross-sectional view of one of the microelectronic packages of one of the stacked electrical connection assemblies of the conductor wafer.

14 is a cross-sectional view illustrating one embodiment of a microelectronic package including one of a first microelectronic component and a second microelectronic component each having an element contact that faces and is coupled to a corresponding substrate contact.

Figure 15A is a diagrammatic plan view showing one of the signal assignments of the terminals on a microelectronic package in accordance with the embodiment shown in Figure 14, wherein Figure 14 is a cross-sectional view taken through line 14-14 of Figure 15A.

Figure 15B is a plan view further illustrating the possible placement of one of the terminals on the package of Figures 14 and 15A with respect to one of the first microelectronic component and the second microelectronic component therein.

16A is a plan view showing another embodiment of a microelectronic package in which one of a first microelectronic component, a second microelectronic component, a third microelectronic component, and a fourth microelectronic component are separated from each other on a substrate. .

Figure 16B is a plan view showing one of the possible configurations and signal assignments of the terminals on the microelectronic package in accordance with the embodiment shown in Figure 16A.

17A illustrates a microelectronic package in which a first microelectronic component, a second microelectronic component, a third microelectronic component, and a fourth microelectronic component having a needle wheel configuration on a substrate are separated from each other. A plan view of another embodiment.

Figure 17B is a plan view showing one of the possible configurations and signal assignments of the terminals on the microelectronic package in accordance with the embodiment shown in Figure 17A.

Figure 18A is a cross-sectional view of one of the wafer level microelectronic packages in accordance with one variation of the embodiment shown in Figures 5 and 6A.

Figure 18B is a cross-sectional view illustrating one of the fan-out wafer level microelectronic packages in accordance with one variation of the embodiment shown in Figure 18A.

Figure 19 is a schematic cross-sectional view of one of the systems illustrating an embodiment of the present invention.

100A‧‧‧First microelectronic package

100B‧‧‧Second microelectronic package

104-1‧‧‧First terminal

104-2‧‧‧First terminal

105‧‧‧Grid

300‧‧‧Microelectronics assembly

310‧‧‧Substrate surface

312‧‧‧Central area

320‧‧‧ dotted line

322‧‧‧dotted line

350‧‧‧ Relative to the surface of the first surface/circuit panel

352‧‧‧ relative second surface

354‧‧‧ circuit panel

356‧‧‧ thickness between the first surface and the second surface

360‧‧‧ Panel contacts

362‧‧‧ Panel contacts

Claims (31)

A microelectronic package comprising: a microelectronic component having a memory storage array function, the microelectronic component having one or more rows of component contacts, each row extending along a side of the microelectronic component in a first direction, Having a plane extending normal to the face of the microelectronic element along a line extending in the first direction intersecting the face of the microelectronic element and centered relative to the one or more rows of component contacts; a substrate a plurality of substrate contacts having a first opposing surface and a second opposing surface and exposed to the component contacts and coupled to the component contacts; a plurality of rows of parallel terminals, etc. in the first side Extending upwardly and exposed to the second surface of the substrate, the terminals are electrically connected to the substrate contacts and configured to connect the microelectronic package to a component external to the microelectronic package, the terminals comprising a first terminal exposed in a central region of the second surface of the substrate, the first terminals configured to be carried by a circuit within the package for storage from a memory Determining address information of an addressable memory location among all available addressable memory locations within the microelectronic component, and wherein the central region is along the substrate in a second direction transverse to the first direction The second surface has a width, the width of the central region being no greater than three and a half times the minimum spacing between any two adjacent rows of parallel rows of the rows, and the axial plane intersecting the central region. The microelectronic package of claim 1, wherein the microelectronic component implements more active devices to provide memory storage array functionality in addition to any other functionality. The microelectronic package of claim 1, wherein the first terminals are configured to carry all of the address information that can be used by the circuitry within the package to determine the addressable memory location. The microelectronic package of claim 1, wherein the first terminals are configured to carry information that controls an operational mode of the microelectronic component. The microelectronic package of claim 4, wherein the first terminals are configured to carry all of the command signals transmitted to the microelectronic package, the command signals being write enable signals, column address strobe signals, and Line address strobe signal. The microelectronic package of claim 1, wherein the first terminals are configured to carry a clock signal transmitted to the microelectronic package, the microelectronic package configured to use the clock signals for sampling to be received The signal at the terminals carrying the address information. The microelectronic package of claim 1, wherein the first terminals are configured to carry all of the bank address signals transmitted to the microelectronic package. The microelectronic package of claim 1, wherein the first terminals are disposed in no more than two rows of the terminal rows. The microelectronic package of claim 1, wherein the first terminals are disposed in a single row of the terminal rows. The microelectronic package of claim 9 wherein the component contacts connected to the first terminals are disposed within a single row of component contacts. The microelectronic package of claim 1, wherein the component contacts comprise redistribution contacts exposed at a front side of the microelectronic component, each redistribution contact passing through at least one of a trace or a via and the micro One of the electronic component contact pads is electrically connected, at least some of the redistributable contacts being displaced from the component contacts along the face of the microelectronic component in at least one direction. The microelectronic package of claim 1, wherein the substrate has a first opposing edge and a second opposing edge each extending between the first opposing surface and the second opposing surface, the first opposing edge and the second opposing An edge extending in the first direction, the second surface having a first peripheral region and a second peripheral region respectively adjacent to the first edge and the second edge, wherein the central region causes the first peripheral region to Separating the second peripheral regions, the terminals including a plurality of second terminals exposed to the second surface in at least one of the peripheral regions, at least some of the second terminals configured to carry Information other than address information. The microelectronic package of claim 12, wherein at least some of the second terminals are configured to carry a data signal. The microelectronic package of claim 1, wherein the microelectronic component comprises a first semiconductor wafer having a contact thereon coupled to the substrate contacts and the first of the first semiconductor wafer overlying the first semiconductor wafer At least one second semiconductor wafer on one side of the surface and electrically interconnected with the first semiconductor wafer. The microelectronic package of claim 14, wherein the first wafer is configured to The first terminals receive at least some of the address information and generate the at least some address information for transmission to the at least one second wafer, and the at least one second chip implements more active devices to provide Memory storage array function other than other functions. The microelectronic package of claim 14, wherein the first terminals are configured to carry information that controls an operational mode of the microelectronic component, and the first wafer is configured to perform at least one of: regenerating Or at least partially decoding the information that controls the mode of operation. The microelectronic package of claim 15, wherein the first wafer comprises a plurality of through vias electrically connecting the at least one second wafer to the first wafer. The microelectronic package of claim 15 wherein at least some of the electrical interconnections between the first wafer and the at least one second wafer are performed by wire bonding. The microelectronic package of claim 15, wherein the at least one second wafer passes through a second contact member that is exposed to a surface of the second wafer and that is connected to the first contact exposed at a surface of the first wafer. A flip-chip electrical interconnect is electrically interconnected with the first wafer, the surface of the first wafer facing away from the first surface of the substrate. The microelectronic package of claim 19, wherein the first wafer is configured to buffer at least some of the address information received at the first terminals for transmission to each second wafer, and each second wafer The information is not configured to buffer the address information for transmission to the first wafer and another wafer of the second wafer. The microelectronic package of claim 19, wherein the first wafer is configured to at least partially decode the address information received at the first terminals for transmission Up to each second wafer, and each second wafer is not configured to fully decode the address information. The microelectronic package of claim 21, wherein the second semiconductor wafer is a plurality of stacked second semiconductor wafers. The microelectronic package of claim 14, wherein at least some of the first wafer and the at least one second wafer are electrically connected to each other by a plurality of through vias. The microelectronic package of claim 14, wherein at least one of the at least one second wafer is configured to perform at least one of: partially or completely decoding information received at one of the contacts, or regenerating the received The information at the contact is transmitted to at least one of the first wafer or the other of the at least one second wafer. The microelectronic package of claim 14, wherein at least some of the electrical interconnections between the first wafer and the second wafer are conducted through conductive traces extending along at least one edge of the microelectronic component. The microelectronic package of claim 14, wherein at least some of the electrical interconnections between the first wafer and the second wafer are performed by wire bonding, one of the at least one second wafer facing away from the first a wafer, and at least some of the wire bonds connect the first wafer to a contact exposed at the face of the at least one second wafer. The microelectronic package of claim 26, wherein at least some of the electrical interconnections between the first wafer and the second wafer are performed by wire bonding, one of the at least one second wafer facing the first a wafer, and at least some of the wire bonds are such that the first wafer is exposed to the at least one The contacts at the face of the two wafers are connected. The microelectronic package of claim 14, wherein at least one of the first wafers or the at least one second wafer comprises a dynamic random access memory ("DRAM") storage array. The microelectronic package of claim 14, wherein at least one of the first wafers or the at least one second chip is implemented in a NAND flash memory, a resistive RAM (RRAM), a static random access memory (SRAM) , phase change memory (PCM), magnetic random access memory (MRAM), spin torque RAM or content addressable memory technology. A microelectronic package comprising: a microelectronic component having a memory storage array function, the microelectronic component having one or more rows of component contacts, each row extending along a side of the microelectronic component in a first direction, Having a plane extending normal to the face of the microelectronic element intersecting the face of the microelectronic element along a line extending in the first direction and centered with respect to the one or more rows of component contacts; a substrate Having a first opposing surface and a second opposing surface and a plurality of substrate contacts exposed to the component contacts and coupled to the component contacts at the first surface; a plurality of rows of parallel terminals exposed to the At the second surface of the substrate and extending in the first direction, the terminals are electrically connected to the substrate contacts and configured to connect the microelectronic package to one of the components of the microelectronic package, such The terminal includes a central region exposed to the second surface of the substrate a first terminal in the domain, the first terminal configured to be carried by circuitry within the package to determine an addressable location from all available addressable memory locations of a memory storage array of the microelectronic component a majority of the address information of the memory location, and wherein the central region has a width along the second surface of the substrate in a second direction transverse to the first direction, the width of the central region being no greater than One-half and a half of the minimum spacing between any two adjacent rows of parallel rows of the rows, and the axial plane intersects the central region. The microelectronic package of claim 30, wherein the first terminals are configured to carry at least three-quarters of the address information that can be used by the circuitry within the package to determine the addressable memory location.