KR101837520B1 - Substrate processing apparatus - Google Patents

Abstract

Each of the semiconductor chips 100 and 200 has imaging units 56 and 153 that are relatively movable with respect to the wafer W and absorption heads 55a and 55b and 152a and 152b that adsorb chips of the wafer. And a control unit 12. The control unit performs an adsorption process for adsorbing the chips T of the wafer to the adsorption unit and performs the adsorption process in parallel with the adsorption process So as to perform image pick-up processing for picking up a wafer on which the adsorption processing is performed.

Description

[0001] SUBSTRATE PROCESSING APPARATUS [0002]

The present invention relates to a substrate processing apparatus, and more particularly, to a substrate processing apparatus having an image pickup section and a suction section.

Conventionally, a substrate processing apparatus having an image pickup section and a suction section is known. Such a substrate processing apparatus is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-214421.

Japanese Patent Application Laid-Open No. 2004-214421 discloses a substrate processing apparatus including an imaging section and a suction section which are relatively movable with respect to the pellet, and a control section. This substrate processing apparatus is configured to perform an image pickup process for picking up a predetermined pellet in a camera, perform an adsorption process for adsorbing a predetermined pellet to the adsorption section after recognition processing for recognizing an image of a predetermined pellet picked up is performed .

Japanese Patent Application Laid-Open No. 2004-214421

However, in the substrate processing apparatus of Japanese Patent Application Laid-Open No. 2004-214421, since the adsorption processing is performed after the image pickup processing and the recognition processing are performed, a waiting time for image pickup processing and recognition processing occurs when the adsorption processing is performed. Therefore, it is difficult to reduce the time required for the substrate processing (it is difficult to shorten the tact time).

An object of the present invention is to provide a substrate processing apparatus capable of reducing the time required for substrate processing.

An apparatus for processing a substrate according to an aspect of the present invention includes: an image pickup section for picking up a wafer including a plurality of chips and moving relative to the wafer; and an adsorption head for adsorbing chips from the wafer, And the control unit executes an adsorption process for adsorbing the chips of the wafer by the adsorption unit and performs an image pickup process for imaging the wafer on which the adsorption process is performed by the image pickup unit in parallel with the adsorption process .

In the substrate processing apparatus according to one aspect of the present invention, an adsorption process for adsorbing chips of a wafer by the adsorption unit as described above, and an image pickup process for picking up a wafer to be adsorbed by the image pickup unit in parallel with the adsorption process The image pickup process can be performed during the suction process differently from the case where the suction process and the image pickup process are executed at different timings. Thus, the time required for the substrate processing can be reduced (the tact time can be shortened).

In the above substrate processing apparatus according to one aspect, preferably, the control section executes an adsorption process for adsorbing a chip at a predetermined position of the wafer by the adsorption section, and in parallel with the adsorption process, And is configured to execute image pickup processing for picking up a part of chips to be picked up later than a chip at a predetermined position to be picked up. With this configuration, it is possible to perform imaging of a chip in which a suction process is performed in the vicinity of a predetermined position and in the vicinity of a predetermined position while the suction process is performed on a chip at a predetermined position It is possible to absorb the time required for the imaging processing of the chip close to the timing of the suction to be carried out at the time of the suction processing of the chip at the predetermined position. As a result, it is possible to easily reduce the time required for the substrate processing.

In this case, preferably, the control unit is configured to execute image pickup processing for picking up a chip to be picked up next to the chip at a predetermined position by the image pickup unit in parallel with the adsorption processing. With this configuration, it is possible to perform imaging (next to the chip to be picked up) of the chip to be subjected to the adsorption processing next to the chip at the predetermined position while performing the adsorption process on the chip at the predetermined position, The time required for the imaging processing of the nearest chip can be absorbed in the time of the suction processing of the chip at the predetermined position. As a result, it is possible to easily reduce the time required for the substrate processing even when the imaging processing of the chip closest to the timing of attraction is performed.

In the configuration in which the image pick-up processing for picking up a part of the chips picked up from the chip at a predetermined position near the predetermined position is performed, And to perform image pick-up processing for picking up a plurality of chips including a chip to be picked up next to the chip in the position. With such a configuration, it is possible to simultaneously perform imaging of a plurality of chips, in which the suction process is sequentially performed after the chip at the predetermined position, while the suction process is performed on the chip at the predetermined position, Can be obtained efficiently.

In the above substrate processing apparatus according to one aspect, preferably, the control section executes the image pickup processing in parallel with the adsorption processing, which is a processing for moving the adsorption section from the initial position to the adsorption position and adsorbing the chips and then moving from the adsorption position to the initial position . With this configuration, it is possible to carry out the image pick-up processing in parallel not only during the operation of sucking the chip but also during the movement from the initial position to the suction position and from the suction position to the initial position.

In this case, preferably, the control section is configured to execute the image pick-up processing at the timing at which the suction section picks up the chips while the pick-up processing is being performed. With this configuration, the image pickup processing can be reliably performed during the execution of the adsorption processing.

The substrate processing apparatus according to the aspect may further include an image processing section for recognizing the image picked up by the image pick-up processing, wherein the control section executes the pick-up processing in parallel with the pick- And the image processing unit is configured to execute a recognition process of recognizing the state of the chip based on the image transferred in parallel with the attraction process. With this configuration, unlike the case where the adsorption process, the image pickup process and the recognition process are executed at different timings, the recognition process is performed in addition to the image pickup process during the adsorption process . As a result, the time required for the substrate processing can be further reduced.

In the substrate processing apparatus according to the aspect, preferably, the wafer includes chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction, and the adsorption unit is arranged in a first direction Sequentially picking up chips arranged in a first row of a predetermined row in a second direction after successively sucking chips in a predetermined row, and adsorbing the chips successively in a first direction of a next row in a second direction in a second direction, And a first portion extending in the second direction within the imaging region of the imaging section and provided with the suction head. With this configuration, unlike the case where the first portion of the adsorption portion in the image pickup region is extended in the first direction during the adsorption processing, the image pickup processing is performed in parallel with the adsorption processing of the chips in the predetermined row along the first direction, It is possible to prevent the area of the chip taken by the first portion from being narrowed.

In this case, preferably, the adsorption portion is formed so as to be connected to the first portion, and further includes a second portion protruding out of the imaging region of the imaging portion during the adsorption processing and extending in the first direction, and the first portion and the second portion The adsorbing portion including the adsorbing portion has a substantially L shape when viewed from the plane. With this configuration, the suction portion can be easily supported by the second portion while suppressing narrowing of the area of the chip to be imaged.

The image processing unit further includes a wafer table for holding the wafer so as to be relatively movable with respect to the position of the image pickup unit and the position of the suction unit when the chip is being picked up, The wafer table is moved on the basis of the image recognized by the recognition process to perform the adsorption process and to execute the image pick-up process in parallel with the adsorption process. With this configuration, the imaging processing and the adsorption processing can be performed by moving only the wafer table, unlike the case of moving the imaging section and the suction section, respectively, in order to execute the imaging processing and the adsorption processing. In other words, since the number of moving parts can be reduced, the structure of the substrate processing apparatus can be simplified.

In the substrate processing apparatus according to the aspect, preferably, the wafer includes chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction, and the adsorption unit is arranged in a first direction Sequentially move chips in a predetermined row and move in a second direction to successively pick up chips arranged along a first direction of a next row of a predetermined row, wherein the adsorption section and the imaging section are independently arranged in a first direction And the control unit is configured to execute image pickup processing in parallel with the adsorption processing. With this configuration, the adsorption unit and the image pickup unit can be moved independently of each other, so that the image pickup process can be easily performed in parallel with the adsorption process.

(Effects of the Invention)

According to the present invention, it is possible to reduce the time required for the substrate processing as described above.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the overall structure of an actual organ according to a first embodiment of the present invention. Fig.
2 is a block diagram of an actual organ according to the first embodiment of the present invention.
3 is a schematic view showing a state in which image pickup processing is performed in parallel with the adsorption processing by the adsorption section on the X2 side of the yarn end according to the first embodiment of the present invention.
4 is a plan view showing a state in which an image pickup process is performed in parallel with the adsorption process by the adsorbing portion on the X2 side of the yarn end according to the first embodiment of the present invention.
5 is a schematic view showing a state in which image pickup processing is performed in parallel with the adsorption processing by the adsorbing portion on the X1 side of the yarn end according to the first embodiment of the present invention.
6 is a plan view showing a state in which image pickup processing is performed in parallel with the adsorption processing by the adsorbing portion on the X1 side of the yarn end according to the first embodiment of the present invention.
7A is a view showing a state before adsorption is started. 7B is a view showing a state in which the adsorption section on the X2 side is rotated from the initial position to the adsorption position. Fig. 7C is a view showing a state in which the adsorbing portion on the X2 side is rotated from the adsorption position to the initial position. 7D is a diagram showing a state in which the adsorption section on the X1 side starts to rotate from the initial position to the adsorption position. 7E is a view showing a state in which the adsorbing portion on the X1 side is rotated from the initial position to the adsorbing position.
Fig. 8 is a flowchart showing adsorption processing, image pickup processing, and recognition processing of an actual organ according to the first embodiment of the present invention.
Fig. 9 is a view showing the overall structure of an actual organs according to a second embodiment of the present invention. Fig.
Fig. 10 is a block diagram of an actual organ according to a second embodiment of the present invention.
11 is a view showing an apparatus for taking out an actual organs according to a second embodiment of the present invention.
Fig. 12 is a view showing an adsorption position and an imaging region of an actual organ according to the second embodiment of the present invention. Fig.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, the structure of the yarn 100 according to the first embodiment of the present invention will be described with reference to Figs. 1 to 7. Fig. Further, the base body 100 is an example of the "substrate processing apparatus" of the present invention.

As shown in Fig. 1, the chip 100 draws a chip (bare chip) T from a diced wafer W and mounts it on a substrate 500 at a predetermined mounting operation position 500a (500b) (Mounting). The wafer W includes a chip T arranged in a matrix in a first direction (hereinafter referred to as X direction) and a second direction (hereinafter referred to as Y direction) substantially perpendicular to the X direction .

The yarn carrier 100 includes a base 1, a conveyor 2, and two mounting portions 3a and 3b. The yarn end system 100 includes the wafer table 4, the drawing device 5, the relay units 6a and 6b, the chip mounting portions 7a and 7b, the transfer stations 8a and 8b, And part-recognition imaging sections 9a and 9b. As shown in FIG. 2, the physical entity 100 further includes a controller 10 for controlling the physical entity 100 and a display section 15 for displaying information about the real entity 100.

As shown in Fig. 1, the base 1 includes a conveyor 2, a wafer table 4, a drawing device 5, a relay unit 6a (6b), a chip mounting portion 7a (7b) (8a (8b)) and the component recognition imaging section (9a (9b)).

The conveyor 2 is configured to transport the substrate 500 from the X1 direction to the X2 direction. More specifically, the conveyor 2 conveys the substrate 500 to a predetermined mounting operation position 500a (500b) and mounts the chip T from the predetermined mounting operation position 500a (500b) 500 are carried out.

The mounting portion 3a (3b) is disposed at a higher position than the substrate 500. [ The mounting portion 3a (3b) is configured to be movable in the X direction with respect to the X bar 110 by driving the X-axis motor 161 (see FIG. 2), respectively. The mounting portions 3a (3b) are independently movable along the X-bars 110 in the X-direction. The X bar 110 is configured to be movable in the Y direction with respect to the Y bar 120 by driving the Y axis motor 162 (see FIG. 2). Thus, both of the two mounting portions 3a and 3b can move in the horizontal direction (X and Y directions). The mounting portion 3a (3b) includes a plurality of mounting heads 31a (31b) and one substrate recognizing image pickup portion 32a (32b). Although two X-axis motors 161 (see Fig. 2) are provided for driving the mounting portions 3a and 3b, only one X-axis motor 161 is shown in Fig. 2 in a simplified manner.

The plurality of mounting heads 31a and 31b are configured to move in the vertical direction (Z direction) by driving the Z-axis motor 163 (see FIG. 2) (R direction) parallel to the Z direction by driving the R axis motor 164 (see FIG. 2). The mounting heads 31a (or 31b) A plurality of Z-axis motors 163 and R-axis motors 164 (see FIG. 2) are provided, respectively. However, in FIG. 2, only one Respectively.

The substrate recognition imaging section 32a (32b) includes a camera and is configured to image the substrate 500 from above. The R-axis motor 164 (see FIG. 2) is driven on the basis of the image information of the substrate 500 picked up by the substrate recognition imaging section 32a (32b). The mounting head 31a (31b) is controlled to adjust (correct) the position of the chip T so that the chip T is mounted on the substrate 500.

The wafer table 4 is driven by the X-axis motor 171, the Y-axis motor 172, the Z-axis motor 173 and the R-axis motor 174 shown in FIG. , And the position relative to the base table 1 in the R direction can be changed (adjusted). The wafer table 4 is configured to be movable in the Y direction with respect to the base table 1 in a state in which the wafer W is fixedly held by driving the Y axis motor 172. [ The wafer table 4 is moved between the withdrawing operation position of the chip T in the state shown in Fig. 1 and the wafer replacing position in which the wafer W in which the chip T is taken is replaced with a new wafer W Consists of.

The wafer table 4 is configured to hold the wafer W substantially at the center when viewed from the plane. The chip T of the wafer W is projected from the lower side of the wafer table 4 by a projection device (not shown), and is then sucked by a sucking portion 51, which will be described later.

Here, in the first embodiment, the drawing device 5 includes a suction portion 51 and a wafer recognition imaging portion 56 as shown in Figs. 3 and 5. Further, the adsorption units 51 are arranged in pairs so as to sandwich the wafer table 4 in the left-right direction (X direction). Hereinafter, the adsorbing portion 51 on the X2 side will be referred to as a sucking portion 51a and the sucking portion 51 on the X1 side will be referred to as a sucking portion 51b. The adsorption portion 51a includes a first portion 52a, a second portion 53a, a base portion 54a (see FIG. 1), and an adsorption head 55a. The suction portion 51b includes a first portion 52b, a second portion 53b, a base portion 54b (see FIG. 1), and an adsorption head 55b. The adsorption heads 55a (55b) are provided in the vicinity of the tip of the Y1 side of the first portion 52a (52b). The suction portion 51a is configured to be rotated around a pivot axis parallel to the Y direction by a motor 181 (see Fig. 2). Similarly, the sucking portion 51b is configured to be rotated around the pivot axis parallel to the Y direction by the motor 182 (see Fig. 2). At the predetermined position P0 where the chip T is sucked, the upper surface (the surface on the Z1 side) is sucked by the sucking head 55a (55b). When the chip T is rotated from the sucking position P2 to the initial position P1, the surface of the chip T placed on the Z2 side at the sucking position P2 is shifted toward the upper side (Z1 side (Flipped). 7, the suction head 55a of the suction portion 51a disposed at the suction position P2 as seen from the Y direction and the suction head 55a of the suction portion 51b disposed at the suction position P2 55b correspond to each other (correspond). The position of the X2 side end of the wafer recognition image sensing unit 56 and the second portion 53a of the attracting unit 51a and the position of the end of the X1 side of the second portion 53b of the attracting unit 51b The position is fixed. The wafer-recognition imaging section 56 is an example of the "imaging section" of the present invention.

As shown in Figs. 3 and 5, the suction portion 51a has a substantially L shape in which the second portion 53a and the first portion 52a are connected. The second portion 53b and the first portion 52b are connected to the suction portion 51b. Since the adsorbing portions 51a and 51b have substantially the same structure in the other points, only the adsorbing portion 51a will be described below, and the description of the adsorbing portion 51b will be omitted.

4, the first portion 52a is configured to extend in the Y direction as well as being within the imaging region R of the wafer recognition imaging section 56 at the time of the adsorption treatment as seen from the plane . The width of the first portion 52a in the X direction is smaller than the width of the imaging region R in the X direction. Specifically, the width of the first portion 52a in the X direction is about 1/4 of the width of the imaging region R in the X direction. The first portion 52a is configured so that the tip portion on the Y1 side is disposed at a position spaced apart from the outer edge of the Y1 side of the imaging region R by a predetermined distance.

The second portion 53a is configured to protrude out of the imaging region R of the wafer recognition imaging section 56 during the adsorption process. In addition, the second portion 53a is configured to extend in the X direction schematically. The suction portion 51a is configured to be rotatable about a pivot axis extending in the Y direction by being rotatably supported by the base portion 54a at the end portion (pivot center) of the second portion 53a on the X2 side . 7, the adsorption section 51a is rotated (moved) from the initial position P1 (rotation start position) to the adsorption position P2 to adsorb the chip T as shown in FIG. 7 And is configured to rotate from the suction position P2 to the initial position P1.

Further, as shown in Figs. 4, 6, and 7, the adsorption section 51a is configured to be movable relative to the wafer W. Specifically, since the position of the end portion (pivot center) on the X2 side of the second portion 53a of the suction portion 51a is fixed, the movement of the wafer table 4 causes the movement of the end portion on the X2 side of the second portion 53a The position of the wafer table 4 relative to the position is shifted (the relative position between the wafer W and the sucking portion 51a is changed). The sucking portion 51a sequentially sucks chips T of a predetermined row (for example, the n-th row) arranged along the X-direction and then successively sucks the chips of the next row (for example, (n + 1) -th row) along the X direction.

As shown in Fig. 1, the wafer recognition imaging section 56 includes a camera and has a function of imaging a wafer W including a plurality of chips (T). In addition, the wafer recognition imaging section 56 is fixedly arranged. In addition, the wafer-recognition imaging section 56 is configured to be relatively movable with respect to the wafer W. The position of the wafer recognition imaging section 56 is fixed and the wafer table 4 moves relative to the position of the wafer recognition imaging section 56 as the wafer table 4 moves ) And the wafer recognition imaging section 56 are changed. 3 to 6, the wafer recognition imaging section 56 has a substantially rectangular imaging region R having long sides along the X direction. The wafer recognition imaging section 56 is arranged so that the chip T sucked by the attracting section 51a (51b) enters the center of the imaging region R. In addition, the imaging region R has a size in which a plurality of chips T enter. Therefore, the wafer-recognition imaging section 56 has a first portion 52a (52b) that enters the imaging region R in a state where the adsorption section 51a (51b) is disposed at the adsorption position P2, (Wafer W) other than the chips T (52a and 52b). The first portion 52a (52b) of the attracting portion 51 is accommodated in the imaging region R at a position corresponding to a position substantially at the center of the imaging region R in the X direction. The number of chips T entering the imaging region R depends on the size of the chip T. [

As shown in Fig. 1, the two relay units 6a and 6b each have a function of carrying the chip T sucked by the suction units 51a (51b) to the two chip stacking units 7a and 7b have. The relay units 6a and 6b are configured to move in the Y direction by the motors 191 and 192 (see Fig. 2), respectively.

The chip mounting portions 7a and 7b are configured so that the chips T carried from the relaying units 6a and 6b are stacked, respectively. The chip T mounted on the chip mounting portion 7a (7b) is configured to be picked up by the mounting heads 31a (31b) moved to the position of the chip mounting portion 7a (7b), respectively.

The two transfer stations 8a and 8b are formed for applying an adhesive (flux) to the chip T sucked by the mounting heads 31a and 31b.

The two component recognition imaging sections 9a and 9b are configured to capture a lower surface of a chip T which is held (held) by a mounting head 31a (31b), including a camera.

The controller 10 includes a storage unit 11, an arithmetic processing unit 12, a motor control unit 13, and an image processing unit 14 as shown in Fig.

The storage unit 11 stores various programs and data related to the mounting work such as the mounting program, the transportation system data, and the equipment inherent data.

The operation processing section 12 (hereinafter referred to as the main CPU 12) includes a CPU and is configured to control the physical entity 100 using the program and data of the storage section 11. [ The main CPU 12 also executes a plurality of chips T including a chip T sucked next to the chip T at a predetermined position P0 in the wafer recognition and imaging section 56 in parallel with the adsorption process So that the image is picked up. The main CPU 12 is configured to execute the image pick-up processing at the timing at which the suction heads 55a (55b) adsorb the chips T during the time when the adsorption processing is performed. The details of the main CPU 12 will be described later.

The motor control unit 13 includes a CPU and is configured to receive commands from the main CPU 12 and to control the operation of various motors (see FIG. 2).

The image processing unit 14 (hereinafter referred to as an image processing CPU 14) includes a CPU and is configured to use the program and data of the storage unit 11 to identify the component recognition imaging unit 9a (9b) (32a (32b)) and the wafer-recognition imaging section (56).

Here, in the first embodiment, the main CPU 12 (see Fig. 2) performs an adsorption process for adsorbing the chips T of the wafer W by the adsorption heads 55a (55b) The wafer recognition imaging section 56 is configured to execute imaging processing for imaging the wafer W to be subjected to the attraction processing. More specifically, the main CPU 12 performs an adsorption process for adsorbing the chips T at a predetermined position P0 of the wafer W by the adsorption heads 55a (55b) A part of chips T (predetermined position P0) of chips T sucked later than the chip T at a predetermined position P0 near the predetermined position P0 by the image pickup unit 56, (Chip T to be picked up next to the chip T of the chip T). The main CPU 12 also performs the suction process so as to move the wafer table 4 based on the image recognized by the recognition process so that the chip T can be sucked at an appropriate position, Processing is executed. After the suction process for the chip T at the predetermined position P0 is performed, the image pickup process of the chip T in the vicinity of the predetermined position P0 and for the suction process to be performed after the chip T is executed The chip T in the vicinity of the predetermined position P0 is displaced from the position P0 due to the suction of the chip T at the predetermined position P0, Is picked up behind the chip T at the predetermined position P0 on the basis of the image of the chip T in the vicinity of the predetermined position PO captured after the execution of the suction process and also at the back of the chip T The adsorption process of the chip T can be performed accurately.

Further, the main CPU 12 is configured to execute image pickup processing in parallel with the adsorption processing, and to transmit the image picked up by the image pickup processing to the image processing CPU 14 (see FIG. 2). The image processing CPU 14 is configured to execute recognition processing for recognizing the state of the chip T based on the image transferred in parallel with the attraction processing. That is, while the main CPU 12 performs the adsorption processing of the chip T at the predetermined position P0, the image of the chip T sucked next to the chip T at the predetermined position P0 is detected by the wafer- (The image pickup processing control by the main CPU 12 is performed) by the image processing CPU 14 and the image processing CPU 14 recognizes the image. Then, the main CPU 12 obtains (previously) the information of the chip T to be picked up next, while performing the adsorption process of the chip T at the predetermined position P0. This makes it possible to absorb the time required for the image pickup processing and the recognition processing of the chip T at the time required for the chip T adsorption processing.

Next, the operation of the wafer table 4 will be described with reference to Figs. 3 to 6. Fig.

3 to 6, the wafer table 4 is provided with a chip (hereinafter referred to as a chip) 4 in the X1 direction from the chip T at the end in the X2 direction of a predetermined row T are sequentially arranged in the X2 direction so as to be disposed at the arrangement positions of the adsorption heads 55a (55b) of the adsorption units 51a (51b) at the adsorption positions P2. Thereafter, the wafer table 4 has chips T at the end in the X1 direction of the next row (the (n + 1) th row) of the predetermined row in the Y direction at the adsorption portion 51a (51b) The adsorption heads 55a (55b) of the adsorbing head 55 are moved. Thereafter, the wafer table 4 sequentially moves from the chip T at the end in the X1 direction to the chip T at the end in the X2 direction of the next row of the predetermined row to the suction unit 51a (51b ) In the X1 direction so as to be disposed at the disposing position of the adsorption heads 55a (55b). Thereafter, the wafer table 4 is moved in the X2 direction in the next row (the (n + 2) th row) in the Y direction by the chip T at the tip of the adsorption head 51a (51b) 55a (55b)). The chips T are sequentially arranged at the positions where the adsorption heads 55a (55b) of the adsorption portions 51a (51b) of the adsorption position P2 are arranged by repeating these operations by the wafer table 4. [ Means a row of chips T arranged in a matrix on a wafer W in the X direction and a row means a row of chips T in the Y direction.

Next, referring to Fig. 7, the operation of the suction units 51a and 51b to pick up the chips T will be described.

The adsorbing portions 51a on the X1 side and the adsorbing portions 51b on the X2 side are configured to adsorb the chips T from the wafers W alternately. Concretely, the adsorbing portion 51a on the X2 side corresponds to the position of the chip T in a predetermined column (for example, the m-th column) of the predetermined row (for example, the n-th row) And is rotated from the initial position P1 to the suction position P2 (see Fig. 7A). Subsequently, the adsorption head 55a on the X2 side adsorbs a predetermined row (mth column) of chips T (see Fig. 7B). Next, the adsorption head 55a on the X2 side is rotated from the adsorption position P2 to the initial position P1 while adsorbing the chips T (see Fig. 7C). At this time, the relay unit 6a receives the chip T from the attraction head 55a rotated to the initial position P1 and carries the chip T to the chip mounting portion 7a (see Fig. 1). At this time, the wafer table 4 is moved in the X2 direction so that the chip T of the next row (m + 1)) is placed at the attracting position P2. The adsorbing portion 51b on the X1 side is moved from the initial position P1 so that the adsorption head 55b corresponds to the position of the chip T in the predetermined row (m + 1) And is rotated to the adsorption position P2 (see Fig. 7D). Subsequently, the adsorption head 55b on the X1 side adsorbs chips T in a predetermined row (m + 1) column (see FIG. 7E). Thereafter, the adsorption head 55b on the X1 side is rotated from the adsorption position P2 to the initial position P1 while the chip T is adsorbed. Then, the wafer table 4 is moved in the X2 direction so that the chip T of the next row (m + 2 < th > column) is placed at the sucking position P2. These operations are repeated so that the chips T are successively attracted (drawn out) from the wafer W. In the hole performance, the chips T are successively attracted from the X2 direction to the X1 direction, and the chips T are successively attracted from the X1 direction to the X2 direction in the even performance.

Next, the adsorption process, image pickup process and recognition process of the physical organs 100 will be described with reference to Figs. 2, 7, and 8. Fig. The main CPU 12 executes the adsorption process and the image pickup process, and the image processing CPU 14 executes the recognition process.

First, processing relating to the adsorption process (steps S1 to S6) will be described.

In step S1, the main CPU 12 acquires the sucking address (position information of the chip T) from the storage unit 11. Then, That is, the main CPU 12 acquires the information of the wafer W held in the wafer table 4 and acquires the positional information of the chip T sucked by the sucking unit 51.

Subsequently, in step S2, the main CPU 12 determines whether or not the center image of the chip T at the predetermined position P0 to be attracted is recognized. In addition, the image processing CPU 14 performs the recognition processing of the center image of the chip T to be picked up in step S14. The main CPU 12 repeats this process until the chip T on which the image processing CPU 14 picks up a center image is recognized and the chip T to which the image processing CPU 14 picks up If the image is recognized, the process proceeds to step S3.

Subsequently, in step S3, the main CPU 12 executes the adsorption process. More specifically, the main CPU 12 rotates the suction head 55a or 55b to a position corresponding to the chip T at a predetermined position P0 to be sucked, and sucks the chip T to the suction head 55a or 55b . If the main CPU 12 determines in step S14 that the chip T is defective, the main CPU 12 proceeds to step S4 without sucking the chip T determined to be defective.

Subsequently, in step S4, the main CPU 12 updates the adsorption address and stores it in the storage unit 11. [

Subsequently, in step S5, the main CPU 12 determines whether there is another chip T to be attracted on the wafer W or not. If another chip T to be adsorbed exists, the process proceeds to step S6. On the other hand, when there is no other chip T to be adsorbed, the processes (steps S1 to S6) related to the adsorption process are terminated.

Subsequently, in step S6, the main CPU 12 performs a process of moving the wafer table 4. [ More specifically, the main CPU 12 performs processing for moving the wafer table 4 so that the next chip T of the chip T at the predetermined position P0 where the adsorption processing is performed in step S3 can be adsorbed.

Next, processing relating to the image pickup processing and recognition processing (steps S11 to S16) will be described. The processing from step S11 to step S16 is performed in parallel with the processing from step S1 to step S6.

First, in step S11, the main CPU 12 acquires the recognition address (information on whether or not the chip T is recognized) from the storage unit 11. [

Subsequently, in step S12, the main CPU 12 determines whether or not the central image of the chip T to be picked up is captured. When the main CPU 12 determines that the chip T to be picked up has a central image picked up, the main CPU 12 advances the processing to step S14. On the other hand, when the main CPU 12 determines that the central image of the chip T to be picked up is not picked up, the main CPU 12 advances the processing to step S13.

Subsequently, in step S13, the main CPU 12 executes imaging processing. Specifically, the main CPU 12 performs a process of picking up a central image of the chip T to be picked up.

Subsequently, in step S14, the image processing CPU 14 executes recognition processing. More specifically, the image processing CPU 14 (see Fig. 2) processes the appearance (interpretation) of the appearance of the chip T based on the image centered on the chip T which is received and received by the main CPU 12 . The image processing CPU 14 recognizes that the adjacent chips T are not adequately diced (in fact, a separate chip T is connected) and that the chip T ) Has a crack, it is determined that the chip T is defective. On the other hand, the image processing CPU 14 determines that the chip T is normal when the chip T is not defective. In addition, the image processing CPU 14 performs a recognition process on a portion of the central image, in which the chip T sucked at the time of performing the recognition process, is already recognized (a portion already recognized in the image obtained before recognition) Do not do it. In other words, the image processing CPU 14 performs recognition processing of the newly reflected portion of the center image of the chip T to be picked up.

Subsequently, in step S15, the main CPU 12 updates the recognition address and stores it in the storage unit 11. [

Subsequently, in step S16, the main CPU 12 determines whether or not there is another chip T to be recognized on the wafer W. [ If there is another chip T to be recognized on the wafer W, the main CPU 12 advances the processing to step S11. On the other hand, when there is no other recognized chip T on the wafer W, the main CPU 12 ends the processes (steps S11 to S16) related to the image pickup processing and recognition processing.

As described above, the main CPU 12 determines whether or not the predetermined position (P0) chip T to be sucked in parallel with the process (step S1 to step S6) related to the adsorption process of the chip T at the predetermined position P0 (Steps S11 to S16) related to the image pickup processing and the recognition processing of the chip including the chip T sucked next to the chip T at the predetermined position P0 are executed.

In the first embodiment, the following effects can be obtained.

In the first embodiment, the adsorption process for adsorbing the chips T of the wafer W is performed by the adsorption units 51a (51b) as described above, and the wafer identification and imaging unit 56 A main CPU 12 configured to execute image pickup processing for picking up an image of a wafer W on which an adsorption process is performed is provided. Thus, unlike the case where the adsorption process and the image pick-up process are performed at different timings, the image pick-up process can be executed during the execution of the adsorption process. Thus, the time required for the substrate processing can be reduced.

In the first embodiment, the adsorption process for adsorbing the chips T at the predetermined position P0 of the wafer W by the adsorption units 51a (51b) is performed, and in parallel with the adsorption process, (T) picked up later than the chip (T) at a predetermined position (P0) in the vicinity of the predetermined position (P0) by the picking up unit (56) And constitutes the main CPU 12. [ Thereby, the chip (chip) in which the adsorption process is performed after the chip T in the vicinity of the predetermined position P0 and at the predetermined position P0 during the adsorption process for the chip T at the predetermined position P0 The time required for image pick-up processing of the chip T close to the timing of picking up can be made shorter than the time required for picking up the chip T (P0) at the predetermined position P0 In the adsorption process of the adsorbent. As a result, it is possible to easily reduce the time required for the substrate processing.

In addition, in the first embodiment, in parallel with the adsorption process, the main CPU (not shown) executes image pick-up processing for picking up a chip T sucked next to the chip T at the predetermined position P0 by the wafer identifying / (12). Thereby, imaging of the chip T to be subjected to the adsorption process is performed next to the chip T at the predetermined position P0 while performing the adsorption process on the chip T at the predetermined position P0 The time required for the image pick-up processing of the chip T closest to the timing at which the chips are adsorbed can be absorbed in the time of the adsorption processing of the chips T at the predetermined position P0 . As a result, it is possible to easily reduce the time required for the substrate processing even when the imaging processing of the chip T closest to the timing of attraction is performed.

In the first embodiment, a plurality of chips T including a chip T sucked next to a chip T at a predetermined position P0 are detected by the wafer identifying / sensing unit 56 in parallel with the adsorption process The main CPU 12 is configured to execute an image pickup process for picking up an image. Thereby it is possible to perform image pickup of a plurality of chips T in which the adsorption process is sequentially performed after the chip T at the predetermined position P0 while the adsorption process for the chip T at the predetermined position P0 is carried out It is possible to efficiently acquire images of a plurality of chips T by one imaging process.

In the first embodiment, the sucking portion 51a (51b) moves from the initial position P1 to the sucking position P2 and sucks the chip T, and then moves from the sucking position P2 to the initial position P1 The main CPU 12 is configured to execute image pickup processing in parallel with the adsorption processing which is a moving processing. As a result, not only during the operation of sucking the chip T but also during the movement of the adsorption section 51a (51b) from the initial position P1 to the adsorption position P2 and from the adsorption position P2 to the initial position P1 The imaging processing can be executed in parallel while moving.

In the first embodiment, the main CPU 12 is configured to execute the image pick-up processing at the timing at which the suction unit 51a (51b) sucks the chips T while the suction process is performed. Thus, the image pickup processing can be reliably performed during the execution of the adsorption processing.

In the first embodiment, the main CPU 12 is configured to execute the image pickup process in parallel with the adsorption process, to transfer the image picked up by the image pickup process to the image processing CPU 14, And the image processing CPU 14 is configured to execute recognition processing for recognizing the state of the chip T based on the transmitted image. As a result, unlike the case where the adsorption process, the image pick-up process and the recognition process are executed at different timings, the recognition process is performed in addition to the image pick-up process during the adsorption process (the wafer W to be picked up next is picked up first, W) can be recognized. As a result, the time required for the substrate processing can be further reduced.

In the first embodiment, the chips T arranged in the X direction are successively attracted, and the chips T arranged along the X direction of the next row of the predetermined row in the Y direction (55a) extending in the Y direction within the imaging region (R) of the wafer recognition imaging section (56) at the time of the adsorption processing and constituting the adsorption section (51a (51a (51b)) so as to include the first portion (52a (52b) in which the first portion Unlike the case where the first portion 52a (52b) of the adsorption section 51a (51b) entering the imaging region R during the adsorption process extends in the X direction, The area of the chip T picked up by the first portion 52a (52b) of the attracting portion 51a (51b) can be suppressed from being narrowed even if the image pick-up processing is performed in parallel with the adsorption processing of the picked- .

In the first embodiment, the adsorption portions 51a (51b) including the first portion 52a (52b) and the second portion 53a (53b) are formed in a substantially L shape. The suction portion 51a (51b) can be easily supported by the second portion 53a (53b) while suppressing narrowing of the area of the chip (T) to be picked up.

In the first embodiment, the main CPU 12 is configured to move the wafer table 4 based on the image recognized by the recognition process, perform the adsorption process, and execute the image pickup process in parallel with the adsorption process. Thereby, the image pickup processing and the adsorption processing can be performed by moving only the wafer table 4, unlike the case where the wafer recognition imaging section 56 and the suction section 51a (51b) are respectively moved to execute the imaging processing and the adsorption processing . In other words, since the number of moving parts can be reduced, the structure of the yarn carrier 100 can be simplified.

(Second Embodiment)

Hereinafter, with reference to Figs. 9 to 12, the structure of the physical organs 200 according to the second embodiment of the present invention will be described. The physical body 200 is an example of the "substrate processing apparatus" of the present invention.

Unlike the first embodiment in which the L-shaped suction part (51a (51b) is rotated around the rotation axis extending in the Y direction), the drawing device (105) A description will be given of an actual organs 200 including a suction portion 151 that rotates around.

As shown in Fig. 9, the yarn layer 200 is a yarn that can take out a chip T from a diced wafer W and mount (mount) it on a substrate 500 at a predetermined mounting operation position 500c It is a long term.

The body 200 has a base 1, a conveyor 2, and a mounting portion 103. The physical body 200 is provided with a wafer table 4, a drawing device 105, a transfer station 108, and a single component recognition imaging section 109.

The base table 1 supports the conveyor 2, the wafer table 4, the drawing device 105, the transfer station 108 and the component recognition imaging section 109 as shown in Fig.

The conveyor 2 is configured to transport the substrate 500 from the X1 direction to the X2 direction. More specifically, the conveyor 2 is configured to carry the substrate 500 to a predetermined mounting operation position 500c and to remove the substrate 500 from the predetermined mounting operation position 500c.

One mounting portion 103 is formed. The mounting portion 103 includes a plurality of mounting heads 131 and one board recognizing and photographing portion 132. The mounting portion 103 is configured to receive the chip T sucked by the sucking portion 151. The mounting portion 103 applies an adhesive (flux) to the chip T by the transfer station 108 and mounts the chip T on the substrate 500. [

The substrate recognition image pickup section 132 includes a camera and is configured to pick up an image of the substrate 500.

Here, in the second embodiment, the wafer table 4 is configured so as not to move during the installation work in which the chips T are mounted on the substrate 500. [

In the second embodiment, the drawing device 105 includes a suction portion 151, a wafer recognition imaging portion 153, an X bar 154 and a Y bar 155. [ As shown in Figs. 9 and 11, the adsorption unit 151 and the wafer recognition imaging unit 153 are formed so as to sandwich the X bar 154 therebetween. The adsorption unit 151 and the wafer recognition image pickup unit 153 are configured to move in the X direction along the X bar 154 independently of each other. 11, the X-bar 154 moves in the Y-direction along the Y-bar 155, so that the adsorption unit 151 and the wafer-recognition imaging unit 153 are configured to move together in the Y-direction.

The adsorption unit 151 includes a pair of adsorption heads 152a and 152b. The adsorption heads 152a (152b) are rotatable around an axis parallel to the X-axis direction and are configured to be able to move up and down in the vertical direction.

The adsorption heads 152a (152b) are formed in a rod shape. The rod-like adsorption heads 152a (152b) are capable of adsorbing chips T at both ends. That is, it is possible to adsorb two chips T by one adsorption head 152a (152b). The adsorption heads 152a (152b) are independently movable in the Z direction. The adsorption heads 152a (152b) are independently rotatable about a pivot axis (R direction) extending in the X direction.

The wafer recognition imaging section 153 includes a camera and has a function of picking up an image of a wafer W including a plurality of chips (T).

Next, the relationship between the attraction position P2 and the image sensing area R will be described with reference to Fig. For the sake of simplicity, only the adsorption head 152a is shown in Fig. 12 with respect to the adsorption head 152b, not shown.

12, the center of the suction head 152a (152b) and the center of the wafer recognition imaging section 153 (the center of the imaging area R) as viewed from the plane are Y Direction by a distance D, as shown in Fig. The vicinity of the edge on the Y2 side of the sensing area R and the edge of the chip T on the Y2 side of the suction position P2 are spaced by DELTA Y described by the following equation (1).

? Y = {D- (Lr / 2) + (Lt / 2)} (One)

The value a that indicates how many times the distance DELTA Y corresponds to the length of the chip T in the Y direction is described by the following expression (2).

? =? Y / Lt

= {D- (Lr / 2) + (Lt / 2)} / Lt ... (2)

Lr is the length of the imaging area R in the Y direction and Lt is the length of the chip T in the Y direction.

(n +?) th row to the ({(n +?) + (Lr-Lt) / Lt} th row in the image pickup area R And an image pickup process and a recognition process are performed on the chip T which does not protrude from the image pickup area R in this area.

For example, in the example shown in Fig. 12, D / Lt = 4, (Lr / 2) /Lt=1.7, (Lt / 2) /Lt=0.5. In this example, α is about 2.8 from equation (2). In this case, when the first row of adsorption processing is executed (n = 1), the wafer recognition imaging section 153 recognizes that the area from the approximately 3.8th row to the approximately 6.2th row in the Y direction of the chip T And enters the imaging region R as shown in Fig. Therefore, it is possible to carry out the image pick-up processing and the recognition processing on the chip T in the fourth to sixth rows included in the image sensing area R in parallel with the adsorption processing in the first row.

According to the mounting portion 103 of the second embodiment, since the wafer recognizing and imaging portion 153 can move independently of the suction portion 151 in the X direction, even if the suction process takes time, the suction portion 151 It is possible to carry out the image pickup processing and the recognition processing without depending on the adsorption state by the image pickup element.

In the second embodiment, the following effects can be obtained.

In the second embodiment, the adsorption process for adsorbing the chips T of the wafer W by the adsorption unit 151 is performed, and the adsorption process is performed by the wafer identification imaging unit 153 in parallel with the adsorption process A main CPU 12 configured to execute an image pickup process for picking up a wafer W to be executed is provided. Thus, unlike the case where the adsorption process and the image pickup process are performed at different timings, the image pickup process can be performed during the adsorption process. Thus, the time required for the substrate processing can be reduced.

In the second embodiment, the adsorption unit 151 and the wafer recognition imaging unit 153 are configured to move independently in the X direction, and the main CPU 12 is configured to execute the imaging process in parallel with the adsorption process . As a result, the adsorption unit 151 and the wafer recognition imaging unit 153 can be moved independently of each other, so that the image pickup processing can be performed in parallel with the adsorption treatment.

Furthermore, the embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the description of the embodiments, and includes all modifications within the meaning and scope equivalent to the claims.

For example, in the first and second embodiments described above, an example of performing the image pickup processing and the recognition processing in parallel with the adsorption processing is shown, but the present invention is not limited to this. The present invention may perform only the image pickup processing in parallel with the adsorption processing.

In the first and second embodiments, the image pickup process is performed on a plurality of chips which are sucked after a predetermined chip on which the suction process is performed. However, the present invention is not limited to this. In the present invention, any number of chips to be image-picked up may be used if image pick-up processing is performed on at least one chip among chips to be picked up next to a predetermined chip on which an adsorption process is performed.

In the first and second embodiments, the imaging region of the imaging section for imaging the chip on the wafer table has a substantially rectangular shape. However, the present invention is not limited to this. In the present invention, the imaging region may have a substantially rectangular shape, for example, a circular shape.

In the first and second embodiments, an example in which the wafer table is one is shown, but the present invention is not limited to this. In the present invention, two or more wafer tables may be formed.

In the above-described first embodiment, the adsorption portion is formed in a substantially L shape, but the present invention is not limited to this. In the present invention, the adsorption section may be formed in a shape other than a substantially L-shaped shape, for example, a shape having a linear shape or two or more repeated positions.

In the first and second embodiments, the example in which the recognition process is not performed for the same chip T a plurality of times is shown, but the present invention is not limited to this. In the present invention, a plurality of times of recognition processing may be performed on the same chip (T). In this case, the adsorption process can be performed using the information of the recognition process based on the closer image pickup process. The information on the recognition process performed for the same chip T a plurality of times may be averaged, and the adsorption process may be performed based on this information.

In the first and second embodiments, an example is described in which the imaging region is configured to include a plurality of chips T, but the present invention is not limited thereto. In the present invention, the imaging region may be configured to include one chip T.

In the first embodiment, two suction units are formed in the drawing apparatus, but the present invention is not limited to this. In the present invention, one or more adsorption portions may be formed in the drawing device.

In the second embodiment, the suction unit and the image pickup unit independently move in the X direction. However, the suction unit and the image pickup unit may independently move in the X direction and the Y direction independently of each other.

In the above-described first and second embodiments, a flow-driven flow for performing the processing of the control unit in order in accordance with the processing flow has been described for the sake of convenience of explanation. However, for example, (Event-driven type) processing for executing the event-driven type (event-driven type). In this case, it may be a complete event driving type, or may be a combination of event driving and flow driving.

4: Wafer table 12: Main CPU (control unit)
14: Image processing CPU (image processing section) 51a, 51b, 151:
52a, 52b: first part 53a, 53b: second part
55a, 55b, 152a, 152b:
56, 153: wafer recognition imaging section (imaging section)
100, 200: actual organs (substrate processing apparatus) n: predetermined rows
P0: predetermined position P1: initial position
P2: absorption position R: imaging region
T: chip W: wafer
X direction: first direction Y direction: second direction

Claims (11)

An image pickup apparatus comprising: an image pickup section that picks up a wafer including a plurality of chips and is movable relative to the wafer;
An adsorption unit having an adsorption head for adsorbing the chips from the wafer and relatively movable with respect to the wafer;
And a control unit,
The control unit executes an adsorption process for adsorbing the chips of the wafer by the adsorption unit and an image pickup process for imaging the wafer on which the adsorption process is performed by the image pickup unit in parallel with the adsorption process And the substrate processing apparatus. The method according to claim 1,
Wherein the control unit executes the adsorption process for adsorbing the chips at a predetermined position of the wafer by the adsorption unit and performs the adsorption process in the vicinity of the predetermined position by the imaging unit and at the predetermined position And the image pick-up processing for picking up the chip of a part of the chips to be picked up later than the chip of the chip. 3. The method of claim 2,
Wherein the control unit is configured to execute the image pick-up process for picking up the chip that is picked up next to the chip at the predetermined position by the image pick-up unit in parallel with the adsorption process. 3. The method of claim 2,
Wherein the control unit is configured to execute the image pick-up processing for picking up a plurality of chips including the chip to be picked up next to the chip at the predetermined position by the image pickup unit in parallel with the adsorption processing. The method according to claim 1,
Wherein the control unit is configured to execute the image pick-up process in parallel with the adsorption process, which is a process of moving the adsorption unit from the initial position to the adsorption position and adsorbing the chip and then moving from the adsorption position to the initial position, Device. 6. The method of claim 5,
Wherein the control unit is configured to execute the image pickup processing at a timing at which the suction unit sucks the chip while the suction processing is performed. The method according to claim 1,
Further comprising an image processing section for recognizing an image captured by the image pickup processing,
The control unit executes the image pickup process in parallel with the adsorption process, and also transmits the image picked up by the image pickup process to the image processing unit,
Wherein the image processing unit is configured to execute recognition processing of recognizing the state of the chip based on the image transferred in parallel with the adsorption processing. The method according to claim 1,
Wherein the wafer includes the chip arranged in a matrix in a first direction and a second direction perpendicular to the first direction,
Wherein the adsorption unit successively adsorbs the chips in a predetermined row arranged along the first direction and then successively picks up chips arranged along the first direction of the next row of the predetermined row in the second direction Adsorption,
Wherein the adsorption portion is configured to include a first portion that extends in the second direction within the imaging region of the imaging portion when the adsorption process is viewed from a plan view and in which the adsorption head is formed. 9. The method of claim 8,
The adsorption section further includes a second section which is formed to be connected to the first section and which protrudes outside the imaging area of the imaging section during the adsorption processing and extends in the first direction,
Wherein the adsorption portion including the first portion and the second portion has an L shape when viewed from a plane. 8. The method of claim 7,
Further comprising a wafer table that holds the wafer so as to be relatively movable with respect to a position of the imaging unit and a position of the suction unit when the chip is being sucked,
Wherein the control unit is configured to move the wafer table based on the image recognized by the recognition process to execute the adsorption process and execute the image pickup process in parallel with the adsorption process. The method according to claim 1,
Wherein the wafer includes the chip arranged in a matrix in a first direction and a second direction perpendicular to the first direction,
The adsorption unit successively adsorbs the chips in a predetermined row arranged along the first direction and moves in a second direction to sequentially move the chips arranged along the first direction of the next row of the predetermined row Adsorption,
Wherein the adsorption unit and the imaging unit are configured to move in the first direction independently of each other,
Wherein the control unit is configured to execute the image pick-up process in parallel with the adsorption process.

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