JPWO2015151229A1 - Substrate processing equipment - Google Patents

Abstract

This mounting machine (100, 200) includes an imaging unit (56, 153) that can move relative to the wafer (W), and a suction head (55a, 55b, 152a, 152b) that sucks chips of the wafer. And a suction part (51a, 51b, 151) movable relative to the wafer, and a control part (12), the control part attracts the wafer chip (T) to the suction part. The process is executed, and in parallel with the suction process, the imaging process is performed to cause the imaging unit to image the wafer on which the suction process is performed.

Description

  The present invention relates to a substrate processing apparatus, and more particularly to a substrate processing apparatus including an imaging unit and a suction unit.

  Conventionally, a substrate processing apparatus including an imaging unit and a suction unit is known. Such a substrate processing apparatus is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-214421.

  Japanese Patent Application Laid-Open No. 2004-214421 discloses a substrate processing apparatus including an imaging unit and an adsorption unit that are movable relative to a pellet, and a control unit. This substrate processing apparatus performs an imaging process for causing a camera to image a predetermined pellet, and after performing a recognition process for recognizing an image of the captured predetermined pellet, an adsorption process for adsorbing the predetermined pellet to the adsorption unit It is comprised so that it may perform.

JP 2004-214421 A

  However, in the substrate processing apparatus disclosed in Japanese Patent Application Laid-Open No. 2004-214421, after the imaging process and the recognition process are performed, the suction process is performed. Therefore, when the suction process is performed, waiting for the imaging process and the recognition process is performed. Time occurs. For this reason, there is a problem that it is difficult to reduce the time required for substrate processing (it is difficult to shorten the tact time).

  The present invention has been made to solve the above-described problems, and one object of the present invention is to provide a substrate processing apparatus capable of reducing the time required for substrate processing.

  A substrate processing apparatus according to an aspect of the present invention has an image pickup unit that picks up an image of a wafer including a plurality of chips, is movable relative to the wafer, and a suction head that sucks the chips from the wafer. In contrast, the controller includes a suction unit that is relatively movable, and a control unit. The control unit performs a suction process of sucking the wafer chip by the suction unit, and performs the suction process by the imaging unit in parallel with the suction process. An imaging process for imaging the wafer to be executed is executed.

  In the substrate processing apparatus according to one aspect of the present invention, as described above, an adsorption process for adsorbing a chip of a wafer by the adsorption unit is performed, and a wafer on which the adsorption process is performed by the imaging unit is performed in parallel with the adsorption process. Unlike the case where the adsorption process and the imaging process are executed at different timings, by providing a control unit configured to execute the imaging process for imaging, the imaging process can also be executed during the adsorption process. it can. Thereby, the time required for substrate processing can be reduced (tact time can be shortened).

  In the substrate processing apparatus according to the one aspect described above, preferably, the control unit performs an adsorption process for adsorbing a chip at a predetermined position of the wafer by the adsorption unit, and in the vicinity of the predetermined position by the imaging unit in parallel with the adsorption process. And it is comprised so that the imaging process which image | photographs one part chip | tip of the chip | tips attracted after the chip | tip of the predetermined position attracted | sucked may be performed. If comprised in this way, while performing the adsorption | suction process about the chip | tip of a predetermined position, the imaging | photography of the chip | tip in which the adsorption | suction process is performed in the vicinity of a predetermined position and after the chip | tip of a predetermined position is performed. Since a chip having a close timing can be imaged first), it is possible to absorb the time required for the imaging process for a chip having a close suction timing in the time for the suction process for a chip at a predetermined position. As a result, the time required for substrate processing can be easily reduced.

  In this case, preferably, in parallel with the suction process, the control unit is configured to execute an image pickup process for picking up an image of a chip that is sucked next to a chip at a predetermined position by the image pickup unit. If comprised in this way, while performing the adsorption | suction process about the chip | tip of a predetermined position, the chip | tip in which an adsorption | suction process is performed next to the chip | tip of a predetermined position is imaged. Therefore, it is possible to absorb the time required for the imaging processing of the chip with the latest suction timing in the time of the suction processing of the chip at a predetermined position. As a result, it is possible to easily reduce the time required for the substrate processing even when the imaging processing of the chip having the latest adsorption timing is executed.

  In the configuration in which an imaging process is performed in the vicinity of the predetermined position and an image of a part of the chips sucked after the chip at the predetermined position to be sucked is executed, the control unit preferably includes the suction process. In parallel, the imaging unit is configured to execute an imaging process for imaging a plurality of chips including a chip adsorbed next to a chip at a predetermined position. If comprised in this way, while performing the adsorption | suction process about the chip | tip of a predetermined position, since the imaging | photography of the several chip | tip which is sequentially performed after the chip | tip of a predetermined position can be performed simultaneously, once Thus, it is possible to efficiently acquire images of a plurality of chips.

  In the substrate processing apparatus according to the above aspect, preferably, the control unit is parallel to the suction process, which is a process in which the suction unit moves from the initial position to the suction position to suck the chip and then moves from the suction position to the initial position. Thus, the imaging process is executed. With this configuration, the imaging process is executed in parallel not only during the operation of sucking the chip but also during the movement of the suction portion from the initial position to the suction position and the movement from the suction position to the initial position. be able to.

  In this case, preferably, the control unit is configured to execute the imaging process at a timing at which the suction unit sucks the chip while the suction process is being performed. If comprised in this way, an imaging process can be reliably performed during performing an adsorption | suction process.

  The substrate processing apparatus according to the above aspect preferably further includes an image processing unit that recognizes an image captured by the imaging process, and the control unit executes the imaging process in parallel with the suction process and performs the imaging process. The captured image is transferred to the image processing unit, and the image processing unit is configured to execute a recognition process for recognizing the state of the chip based on the transferred image in parallel with the suction process. With this configuration, unlike the case where the suction process, the imaging process, and the recognition process are executed at different timings, the recognition process is executed in addition to the imaging process during the suction process (the next chip to be suctioned first). To recognize the state of the chip). Thereby, the time required for substrate processing can be further reduced.

  In the substrate processing apparatus according to the aforementioned aspect, preferably, the wafer includes chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction, and the suction portion is in the first direction. The chips arranged in the predetermined direction along the first row are sequentially sucked, and then the chips arranged along the first direction of the next row after the predetermined row in the second direction are sequentially sucked. In a plan view, the suction portion is configured to include a first portion that is in the imaging region of the imaging unit and extends in the second direction and is provided with a suction head. If comprised in this way, unlike the case where the 1st part of the adsorption | suction part in an imaging area extends in a 1st direction in the case of an adsorption | suction process, it parallels with the adsorption | suction process of the chip | tip of the predetermined line along a 1st direction. Even when the imaging process is executed, it is possible to suppress the chip area to be captured from being narrowed by the first portion of the suction portion.

  In this case, preferably, the suction part is provided so as to be connected to the first part, and further includes a second part that protrudes outside the imaging region of the imaging part during the suction process and extends in the first direction. The suction part including the part and the second part has a substantially L shape in plan view. If comprised in this way, an adsorption | suction part can be easily supported by the 2nd part, suppressing that the area | region of the chip | tip imaged becomes narrow.

  In the configuration in which the image processing unit executes the recognition process, preferably, a wafer table that holds the wafer so as to be movable relative to the position of the imaging unit and the position of the suction unit when the chip is sucked. The control unit is configured to move the wafer table based on the image recognized by the recognition process, execute the suction process, and execute the imaging process in parallel with the suction process. If comprised in this way, in order to perform an imaging process and a suction process, unlike the case where an imaging part and a suction part are each moved, only a wafer table can be moved and an imaging process and a suction process can be performed. That is, since the number of parts to be moved can be reduced, the structure of the substrate processing apparatus can be simplified.

  In the substrate processing apparatus according to the aforementioned aspect, preferably, the wafer includes chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction, and the suction portion is in the first direction. Configured to sequentially suck chips arranged along a predetermined row, and then move in the second direction to sequentially suck chips arranged along the first direction of the next row after the predetermined row, The adsorption unit and the imaging unit are configured to move in the first direction independently of each other, and the control unit is configured to execute the imaging process in parallel with the adsorption process. If comprised in this way, since an adsorption | suction part and an imaging part can be moved mutually independently, an imaging process can be easily performed in parallel with an adsorption | suction process.

  According to the present invention, as described above, the time required for substrate processing can be reduced.

It is the figure which showed the whole structure of the mounting machine by 1st Embodiment of this invention. It is a block diagram of the mounting machine by 1st Embodiment of this invention. It is the schematic diagram which showed the state in which an imaging process is performed in parallel with the adsorption | suction process by the adsorption | suction part by the side of X2 of the mounting machine by 1st Embodiment of this invention. It is the top view which showed the state in which an imaging process is performed in parallel with the adsorption | suction process by the adsorption | suction part by the side of X2 of the mounting machine by 1st Embodiment of this invention. It is the schematic diagram which showed the state in which an imaging process is performed in parallel with the adsorption | suction process by the adsorption | suction part by the side of X1 of the mounting machine by 1st Embodiment of this invention. It is the top view which showed the state in which an imaging process is performed in parallel with the adsorption | suction process by the adsorption | suction part by the side of X1 of the mounting machine by 1st Embodiment of this invention. FIG. 7A is a diagram illustrating a state before the start of adsorption. FIG. 7B is a diagram illustrating a state in which the X2 side suction portion is rotated from the initial position to the suction position. FIG. 7C is a diagram illustrating a state in which the X2 side suction portion is rotated from the suction position to the initial position. FIG. 7D is a diagram illustrating a state in which the X1 side suction portion starts rotating from the initial position to the suction position. FIG. 7E is a diagram illustrating a state in which the X1 side suction portion is rotated from the initial position to the suction position. It is the flowchart which showed the adsorption | suction process of the mounting machine by 1st Embodiment of this invention, an imaging process, and a recognition process. It is the figure which showed the whole structure of the mounting machine by 2nd Embodiment of this invention. It is a block diagram of the mounting machine by 2nd Embodiment of this invention. It is the figure which showed the taking-out apparatus of the mounting machine by 2nd Embodiment of this invention. It is the figure which showed the adsorption position and imaging region of the mounting machine by 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the structure of the mounting machine 100 according to the first embodiment of the present invention will be described with reference to FIGS. The mounting machine 100 is an example of the “substrate processing apparatus” in the present invention.

  As shown in FIG. 1, the mounting machine 100 is a mounting machine that takes out a chip (bare chip) T from a diced wafer W and mounts (mounts) it on a substrate 500 at a predetermined mounting work position 500a (500b). The wafer W includes chips T arranged in a matrix in a first direction (hereinafter referred to as X direction) and a second direction (hereinafter referred to as Y direction) substantially perpendicular to the X direction.

  The mounting machine 100 includes a base 1, a conveyor 2, and two mounting portions 3a and 3b. Further, the mounting machine 100 includes a wafer table 4, a take-out device 5, relay units 6a and 6b, chip placement units 7a and 7b, transfer stations 8a and 8b, and component recognition imaging units 9a and 9b. ing. As shown in FIG. 2, the mounting machine 100 includes a controller 10 that controls the mounting machine 100 and a display unit 15 that displays information about the mounting machine 100.

  As shown in FIG. 1, the base 1 includes a conveyor 2, a wafer table 4, a take-out device 5, a relay unit 6a (6b), a chip placement unit 7a (7b), a transfer station 8a (8b), and component recognition. The imaging unit 9a (9b) is supported.

  The conveyor 2 is configured to transport the substrate 500 from the X1 direction to the X2 direction. Specifically, the conveyor 2 is configured to carry the substrate 500 into a predetermined mounting operation position 500a (500b) and to carry out the substrate 500 on which the chip T is mounted from the predetermined mounting operation position 500a (500b). Has been.

  The mounting portion 3a (3b) is disposed at a position higher than the substrate 500. Further, each of the mounting portions 3a (3b) is configured to be movable in the X direction with respect to the X bar 110 when driven by an X-axis motor 161 (see FIG. 2). The mounting portions 3a (3b) are configured to be independently movable in the X direction along the X bar 110. The X bar 110 is configured to be movable in the Y direction with respect to the Y bar 120 by driving a Y-axis motor 162 (see FIG. 2). As a result, the two mounting portions 3a and 3b can both move in the horizontal direction (XY direction). Further, the mounting unit 3a (3b) includes a plurality of mounting heads 31a (31b) and one board recognition imaging unit 32a (32b). Two X-axis motors 161 (see FIG. 2) are provided to drive each of the mounting portions 3a and 3b, but only one is shown in FIG. 2 in a simplified manner.

  Each of the plurality of mounting heads 31a (31b) is configured to move in the vertical direction (Z direction) when the Z-axis motor 163 (see FIG. 2) is driven. Each of the plurality of mounting heads 31a (31b) is configured to rotate around an axis line (R direction) parallel to the Z direction when the R axis motor 164 (see FIG. 2) is driven. . The mounting head 31a (31b) is configured to suck the chip T and mount it on the substrate 500. A plurality of Z-axis motors 163 and a plurality of R-axis motors 164 (see FIG. 2) are provided, but in FIG. 2, only one each is shown in a simplified manner.

  The board recognition imaging unit 32a (32b) includes a camera and is configured to take an image of the board 500 from above. Further, the R-axis motor 164 (see FIG. 2) is driven based on the image information of the substrate 500 imaged by the substrate recognition imaging unit 32a (32b). The mounting head 31a (31b) is controlled so that the position of the chip T is adjusted (corrected) and the chip T is mounted on the substrate 500.

  The wafer table 4 is driven in the X, Y, and R directions by driving each of the X-axis motor 171, Y-axis motor 172, Z-axis motor 173, and R-axis motor 174 shown in FIG. The position relative to the table 1 can be changed (adjusted). The wafer table 4 is configured to be movable in the Y direction with respect to the base 1 in a state where the wafer W is fixedly held by driving the Y-axis motor 172. In addition, the wafer table 4 is configured to move between an extraction work position of the chip T in the state shown in FIG. 1 and a wafer replacement position where the wafer W from which the chip T has been removed is replaced with a new wafer W. Yes.

  The wafer table 4 is configured to hold the wafer W substantially at the center in plan view. Further, the chip T of the wafer W is pushed up from below the wafer table 4 by a push-up device (not shown) and then sucked by a suction unit 51 described later.

  Here, in the first embodiment, the take-out device 5 includes a suction unit 51 and a wafer recognition imaging unit 56 as shown in FIGS. 3 and 5. Further, a pair of suction portions 51 are arranged so as to sandwich the wafer table 4 from the left-right direction (X direction). Hereinafter, the X2 side suction part 51 is referred to as a suction part 51a, and the X1 side suction part 51 is referred to as a suction part 51b. The suction part 51a includes a first part 52a, a second part 53a, a base part 54a (see FIG. 1), and a suction head 55a. The suction portion 51b includes a first portion 52b, a second portion 53b, a base portion 54b (see FIG. 1), and a suction head 55b. Further, the suction head 55a (55b) is provided in the vicinity of the tip on the Y1 side of the first portion 52a (52b). Moreover, the adsorption | suction part 51a is comprised so that the motor 181 (refer FIG. 2) may be rotated around the rotation axis parallel to a Y direction. Similarly, the suction portion 51b is configured to be rotated around a rotation axis parallel to the Y direction by a motor 182 (see FIG. 2). Further, the upper surface (the surface on the Z1 side) of the chip T is sucked by the suction head 55a (55b) at the predetermined position P0 where the chip T is sucked. Further, when the suction part 51a (51b) is rotated from the suction position P2 to the initial position P1, the chip T is arranged such that the surface disposed on the Z2 side at the suction position P2 faces upward (Z1 side). Arranged (flipped). Further, as shown in FIG. 7, when viewed from the Y direction, the suction head 55a of the suction portion 51a disposed at the suction position P2 and the suction head 55b of the suction portion 51b disposed at the suction position P2 coincide ( Corresponding). In addition, the position of the wafer recognition imaging unit 56, the end portion on the X2 side of the second portion 53a of the suction portion 51a, and the position of the end portion on the X1 side of the second portion 53b of the suction portion 51b are fixed. . The wafer recognition imaging unit 56 is an example of the “imaging unit” in the present invention.

  Moreover, the adsorption | suction part 51a has the substantially L shape to which the 2nd part 53a and the 1st part 52a were connected, as shown in FIG.3 and FIG.5. The suction portion 51b is connected to the second portion 53b and the first portion 52b. In addition, since the adsorption | suction part 51a and 51b are the structures substantially the same except that, below, only the adsorption | suction part 51a is demonstrated and description of the adsorption | suction part 51b is abbreviate | omitted.

  As shown in FIG. 4, the first portion 52 a is configured so as to be in an imaging region R (to be described later) of the wafer recognition imaging unit 56 and to extend in the Y direction when viewed in a plan view. Further, the width of the first portion 52a in the X direction is smaller than the width of the imaging region R in the X direction. Specifically, the width of the first portion 52a in the X direction is about ¼ of the width of the imaging region R in the X direction. In addition, the first portion 52a is configured such that the tip portion on the Y1 side is disposed at a position separated from the outer edge on the Y1 side of the imaging region R by a predetermined distance.

  The second portion 53a is configured to protrude outside the imaging region R of the wafer recognition imaging unit 56 during the suction process. The second portion 53a is generally configured to extend in the X direction. Further, the X-side end portion (rotation center) of the second portion 53a is rotatably supported by the base portion 54a so that the adsorption portion 51a can rotate around a rotation axis extending in the Y direction. It is configured. Further, as shown in FIG. 7, the suction portion 51a rotates (moves) from the initial position P1 (rotation start position) to the suction position P2 and sucks the chip T, and then from the suction position P2. It is configured to rotate to the initial position P1.

  Further, the suction portion 51a is configured to be movable relative to the wafer W as shown in FIGS. Specifically, since the position of the end portion (rotation center) on the X2 side of the second portion 53a of the suction portion 51a is fixed, the end of the second portion 53a on the X2 side is moved by the movement of the wafer table 4. The wafer table 4 moves relative to the position of the part (the relative position of the wafer W and the suction part 51a is changed). The suction unit 51a sequentially sucks chips T in a predetermined row (for example, the nth row) arranged along the X direction, and then the next row (for example, the n + 1th row) of the predetermined row in the Y direction. The chips T arranged along the X direction are sequentially sucked.

  As shown in FIG. 1, the wafer recognition imaging unit 56 includes a camera and has a function of imaging a wafer W including a plurality of chips T. Further, the wafer recognition imaging unit 56 is fixedly arranged. Further, the wafer recognition imaging unit 56 is configured to be movable relative to the wafer W. Specifically, the position of the wafer recognition imaging unit 56 is fixed, and the wafer table 4 moves relative to the position of the wafer recognition imaging unit 56 by moving the wafer table 4 (wafer W and wafer). The relative position of the recognition imaging unit 56 is changed). Further, as shown in FIGS. 3 to 6, the wafer recognition imaging unit 56 has a substantially rectangular imaging region R having a long side along the X direction. Further, the wafer recognition imaging unit 56 is arranged so that the chip T adsorbed by the adsorption unit 51a (51b) fits in the center of the imaging region R. The imaging region R is configured to have a size that can accommodate a plurality of chips T. Therefore, the wafer recognition imaging unit 56 has a chip T other than the first part 52a (52b) and the first part 52a (52b) that fit in the imaging region R in a state where the suction part 51a (51b) is disposed at the suction position P2. It is configured to capture an image of (wafer W). In the imaging region R, the first portion 52a (52b) of the suction portion 51 is stored at a position corresponding to the position of the approximate center of the imaging region R in the X direction. Note that the number of chips T stored in the imaging region R differs depending on the size of the chip T.

  As shown in FIG. 1, the two relay units 6a and 6b have a function of delivering the chip T sucked by the suction part 51a (51b) to the two chip mounting parts 7a and 7b, respectively. The relay units 6a and 6b are configured to move in the Y direction by motors 191 and 192 (see FIG. 2), respectively.

  The chip mounting portions 7a and 7b are configured such that the chips T transferred from the relay units 6a and 6b are mounted thereon, respectively. The chips T placed on the chip placement unit 7a (7b) are configured to be attracted by the mounting head 31a (31b) moved to the position of the chip placement unit 7a (7b). Yes.

  The two transfer stations 8a and 8b are provided for applying an adhesive (flux) to the chip T adsorbed by the mounting head 31a (31b).

  The two component recognition imaging units 9a and 9b include a camera and are configured to image the lower surface of the chip T that is attracted (held) to the mounting head 31a (31b).

  As illustrated in FIG. 2, the controller 10 includes a storage unit 11, an arithmetic processing unit 12, a motor control unit 13, and an image processing unit 14.

  The storage unit 11 stores various programs and data related to mounting work such as mounting programs, transport system data, and equipment specific data.

  The arithmetic processing unit 12 (hereinafter referred to as main CPU 12) includes a CPU, and is configured to control the mounting machine 100 using the program and data in the storage unit 11. The main CPU 12 is configured to cause the wafer recognition imaging unit 56 to image a plurality of chips T including the chip T adsorbed next to the chip T at the predetermined position P0 in parallel with the adsorption processing. Further, the main CPU 12 is configured to execute the imaging process at a timing at which the suction head 55a (55b) sucks the chip T in the time during which the suction process is performed. Details of the main CPU 12 will be described later.

  The motor control unit 13 includes a CPU, and is configured to receive commands from the main CPU 12 and control operations of various motors (see FIG. 2).

  The image processing unit 14 (hereinafter referred to as an image processing CPU 14) includes a CPU, and uses the program and data stored in the storage unit 11, and uses a component recognition imaging unit 9a (9b), a board recognition imaging unit 32a (32b), and a wafer recognition imaging unit. 56 is configured to recognize the captured image.

  Here, in the first embodiment, the main CPU 12 (see FIG. 2) executes a suction process for sucking the chip T of the wafer W by the suction head 55a (55b), and in parallel with the suction process, the wafer recognition imaging unit. An image pickup process for picking up an image of the wafer W on which the suction process is executed by 56 is executed. Specifically, the main CPU 12 performs a suction process in which the chip T at the predetermined position P0 of the wafer W is sucked by the suction head 55a (55b), and in parallel with the suction process, the wafer recognition imaging unit 56 performs the predetermined position P0. And picking up an image of a part of the chips T adsorbed after the chip T at the predetermined position P0 to be adsorbed (the chip T adsorbed next to the chip T at the predetermined position P0). It is configured to perform processing. Further, the main CPU 12 moves the wafer table 4 based on the image recognized by the recognition process, executes the suction process so that the chip T can be sucked at an appropriate position, and executes the imaging process in parallel with the suction process. Is configured to do. In addition, after the suction process for the chip T at the predetermined position P0 is executed, the imaging process for the chip T that is executed in the vicinity of the predetermined position P0 and after the chip T is executed. Even if the chip T near the predetermined position P0 is displaced due to the suction of the chip T at the predetermined position P0, the image is picked up after the suction processing for the chip T at the predetermined position P0 is executed. The suction process of the chip T sucked after the chip T at the predetermined position P0 is accurately executed in the vicinity of the predetermined position P0 and based on the image of the chip T on which the suction process is executed after the chip T. be able to.

  In addition, the main CPU 12 is configured to execute an imaging process in parallel with the suction process and transfer an image captured by the imaging process to the image processing CPU 14 (see FIG. 2). The image processing CPU 14 is configured to execute a recognition process for recognizing the state of the chip T based on the transferred image in parallel with the suction process. That is, while the main CPU 12 performs the suction process of the chip T at the predetermined position P0, the wafer recognition imaging unit 56 captures an image of the chip T that is sucked next to the chip T at the predetermined position P0 (the imaging process by the main CPU 12). The image processing CPU 14 recognizes this image. Then, the main CPU 12 acquires in advance (first) the information of the next chip T to be sucked while performing the suction process of the chip T at the predetermined position P0. Thereby, the time required for the imaging process and the recognition process of the chip T can be absorbed in the time required for the suction process of the chip T.

  Next, the operation of the wafer table 4 will be described with reference to FIGS.

  As shown in FIGS. 3 to 6, the wafer table 4 is sequentially formed from a tip T in the X2 direction to a tip T in the X1 direction of a predetermined row (for example, the nth row in FIGS. 4 and 6). Then, it moves in the X2 direction so as to be arranged at the arrangement position of the adsorption head 55a (55b) of the adsorption part 51a (51b) at the adsorption position P2. Thereafter, the wafer table 4 has a tip T in the X1 direction of the next row (n + 1th row) after the predetermined row in the Y direction of the suction head 55a (55b) of the suction portion 51a (51b) at the suction position P2. Move to correspond to the placement position. Thereafter, in the wafer table 4, the suction head 55a (55b) of the suction part 51a (51b) at the suction position P2 is sequentially arranged from the tip chip T in the X1 direction to the tip chip T in the X2 direction of the next row after the predetermined row. ) To move in the X1 direction so as to be arranged at the arrangement position. Thereafter, on the wafer table 4, the tip chip T in the X2 direction of the next row (n + 2) in the Y direction is positioned at the position of the suction head 55a (55b) of the suction portion 51a (51b) at the suction position P2. Move to correspond. When the wafer table 4 repeats these operations, the chips T are sequentially arranged at the arrangement position of the adsorption head 55a (55b) of the adsorption unit 51a (51b) at the adsorption position P2. “Row” means an arrangement in the X direction of the chips T arranged in a matrix on the wafer W, and “Column” means an arrangement in the Y direction of the chips T.

  Next, with reference to FIG. 7, the operation in which the suction units 51a and 51b suck the chip T will be described.

  The X1 side suction portion 51a and the X2 side suction portion 51b are configured to alternately suck the chips T from the wafer W. Specifically, the suction portion 51a on the X2 side has an initial position such that the suction head 55a corresponds to the position of the chip T in a predetermined column (for example, the mth column) in a predetermined row (for example, the nth row). It is rotated from P1 to the suction position P2 (see FIG. 7A). Next, the suction head 55a on the X2 side sucks the chips T in a predetermined row (m-th row) (see FIG. 7B). Next, the suction head 55a on the X2 side is rotated from the suction position P2 to the initial position P1 in a state where the chip T is sucked (see FIG. 7C). At this time, the relay unit 6a receives the chip T from the suction head 55a rotated to the initial position P1, and transfers the chip T to the chip mounting portion 7a (see FIG. 1). At this time, the wafer table 4 is moved in the X2 direction so that the next row (m + 1) th chip T is arranged at the suction position P2. Next, the suction portion 51b on the X1 side moves from the initial position P1 to the suction position P2 so that the suction head 55b corresponds to the position of the chip T in a predetermined column (m + 1 column) in a predetermined row (nth row). It is rotated (see FIG. 7D). Next, the suction head 55b on the X1 side sucks the chips T in a predetermined column (m + 1 column) (see FIG. 7E). Thereafter, the suction head 55b on the X1 side is rotated from the suction position P2 to the initial position P1 while the chip T is sucked. Then, the wafer table 4 is moved in the X2 direction so that the next row (m + 2nd row) of chips T are arranged at the suction position P2. These operations are repeated, and the chips T are sequentially sucked (taken out) from the wafer W. Note that in the odd-numbered rows, the chips T are sequentially attracted from the X2 direction to the X1 direction, and in the even-numbered rows, the chips T are sequentially attracted from the X1 direction to the X2 direction.

  Next, with reference to FIG. 2, FIG. 7, and FIG. 8, the suction process, the imaging process, and the recognition process of the mounting machine 100 will be described. The main CPU 12 executes suction processing and imaging processing, and the image processing CPU 14 executes recognition processing.

  First, processes (steps S1 to S6) related to the adsorption process will be described.

  In step S <b> 1, the main CPU 12 acquires a suction address (position information of the chip T) from the storage unit 11. That is, the main CPU 12 acquires information on the wafer W held on the wafer table 4, and acquires position information on the chip T to be sucked by the suction unit 51.

  Next, in step S2, the main CPU 12 determines whether or not an image centered on the chip T at the predetermined position P0 to be sucked has been recognized. Note that the image recognition CPU 14 executes the image recognition process centered on the chip T to be attracted in step S14. The main CPU 12 repeats this process until the image T CPU 14 recognizes the center image of the chip T to which the image processing CPU 14 is attracted. When the image T CPU 14 recognizes the center image of the chip T, the main CPU 12 proceeds to Step S3.

  Next, in step S3, the main CPU 12 executes an adsorption process. Specifically, the main CPU 12 rotates the suction head 55a or 55b to a position corresponding to the chip T at the predetermined position P0 to be sucked, and sucks the chip T onto the suction head 55a or 55b. If the main CPU 12 determines that the chip T is defective in step S14, the main CPU 12 proceeds to step S4 without sucking the chip T determined to be defective.

  Next, in step S <b> 4, the main CPU 12 updates the suction address and stores it in the storage unit 11.

  Next, in step S <b> 5, the main CPU 12 determines whether there are other chips T to be attracted on the wafer W. If there is another chip T to be attracted, the process proceeds to step S6. On the other hand, if there is no other chip T to be sucked, the process (steps S1 to S6) related to the sucking process is ended.

  Next, in step S <b> 6, the main CPU 12 performs a process of moving the wafer table 4. Specifically, the main CPU 12 performs a process of moving the wafer table 4 so that the suction process of the chip T next to the chip T at the predetermined position P0 for which the suction process has been performed in step S3 can be performed.

  Next, processes related to the imaging process and the recognition process (steps S11 to S16) will be described. Steps S11 to S16 are performed in parallel with steps S1 to S6.

  First, in step S <b> 11, the main CPU 12 acquires a recognition address (information regarding whether or not the chip T has been recognized) from the storage unit 11.

  Next, in step S12, the main CPU 12 determines whether or not an image centered on the chip T to be sucked has been captured. When the main CPU 12 determines that an image centered on the chip T to be sucked has been captured, the main CPU 12 advances the processing to step S14. On the other hand, if the main CPU 12 determines that an image centered on the chip T to be sucked has not been captured, the main CPU 12 advances the processing to step S13.

  Next, in step S13, the main CPU 12 executes an imaging process. Specifically, the main CPU 12 performs processing for capturing an image centered on the chip T to be sucked.

  Next, in step S14, the image processing CPU 14 executes a recognition process. Specifically, the image processing CPU 14 (see FIG. 2) receives a command from the main CPU 12 and performs recognition (analysis) processing on the appearance of the chip T based on an image centered on the chip T to be sucked. In the recognition process, for example, the image processing CPU 14 recognizes that the adjacent chip T is not properly diced (a chip T that should have been originally separated is connected) or the chip T has a crack. If it is recognized that the chip T is defective, the chip T is determined to be defective. On the other hand, the image processing CPU 14 determines that the chip T is normal when the chip T is not defective. In addition, when the image processing CPU 14 executes the recognition processing, a portion that has already been recognized (a portion that has already been recognized in the previous recognition processing image) in the center image of the chip T to be sucked. Does not perform recognition processing. In other words, the image processing CPU 14 performs recognition processing for a newly reflected portion of the image centered on the chip T to be sucked.

  Next, in step S <b> 15, the main CPU 12 updates the recognition address and stores it in the storage unit 11.

  Next, in step S <b> 16, the main CPU 12 determines whether there is another chip T to be recognized on the wafer W. When there is another chip T to be recognized on the wafer W, the main CPU 12 advances the process to step S11. On the other hand, when there is no other chip T to be recognized on the wafer W, the main CPU 12 ends the processes (steps S11 to S16) related to the imaging process and the recognition process.

  As described above, the main CPU 12 parallels the processing (steps S1 to S6) related to the suction processing of the chip T at the predetermined position P0 to be sucked, to the predetermined position P0 chip T and the predetermined position P0 to be sucked. Processing (steps S11 to S16) related to the imaging processing and recognition processing of the chip including the chip T adsorbed next to the chip T is executed.

  In the first embodiment, the following effects can be obtained.

  In the first embodiment, as described above, the suction process for sucking the chip T of the wafer W is performed by the suction unit 51a (51b), and the suction process is performed by the wafer recognition imaging unit 56 in parallel with the suction process. There is provided a main CPU 12 configured to execute an imaging process for imaging the wafer W to be imaged. Thus, unlike the case where the suction process and the imaging process are executed at different timings, the imaging process can also be executed during the suction process. Thereby, the time required for substrate processing can be reduced.

  In the first embodiment, an adsorption process for adsorbing the chip T at the predetermined position P0 of the wafer W is performed by the adsorption unit 51a (51b), and in parallel with the adsorption process, the wafer recognition imaging unit 56 sets the predetermined position P0. The main CPU 12 is configured to execute an image pickup process for picking up an image of some of the chips T that are sucked in the vicinity and after the chip T at the predetermined position P0 to be sucked. Thereby, while performing the suction process for the chip T at the predetermined position P0, imaging of the chip T in which the suction process is executed in the vicinity of the predetermined position P0 and after the chip T at the predetermined position P0 is performed. Since the chip T having a close suction timing can be imaged first), the time required for the imaging process of the chip T having a close suction timing can be absorbed in the time of the suction processing of the chip T at the predetermined position P0. it can. As a result, the time required for substrate processing can be easily reduced.

  In the first embodiment, in parallel with the suction process, the main CPU 12 is configured to execute an image pickup process for picking up an image of the chip T sucked next to the chip T at the predetermined position P0 by the wafer recognition image pickup unit 56. . As a result, during the suction process for the chip T at the predetermined position P0, the chip T to which the suction process is performed next to the chip T at the predetermined position P0 is imaged (the next chip T to be sucked is imaged first). Therefore, the time required for the imaging process of the chip T with the latest suction timing can be absorbed in the time of the suction process of the chip T at the predetermined position P0. As a result, the time required for the substrate processing can be easily reduced even when the imaging processing of the chip T with the latest suction timing is executed.

  In the first embodiment, in parallel with the suction process, the wafer recognition imaging unit 56 executes an imaging process for imaging a plurality of chips T including the chip T sucked next to the chip T at the predetermined position P0. The main CPU 12 is configured. Thereby, while performing the suction process for the chip T at the predetermined position P0, it is possible to simultaneously perform imaging of a plurality of chips T on which the suction process is sequentially executed after the chip T at the predetermined position P0. The images of the plurality of chips T can be efficiently acquired by the imaging processing of the degree.

  In the first embodiment, the suction unit 51a (51b) moves from the initial position P1 to the suction position P2 and sucks the chip T, and then moves to the initial position P1 from the suction position P2. Then, the main CPU 12 is configured to execute the imaging process. Thereby, not only during the operation of sucking the chip T, but also during the movement of the suction portion 51a (51b) from the initial position P1 to the suction position P2 and during the movement from the suction position P2 to the initial position P1, the imaging process is performed. Can be executed in parallel.

  In the first embodiment, the main CPU 12 is configured to execute the imaging process at the timing when the suction unit 51a (51b) sucks the chip T while the suction process is being performed. Thereby, an imaging process can be reliably performed while performing an adsorption | suction process.

  In the first embodiment, the main CPU 12 is configured to execute the imaging process in parallel with the suction process and transfer the image captured by the imaging process to the image processing CPU 14, and in parallel with the suction process, Based on the transferred image, the image processing CPU 14 is configured to execute a recognition process for recognizing the state of the chip T. Thus, unlike the case where the suction process, the imaging process, and the recognition process are executed at different timings, the recognition process is executed in addition to the imaging process during the suction process (the next wafer W to be sucked is imaged first). , The state of the wafer W can be recognized). Thereby, the time required for substrate processing can be further reduced.

  In the first embodiment, the chips T arranged in a predetermined row along the X direction are sequentially sucked, and then the chips T arranged along the X direction of the next row after the predetermined row in the Y direction are used. The suction unit 51a (51b) is configured to sequentially suck, and in a plan view, a suction head 55a (55b) that is in the imaging region R of the wafer recognition imaging unit 56 and extends in the Y direction in the suction process is provided. The suction portion 51a (51b) is configured to include one portion 52a (52b). Thus, unlike the case where the first portion 52a (52b) of the suction portion 51a (51b) that fits in the imaging region R during the suction processing extends in the X direction, the suction of the chips T in a predetermined row along the X direction. Even if the imaging process is executed in parallel with the process, it is possible to suppress the area of the chip T to be imaged from being narrowed by the first portion 52a (52b) of the suction unit 51a (51b).

  Moreover, in 1st Embodiment, the adsorption | suction part 51a (51b) containing the 1st part 52a (52b) and the 2nd part 53a (53b) is formed in a substantially L shape. Thereby, the adsorption | suction part 51a (51b) can be easily supported by the 2nd part 53a (53b), suppressing the area | region of the chip | tip T to be imaged becoming narrow.

  In the first embodiment, the main CPU 12 is configured to move the wafer table 4 based on the image recognized by the recognition process to execute the suction process, and execute the imaging process in parallel with the suction process. Thus, unlike the case where the wafer recognition imaging unit 56 and the suction unit 51a (51b) are moved in order to perform the imaging process and the suction process, it is possible to execute the imaging process and the suction process by moving only the wafer table 4. it can. That is, since the number of parts to be moved can be reduced, the structure of the mounting machine 100 can be simplified.

(Second Embodiment)
Hereinafter, the configuration of the mounting machine 200 according to the second embodiment of the present invention will be described with reference to FIGS. The mounting machine 200 is an example of the “substrate processing apparatus” in the present invention.

  In the second embodiment, unlike the first embodiment including the L-shaped suction portion 51a (51b) that rotates around the rotation axis extending in the Y direction, the take-out device 105 is around the rotation axis extending in the X direction. Next, the mounting machine 200 including the suction part 151 that rotates in the direction will be described.

  As shown in FIG. 9, the mounting machine 200 is a mounting machine capable of taking out the chip T from the diced wafer W and mounting (mounting) it on the substrate 500 at a predetermined mounting work position 500c.

  The mounting machine 200 includes a base 1, a conveyor 2, and a mounting unit 103. Further, the mounting machine 200 includes the wafer table 4, the take-out device 105, the transfer station 108, and one component recognition imaging unit 109.

  As shown in FIG. 1, the base 1 supports a conveyor 2, a wafer table 4, a take-out device 105, a transfer station 108, a component recognition imaging unit 109, and the like.

  The conveyor 2 is configured to transport the substrate 500 from the X1 direction to the X2 direction. Specifically, the conveyor 2 is configured to carry the substrate 500 into a predetermined mounting operation position 500c and to carry out the substrate 500 from the predetermined mounting operation position 500c.

  One mounting unit 103 is provided. Further, the mounting unit 103 includes a plurality of mounting heads 131 and one board recognition imaging unit 132. The mounting unit 103 is configured to receive the chip T sucked by the sucking unit 151. The mounting unit 103 applies an adhesive (flux) to the chip T at the transfer station 108 and mounts the chip T on the substrate 500.

  The board recognition imaging unit 132 includes a camera and is configured to take an image of the board 500.

  Here, in the second embodiment, the wafer table 4 is configured not to move during the mounting operation in which the chip T is mounted on the substrate 500.

  In the second embodiment, the take-out device 105 includes a suction unit 151, a wafer recognition imaging unit 153, an X bar 154, and a Y bar 155. The adsorption unit 151 and the wafer recognition imaging unit 153 are provided so as to sandwich the X bar 154 as shown in FIGS. Further, the suction unit 151 and the wafer recognition imaging unit 153 are configured to move in the X direction along the X bar 154 independently of each other. Further, as shown in FIG. 11, when the X bar 154 moves in the Y direction along the Y bar 155, both the suction unit 151 and the wafer recognition imaging unit 153 are configured to move in the Y direction.

  The suction part 151 includes a pair of suction heads 152a and 152b. The suction head 152a (152b) is configured to be rotatable about an axis parallel to the X-axis direction and to be movable in the vertical direction (up and down).

  The suction head 152a (152b) is configured in a bar shape. Further, the rod-like suction head 152a (152b) can suck the chip T at each of both end portions. That is, two chips T can be sucked by one suction head 152a (152b). Further, the suction heads 152a (152b) are configured to be independently movable in the Z direction. The suction head 152a (152b) is configured to be rotatable about a rotation axis (R direction) extending in the X direction independently.

  The wafer recognition imaging unit 153 includes a camera and has a function of imaging a wafer W including a plurality of chips T.

  Next, the relationship between the suction position P2 and the imaging region R will be described with reference to FIG. For simplification, in FIG. 12, the suction head 152b is not shown, and only the suction head 152a is illustrated.

In the second embodiment, as shown in FIG. 12, the center of the suction head 152a (152b) and the center of the wafer recognition imaging unit 153 (center of the imaging region R) in plan view are distances in the Y direction. Separated by D. Further, the Y2 side edge of the imaging region R and the Y2 side edge of the chip T at the suction position P2 are separated by ΔY described by the following equation (1).
ΔY = {D− (Lr / 2) + (Lt / 2)} (1)
Then, α, which is a value indicating how many times the distance ΔY corresponds to the length of the chip T in the Y direction, is described by the following equation (2).
α = ΔY / Lt
= {D- (Lr / 2) + (Lt / 2)} / Lt (2)
Note that Lr is the length of the imaging region R in the Y direction, and Lt is the length of the chip T in the Y direction.

  While the n-th line adsorption process is being performed (in parallel with the n-th line adsorption process), an area from the (n + α) line to the {(n + α) + (Lr−Lt) / Lt} line is imaged. An imaging process and a recognition process are performed on the chip T that is contained in the area R and does not protrude from the imaging area R in this area.

  For example, in the example shown in FIG. 12, D / Lt = 4, (Lr / 2) /Lt=1.7, and (Lt / 2) /Lt=0.5. In this example, α is about 2.8 according to Equation (2). In this case, when the suction processing of the first row is executed (n = 1), the wafer recognition imaging unit 153 is approximately 6.2 from the region after the approximately 3.8th row in the Y direction of the chip T. The area up to the line is stored in the imaging area R. For this reason, it is possible to perform the imaging process and the recognition process for the chips T in the fourth to sixth lines included in the imaging region R in parallel with the suction process in the first line.

  According to the mounting unit 103 of the second embodiment, since the wafer recognition imaging unit 153 can move independently of the suction unit 151 in the X direction, even if the suction process takes time, the suction unit 151. It is possible to perform the imaging process and the recognition process without depending on the adsorption state.

  In the second embodiment, the following effects can be obtained.

  In the second embodiment, as described above, the suction process for sucking the chips T of the wafer W is performed by the suction unit 151, and the suction process is performed by the wafer recognition imaging unit 153 in parallel with the suction process. A main CPU 12 is provided that is configured to execute an imaging process for capturing the image. Thus, unlike the case where the suction process and the imaging process are executed at different timings, the imaging process can also be executed during the suction process. Thereby, the time required for substrate processing can be reduced.

  In the second embodiment, the suction unit 151 and the wafer recognition imaging unit 153 are configured to move in the X direction independently of each other, and the main CPU 12 executes the imaging process in parallel with the suction process. Configure. Thereby, since the adsorption | suction part 151 and the wafer recognition imaging part 153 can be moved mutually independently, an imaging process can be easily performed in parallel with an adsorption | suction process.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first and second embodiments, the example in which the imaging process and the recognition process are executed in parallel with the suction process has been described, but the present invention is not limited to this. In the present invention, only the imaging process may be executed in parallel with the adsorption process.

  In the first and second embodiments, the example in which the imaging process is performed on a plurality of chips that are sucked after the predetermined chip on which the suction process is performed has been described. However, the present invention is not limited to this. . In the present invention, any number of chips to be imaged may be used as long as the imaging process is performed on at least one chip among the chips adsorbed next to the predetermined chip on which the adsorption process is performed.

  In the first and second embodiments, the example in which the imaging area of the imaging unit that images the chip on the wafer table is substantially rectangular has been described. However, the present invention is not limited to this. In the present invention, the imaging region may have a substantially rectangular shape, for example, a circular shape.

  Moreover, in the said 1st and 2nd embodiment, although the example with one wafer table was shown, this invention is not limited to this. In the present invention, two or more wafer tables may be provided.

  Moreover, although the example which comprised the adsorption | suction part in the substantially L shape was shown in the said 1st Embodiment, this invention is not limited to this. In this invention, you may comprise an adsorption | suction part in shapes other than a substantially L-shape, for example, the shape which has a linear shape and the bending position of 2 times or more.

  In the first and second embodiments, an example in which the recognition process is not performed a plurality of times for the same chip T has been described. However, the present invention is not limited to this. In the present invention, recognition processing may be performed a plurality of times for the same chip T. In this case, the suction process can be performed using the information of the recognition process based on the latest imaging process. Moreover, the information of the recognition process performed several times about the same chip | tip T may be averaged, and the adsorption | suction process may be performed based on this information.

  In the first and second embodiments, an example is shown in which the imaging region is configured so that a plurality of chips T can be accommodated, but the present invention is not limited to this. In the present invention, the imaging region may be configured so that one chip T can be accommodated.

  Moreover, in the said 1st Embodiment, although 2 adsorption | suction parts were provided in the taking-out apparatus, this invention is not limited to this. In this invention, you may provide one or three or more adsorption | suction parts in an extraction apparatus.

  In the second embodiment, an example in which the suction unit and the imaging unit move independently only in the X direction has been described. However, the suction unit and the imaging unit move independently in both the X direction and the Y direction. (It may move completely independently.)

  In the first and second embodiments, for convenience of explanation, the processing of the control unit has been described using a flow-driven flow that performs processing in order along the processing flow. For example, the processing operation of the control unit May be performed by event-driven (event-driven) processing that executes processing in units of events. In this case, it may be performed by a complete event drive type or a combination of event drive and flow drive.

4 Wafer table 12 Main CPU (control unit)
14 Image Processing CPU (Image Processing Unit)
51a, 51b, 151 Suction part 52a, 52b First part 53a, 53b Second part 55a, 55b, 152a, 152b Suction head 56, 153 Wafer recognition imaging part (imaging part)
100, 200 Mounting machine (substrate processing equipment)
n Predetermined line P0 Predetermined position P1 Initial position P2 Suction position R Imaging area T Chip W Wafer X direction First direction Y direction Second direction

A substrate processing apparatus according to an aspect of the present invention has an image pickup unit that picks up an image of a wafer including a plurality of chips, is movable relative to the wafer, and a suction head that sucks the chips from the wafer. In contrast, the controller includes a suction unit that is relatively movable, and a control unit. The control unit performs a suction process of sucking the wafer chip by the suction unit, and performs the suction process by the imaging unit in parallel with the suction process. and it is configured to perform an imaging of the wafer to be performed.

In the substrate processing apparatus according to one aspect of the present invention, as described above, an adsorption process for adsorbing a chip of a wafer by the adsorption unit is performed, and in parallel with the adsorption process, the adsorption process is performed by the imaging unit . by providing a control unit configured to perform an imaging, unlike the case of executing at different times and image shooting and adsorption treatment, it is possible to run an imaging while performing the adsorption treatment. Thereby, the time required for substrate processing can be reduced (tact time can be shortened).

In the substrate processing apparatus according to the one aspect described above, preferably, the control unit performs an adsorption process for adsorbing a chip at a predetermined position of the wafer by the adsorption unit, and in the vicinity of the predetermined position by the imaging unit in parallel with the adsorption process. and it is configured to perform an imaging of a portion of the chip of the chip to be adsorbed after the predetermined position of the chip to be adsorbed. If comprised in this way, while performing the adsorption | suction process about the chip | tip of a predetermined position, the imaging | photography of the chip | tip in which the adsorption | suction process is performed in the vicinity of a predetermined position and after the chip | tip of a predetermined position is performed. since the chip close timing ahead keep captured) it may, it is possible to absorb the time required for an imaging chip close timing to adsorb to the time of the adsorption process of the predetermined position of the chip. As a result, the time required for substrate processing can be easily reduced.

In this case, preferably, the control unit, in parallel with the adsorption process, and is configured to perform an imaging chip that are adsorbed to the next predetermined position of the chip by the imaging unit. If comprised in this way, while performing the adsorption | suction process about the chip | tip of a predetermined position, the chip | tip in which an adsorption | suction process is performed next to the chip | tip of a predetermined position is imaged. since it is put) that can be absorbed time the timing of the adsorption takes to an imaging of the most recent chip to the chip time of the adsorption treatment of the predetermined position. As a result, when the timing of adsorption IMAGING most recent chip is executed, it is possible to easily reduce the time required for substrate processing.

In the vicinity of the predetermined position, and, in a configuration in which an imaging of a portion of the chip is performed among the chips to be adsorbed after the predetermined position of the chip to be adsorbed, parallel Preferably, the control unit includes a suction processing to, and is configured to perform an imaging of a plurality of chips including a chip to be adsorbed to the next predetermined position of the chip by the imaging unit. If comprised in this way, while performing the adsorption | suction process about the chip | tip of a predetermined position, since the imaging | photography of the several chip | tip which is sequentially performed after the chip | tip of a predetermined position can be performed simultaneously, once images can be efficiently acquired in an imaging multiple more chips.

In the substrate processing apparatus according to the above aspect, preferably, the control unit is parallel to the suction process, which is a process in which the suction unit moves from the initial position to the suction position to suck the chip and then moves from the suction position to the initial position. Thus , the imaging is performed. According to this structure, not only in operation for adsorbing chips, also during movement from the movement in and the suction position to the suction position the suction unit from the initial position to the initial position, run in parallel IMAGING be able to.

In this case, preferably, the control unit, the adsorption unit during the adsorption processing is performed is configured in the timing for adsorbing chip executes IMAGING. According to this structure, it is possible to reliably run an imaging while performing the adsorption treatment.

In the substrate processing apparatus according to the aforementioned aspect, preferably, the shooting further comprising a recognizing image processing unit image image, the control unit, in parallel with the adsorption treatment was image shooting in together when running the IMAGING The image is transferred to the image processing unit, and the image processing unit is configured to execute a recognition process for recognizing the state of the chip based on the transferred image in parallel with the suction process. According to this structure, adsorption treatment, and when to perform an imaging Contact and recognition process at different times different, the chip of the addition recognition process also executed (then adsorbed on an imaging while performing the adsorption treatment First, the image is taken and the state of the chip is recognized). Thereby, the time required for substrate processing can be further reduced.

In the configuration in which the image processing unit executes the recognition process, preferably, a wafer table that holds the wafer so as to be movable relative to the position of the imaging unit and the position of the suction unit when the chip is sucked. The control unit is configured to move the wafer table based on the image recognized by the recognition process, execute the suction process, and execute imaging in parallel with the suction process. According to this structure, in order to perform an imaging Contact and adsorption treatment, unlike the case of moving the image pickup unit and the suction unit, respectively, it is possible to perform an imaging Contact and adsorption treatment by moving only the wafer table. That is, since the number of parts to be moved can be reduced, the structure of the substrate processing apparatus can be simplified.

In the substrate processing apparatus according to the aforementioned aspect, preferably, the wafer includes chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction, and the suction portion is in the first direction. Configured to sequentially suck chips arranged along a predetermined row, and then move in the second direction to sequentially suck chips arranged along the first direction of the next row after the predetermined row, The suction unit and the imaging unit are configured to move in the first direction independently of each other, and the control unit is configured to perform imaging in parallel with the suction process. According to this structure, it is possible to move independently of one another adsorption unit and an imaging unit, easily, in parallel with the adsorption treatment, it is possible to perform an imaging.

Claims (11)

An imaging unit (56, 153) that images a wafer (W) including a plurality of chips (T) and is movable relative to the wafer;
An adsorbing portion (51a, 51b, 151) having an adsorbing head (55a, 55b, 152a, 152b) for adsorbing the chip from the wafer, and movable relative to the wafer;
A control unit (12),
The control unit executes an adsorption process for attracting the chip of the wafer by the adsorption unit, and performs an imaging process for imaging the wafer on which the adsorption process is performed by the imaging unit in parallel with the adsorption process. A substrate processing apparatus (100, 200) configured to perform.   The control unit performs the adsorption process for adsorbing the chip at a predetermined position of the wafer by the adsorption unit, and in parallel with the adsorption process, near the predetermined position (P0) by the imaging unit, and 2. The substrate processing apparatus according to claim 1, configured to execute the imaging process for imaging a part of the chips to be sucked after the chip at the predetermined position to be sucked. .   The said control part is comprised so that the said imaging process to which the said chip | tip adsorb | sucked next to the said chip | tip of the said predetermined position by the said imaging part may be performed in parallel with the said attraction | suction process. 2. The substrate processing apparatus according to 1.   The control unit is configured to execute the imaging process for imaging the plurality of chips including the chip adsorbed next to the chip at the predetermined position by the imaging unit in parallel with the adsorption process. The substrate processing apparatus according to claim 2.   The control unit is parallel to the suction process, which is a process of moving the suction unit from the suction position to the initial position after the suction unit moves from the initial position (P1) to the suction position (P2) and sucks the chip. The substrate processing apparatus according to claim 1, wherein the substrate processing apparatus is configured to execute the imaging process.   The substrate processing apparatus according to claim 5, wherein the control unit is configured to execute the imaging process at a timing at which the suction unit sucks the chip while the suction process is being performed. An image processing unit (14) for recognizing an image captured by the imaging process;
The control unit executes the imaging process in parallel with the suction process and transfers the image captured by the imaging process to the image processing unit,
The substrate processing according to claim 1, wherein the image processing unit is configured to execute a recognition process for recognizing a state of the chip based on the transferred image in parallel with the suction process. apparatus. The wafer includes the chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction,
The adsorbing portion sequentially adsorbs the chips in a predetermined row arranged along the first direction, and then arranged along the first direction in a row next to the predetermined row in the second direction. It is configured to adsorb chips sequentially,
The suction part is in the imaging region (R) of the imaging part in the suction process in a plan view and extends in the second direction to be provided with a suction head (55a, 55b). 51. The substrate processing apparatus of claim 1, wherein the substrate processing apparatus is configured to include 51b). The suction part is provided so as to be connected to the first part, and the second part (53a, 53b) extending in the first direction while protruding outside the imaging area of the imaging part during the suction process. In addition,
The substrate processing apparatus according to claim 8, wherein the suction portion including the first portion and the second portion has a substantially L shape in plan view. A wafer table (4) for holding the wafer so as to be movable relative to the position of the imaging unit and the position of the suction unit when the chip is sucked;
The control unit is configured to move the wafer table based on the image recognized by the recognition process, execute the suction process, and execute the imaging process in parallel with the suction process. The substrate processing apparatus according to claim 7. The wafer includes the chips arranged in a matrix in a first direction and a second direction substantially perpendicular to the first direction,
The suction unit sequentially sucks the chips in a predetermined row arranged along the first direction, and then moves in a second direction to move the chip in the row (n + 1) next to the predetermined row (n). Configured to sequentially adsorb the chips arranged along the first direction;
The adsorption unit and the imaging unit are configured to move in the first direction independently of each other,
The substrate processing apparatus according to claim 1, wherein the control unit is configured to execute the imaging process in parallel with the suction process.

Images