KR101779553B1 - 감소된 감지 지연 및 개선된 감지 마진을 갖는 sram 판독 버퍼 - Google Patents

감소된 감지 지연 및 개선된 감지 마진을 갖는 sram 판독 버퍼 Download PDF

Info

Publication number
KR101779553B1
KR101779553B1 KR1020167004905A KR20167004905A KR101779553B1 KR 101779553 B1 KR101779553 B1 KR 101779553B1 KR 1020167004905 A KR1020167004905 A KR 1020167004905A KR 20167004905 A KR20167004905 A KR 20167004905A KR 101779553 B1 KR101779553 B1 KR 101779553B1
Authority
KR
South Korea
Prior art keywords
sram cell
read
switch
inverter
sram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020167004905A
Other languages
English (en)
Korean (ko)
Other versions
KR20160037202A (ko
Inventor
성-욱 정
영휘 양
스탠리 승철 송
총제 왕
초 페이 옙
Original Assignee
퀄컴 인코포레이티드
연세대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드, 연세대학교 산학협력단 filed Critical 퀄컴 인코포레이티드
Publication of KR20160037202A publication Critical patent/KR20160037202A/ko
Application granted granted Critical
Publication of KR101779553B1 publication Critical patent/KR101779553B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G06F17/5072—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
KR1020167004905A 2013-08-02 2014-07-21 감소된 감지 지연 및 개선된 감지 마진을 갖는 sram 판독 버퍼 Active KR101779553B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/957,485 2013-08-02
US13/957,485 US9460777B2 (en) 2013-08-02 2013-08-02 SRAM read buffer with reduced sensing delay and improved sensing margin
PCT/US2014/047455 WO2015017164A1 (en) 2013-08-02 2014-07-21 Sram read buffer with reduced sensing delay and improved sensing margin

Publications (2)

Publication Number Publication Date
KR20160037202A KR20160037202A (ko) 2016-04-05
KR101779553B1 true KR101779553B1 (ko) 2017-09-18

Family

ID=51293186

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167004905A Active KR101779553B1 (ko) 2013-08-02 2014-07-21 감소된 감지 지연 및 개선된 감지 마진을 갖는 sram 판독 버퍼

Country Status (6)

Country Link
US (1) US9460777B2 (enExample)
EP (1) EP3028281B1 (enExample)
JP (1) JP6096991B2 (enExample)
KR (1) KR101779553B1 (enExample)
CN (1) CN105637589B (enExample)
WO (1) WO2015017164A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2887355A1 (en) * 2013-12-20 2015-06-24 IMEC vzw Data storage cell and memory arrangement
WO2019023700A1 (en) * 2017-07-28 2019-01-31 Chowdhury Masud H MEMORY STATIC LIFE 8T
US10438654B2 (en) * 2017-09-22 2019-10-08 Qualcomm Incorporated Transpose static random access memory (SRAM) bit cells configured for horizontal and vertical read operations
US11309431B2 (en) 2018-05-17 2022-04-19 Semiconductor Energy Laboratory Co., Ltd. Memory device, semiconductor device, and electronic device
CN113287170B (zh) 2019-01-05 2025-02-28 美商新思科技有限公司 存储数据的集成电路和存储该集成电路的数字表示的介质
CN109920459B (zh) * 2019-01-10 2021-01-15 中国人民武装警察部队海警学院 一种完全非对称的亚阈值单端9管存储单元
CN111883192B (zh) * 2020-07-20 2023-02-03 安徽大学 基于9t sram单元在内存实现汉明距离计算的电路及9t sram单元
CN112069768B (zh) * 2020-09-08 2024-07-16 飞腾信息技术有限公司 一种针对双端口sram输入输出延时优化的方法
CN112382326B (zh) * 2020-12-11 2023-11-17 北京中科芯蕊科技有限公司 一种亚阈值双电源sram读辅助电路
EP4356429A4 (en) * 2021-06-18 2025-08-13 Univ Southern California AUGMENTED MEMORY COMPUTING: A NEW PATH FOR EFFICIENT AI COMPUTING
US12249367B2 (en) 2022-04-13 2025-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Write assist circuit for memory device
CN114743580B (zh) * 2022-06-13 2022-09-02 中科南京智能技术研究院 一种电荷共享存内计算装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050180224A1 (en) 2004-02-13 2005-08-18 Nestor Tzartzanis Differential current-mode sensing methods and apparatuses for memories
US7400523B2 (en) 2006-06-01 2008-07-15 Texas Instruments Incorporated 8T SRAM cell with higher voltage on the read WL
US20100182823A1 (en) 2009-01-22 2010-07-22 Qualcomm Incorporated Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors
US20110305099A1 (en) 2010-05-12 2011-12-15 Stichting Imec Nederland Hierarchical buffered segmented bit-lines based sram

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0636315B2 (ja) 1983-12-23 1994-05-11 株式会社日立製作所 半導体メモリ
JP2004047003A (ja) * 2002-07-15 2004-02-12 Renesas Technology Corp 記憶装置
JP4528044B2 (ja) * 2004-07-13 2010-08-18 富士通セミコンダクター株式会社 半導体装置
US7106620B2 (en) * 2004-12-30 2006-09-12 International Business Machines Corporation Memory cell having improved read stability
JP2007213699A (ja) * 2006-02-09 2007-08-23 Toshiba Corp 半導体記憶装置
US20070242498A1 (en) * 2006-04-13 2007-10-18 Anantha Chandrakasan Sub-threshold static random access memory
US7502273B2 (en) * 2006-09-27 2009-03-10 Taiwan Semiconductor Manufacturing Co., Ltd. Two-port SRAM with a high speed sensing scheme
US20090161410A1 (en) * 2007-12-21 2009-06-25 Texas Instruments Inc. Seven transistor sram cell
US7660150B2 (en) * 2007-12-31 2010-02-09 Texas Instruments Incorporated Memory cell having improved write stability
US7606062B2 (en) * 2007-12-31 2009-10-20 Intel Corporation Ultra low voltage and minimum operating voltage tolerant register file
JP2009272023A (ja) 2008-05-12 2009-11-19 Toshiba Corp 半導体記憶装置
JP4954954B2 (ja) * 2008-08-07 2012-06-20 パナソニック株式会社 半導体記憶装置
US7986566B2 (en) * 2009-04-01 2011-07-26 Texas Instruments Incorporated SRAM cell with read buffer controlled for low leakage current
US8144540B2 (en) * 2009-04-14 2012-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Two-port 8T SRAM design
US8208314B2 (en) * 2010-06-01 2012-06-26 Aptina Imaging Corporation Sequential access memory elements
US8654575B2 (en) 2010-07-16 2014-02-18 Texas Instruments Incorporated Disturb-free static random access memory cell
KR101914798B1 (ko) * 2010-07-20 2018-11-02 유니버시티 오브 버지니아 페이턴트 파운데이션 메모리 셀
WO2012119988A1 (en) * 2011-03-04 2012-09-13 Imec Local write and read assist circuitry for memory device
US8531873B2 (en) * 2011-05-08 2013-09-10 Ben-Gurion University Of The Negev Research And Development Authority Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation
JP2013206512A (ja) * 2012-03-29 2013-10-07 Kyushu Institute Of Technology 半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050180224A1 (en) 2004-02-13 2005-08-18 Nestor Tzartzanis Differential current-mode sensing methods and apparatuses for memories
US7400523B2 (en) 2006-06-01 2008-07-15 Texas Instruments Incorporated 8T SRAM cell with higher voltage on the read WL
US20100182823A1 (en) 2009-01-22 2010-07-22 Qualcomm Incorporated Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors
US20110305099A1 (en) 2010-05-12 2011-12-15 Stichting Imec Nederland Hierarchical buffered segmented bit-lines based sram

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Benton H. Calhoun et al.,'A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation', IEEE JSSC, Vol. 42, No. 3, March 2007.

Also Published As

Publication number Publication date
US9460777B2 (en) 2016-10-04
JP2016527654A (ja) 2016-09-08
EP3028281A1 (en) 2016-06-08
JP6096991B2 (ja) 2017-03-15
WO2015017164A1 (en) 2015-02-05
CN105637589B (zh) 2018-11-02
US20150036417A1 (en) 2015-02-05
EP3028281B1 (en) 2017-12-20
KR20160037202A (ko) 2016-04-05
CN105637589A (zh) 2016-06-01

Similar Documents

Publication Publication Date Title
KR101779553B1 (ko) 감소된 감지 지연 및 개선된 감지 마진을 갖는 sram 판독 버퍼
US7902878B2 (en) Clock gating system and method
US8279659B2 (en) System and method of operating a memory device
US8446753B2 (en) Reference cell write operations at a memory
US9336863B2 (en) Dual write wordline memory cell
KR101293528B1 (ko) 듀얼-기술 트랜지스터들을 사용한 저누설 고성능 정적 랜덤 액세스 메모리 셀
KR101425121B1 (ko) 자기 터널 접합에 인가될 전류의 방향을 제어하기 위한 시스템 및 방법
CN102016749B (zh) 时钟门控系统和方法
KR20140012213A (ko) 저항성 메모리 엘리먼트를 포함하는 멀티-포트 비휘발성 메모리
KR20130042589A (ko) 래칭 회로
US8599597B2 (en) Circuits configured to remain in a non-program state during a power-down event
CN103544986A (zh) 基于电荷再利用和位线分级的低功耗8管sram芯片设计方法
US8760953B2 (en) Sense amplifier with selectively powered inverter
KR20130018327A (ko) 로컬 전류 싱크를 갖는 메모리 디바이스

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20160224

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
A302 Request for accelerated examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20161206

Comment text: Request for Examination of Application

PA0302 Request for accelerated examination

Patent event date: 20161206

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20170113

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20170615

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20170912

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20170913

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20200624

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20220622

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20230626

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20240624

Start annual number: 8

End annual number: 8