KR101701360B1 - 격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 - Google Patents
격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 Download PDFInfo
- Publication number
- KR101701360B1 KR101701360B1 KR1020117006475A KR20117006475A KR101701360B1 KR 101701360 B1 KR101701360 B1 KR 101701360B1 KR 1020117006475 A KR1020117006475 A KR 1020117006475A KR 20117006475 A KR20117006475 A KR 20117006475A KR 101701360 B1 KR101701360 B1 KR 101701360B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- liner
- gate
- trench
- overlying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/199,616 US7998832B2 (en) | 2008-08-27 | 2008-08-27 | Semiconductor device with isolation trench liner, and related fabrication methods |
| US12/199,616 | 2008-08-27 | ||
| PCT/US2009/053271 WO2010025024A1 (en) | 2008-08-27 | 2009-08-10 | Semiconductor device with isolation trench liner, and related fabrication methods |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020177002051A Division KR101810111B1 (ko) | 2008-08-27 | 2009-08-10 | 격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20110102868A KR20110102868A (ko) | 2011-09-19 |
| KR101701360B1 true KR101701360B1 (ko) | 2017-02-01 |
Family
ID=41202835
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020177002051A Active KR101810111B1 (ko) | 2008-08-27 | 2009-08-10 | 격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 |
| KR1020117006475A Active KR101701360B1 (ko) | 2008-08-27 | 2009-08-10 | 격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020177002051A Active KR101810111B1 (ko) | 2008-08-27 | 2009-08-10 | 격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US7998832B2 (enExample) |
| EP (1) | EP2324496B1 (enExample) |
| JP (1) | JP5619003B2 (enExample) |
| KR (2) | KR101810111B1 (enExample) |
| CN (1) | CN102132397B (enExample) |
| WO (1) | WO2010025024A1 (enExample) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101375388B (zh) * | 2006-01-18 | 2011-08-03 | Nxp股份有限公司 | 金属线之间的自对准沟槽的集成 |
| JP2010199156A (ja) * | 2009-02-23 | 2010-09-09 | Panasonic Corp | 半導体装置及びその製造方法 |
| US20110014726A1 (en) * | 2009-07-20 | 2011-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming shallow trench isolation structure |
| US8716095B2 (en) * | 2010-06-03 | 2014-05-06 | Institute of Microelectronics, Chinese Academy of Sciences | Manufacturing method of gate stack and semiconductor device |
| US8680644B2 (en) * | 2011-04-11 | 2014-03-25 | International Business Machines Coroporation | Semiconductor device and method for making same |
| US8530312B2 (en) | 2011-08-08 | 2013-09-10 | Micron Technology, Inc. | Vertical devices and methods of forming |
| FR2981793A1 (fr) * | 2011-10-25 | 2013-04-26 | St Microelectronics Crolles 2 | Procede de fabrication de transistors a grille isolee |
| US8564074B2 (en) * | 2011-11-29 | 2013-10-22 | International Business Machines Corporation | Self-limiting oxygen seal for high-K dielectric and design structure |
| US9536993B2 (en) * | 2012-03-23 | 2017-01-03 | Japan Science And Technology Agency | Thin film transistor and method for manufacturing thin film transistor |
| US20130341762A1 (en) * | 2012-06-20 | 2013-12-26 | Macronix International Co., Ltd. | Semiconductor hole structure |
| US8673738B2 (en) | 2012-06-25 | 2014-03-18 | International Business Machines Corporation | Shallow trench isolation structures |
| JP6033594B2 (ja) * | 2012-07-18 | 2016-11-30 | 国立大学法人北陸先端科学技術大学院大学 | 薄膜トランジスタ及び薄膜トランジスタの製造方法 |
| KR20140059107A (ko) * | 2012-11-07 | 2014-05-15 | 주식회사 유피케미칼 | 실리콘 질화물 박막 제조 방법 |
| US8900952B2 (en) | 2013-03-11 | 2014-12-02 | International Business Machines Corporation | Gate stack including a high-k gate dielectric that is optimized for low voltage applications |
| US20140315371A1 (en) * | 2013-04-17 | 2014-10-23 | International Business Machines Corporation | Methods of forming isolation regions for bulk finfet semiconductor devices |
| US9679917B2 (en) | 2014-12-23 | 2017-06-13 | International Business Machines Corporation | Semiconductor structures with deep trench capacitor and methods of manufacture |
| US9991124B2 (en) * | 2015-01-20 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal gate and manufacturing method thereof |
| KR102271239B1 (ko) | 2015-03-23 | 2021-06-29 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
| US9865703B2 (en) | 2015-12-31 | 2018-01-09 | International Business Machines Corporation | High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process |
| DE102018107908B4 (de) * | 2017-07-28 | 2023-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verfahren zum Bilden eines integrierten Schaltkreises mit einer Versiegelungsschicht zum Bilden einer Speicherzellenstruktur in Logik- oder BCD-Technologie sowie ein integrierter Schaltkreis mit einer Dummy-Struktur an einer Grenze einer Vorrichtungsregion |
| US10504912B2 (en) * | 2017-07-28 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology |
| CN110707086B (zh) * | 2018-10-09 | 2022-02-18 | 联华电子股份有限公司 | 半导体元件 |
| TW202209688A (zh) * | 2020-06-05 | 2022-03-01 | 日商Flosfia股份有限公司 | 半導體裝置 |
| KR20220085482A (ko) | 2020-12-15 | 2022-06-22 | 삼성전자주식회사 | 반도체 소자 |
| CN117156850A (zh) * | 2022-05-18 | 2023-12-01 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004134757A (ja) | 2002-08-22 | 2004-04-30 | Chartered Semiconductor Mfg Ltd | ダマシンゲート構造物を分離領域に対して自己整合する方法 |
| US7071515B2 (en) * | 2003-07-14 | 2006-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
| US20070032039A1 (en) | 2005-08-03 | 2007-02-08 | Ming-Te Chen | Sti process for eliminating silicon nitride liner induced defects |
| KR100764742B1 (ko) * | 2006-06-16 | 2007-10-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286736B1 (ko) * | 1998-06-16 | 2001-04-16 | 윤종용 | 트렌치 격리 형성 방법 |
| US6306741B1 (en) * | 2000-07-13 | 2001-10-23 | Chartered Semiconductor Manufacturing, Inc. | Method of patterning gate electrodes with high K gate dielectrics |
| KR100421046B1 (ko) | 2001-07-13 | 2004-03-04 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
| US6828211B2 (en) | 2002-10-01 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control |
| DE20308406U1 (de) * | 2003-05-28 | 2003-08-07 | Dekema Dental-Keramiköfen GmbH, 83395 Freilassing | Ofen für Zahnersatz oder -teilersatz |
| US6940705B2 (en) * | 2003-07-25 | 2005-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor with enhanced performance and method of manufacture |
| US6936881B2 (en) * | 2003-07-25 | 2005-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor that includes high permittivity capacitor dielectric |
| JP3802530B2 (ja) * | 2003-12-12 | 2006-07-26 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7015113B2 (en) * | 2004-04-01 | 2006-03-21 | Micron Technology, Inc. | Methods of forming trench isolation regions |
| KR100672754B1 (ko) * | 2004-05-10 | 2007-01-22 | 주식회사 하이닉스반도체 | 트렌치형 소자분리막을 구비한 반도체 소자의 제조 방법 |
| US7160819B2 (en) * | 2005-04-25 | 2007-01-09 | Sharp Laboratories Of America, Inc. | Method to perform selective atomic layer deposition of zinc oxide |
| US20070003203A1 (en) * | 2005-06-30 | 2007-01-04 | Palmer Jeffrey D | Methods and apparatus for stripping optical fiber |
| US7586158B2 (en) * | 2005-07-07 | 2009-09-08 | Infineon Technologies Ag | Piezoelectric stress liner for bulk and SOI |
-
2008
- 2008-08-27 US US12/199,616 patent/US7998832B2/en active Active
-
2009
- 2009-08-10 EP EP09791330.5A patent/EP2324496B1/en active Active
- 2009-08-10 CN CN200980134161.7A patent/CN102132397B/zh active Active
- 2009-08-10 KR KR1020177002051A patent/KR101810111B1/ko active Active
- 2009-08-10 JP JP2011525070A patent/JP5619003B2/ja active Active
- 2009-08-10 KR KR1020117006475A patent/KR101701360B1/ko active Active
- 2009-08-10 WO PCT/US2009/053271 patent/WO2010025024A1/en not_active Ceased
-
2011
- 2011-07-07 US US13/178,362 patent/US8217472B2/en active Active
-
2012
- 2012-05-16 US US13/473,175 patent/US8716828B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004134757A (ja) | 2002-08-22 | 2004-04-30 | Chartered Semiconductor Mfg Ltd | ダマシンゲート構造物を分離領域に対して自己整合する方法 |
| US7071515B2 (en) * | 2003-07-14 | 2006-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
| US20070032039A1 (en) | 2005-08-03 | 2007-02-08 | Ming-Te Chen | Sti process for eliminating silicon nitride liner induced defects |
| KR100764742B1 (ko) * | 2006-06-16 | 2007-10-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010025024A1 (en) | 2010-03-04 |
| KR20110102868A (ko) | 2011-09-19 |
| US20100052094A1 (en) | 2010-03-04 |
| US20120223399A1 (en) | 2012-09-06 |
| JP2012501542A (ja) | 2012-01-19 |
| JP5619003B2 (ja) | 2014-11-05 |
| KR20170013403A (ko) | 2017-02-06 |
| US8716828B2 (en) | 2014-05-06 |
| EP2324496A1 (en) | 2011-05-25 |
| US7998832B2 (en) | 2011-08-16 |
| KR101810111B1 (ko) | 2017-12-18 |
| CN102132397A (zh) | 2011-07-20 |
| EP2324496B1 (en) | 2018-10-10 |
| US8217472B2 (en) | 2012-07-10 |
| US20110260263A1 (en) | 2011-10-27 |
| CN102132397B (zh) | 2016-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101701360B1 (ko) | 격리 트렌치 라이너를 가지는 반도체 장치 및 관련된 제조 방법 | |
| US9548356B2 (en) | Shallow trench isolation structures | |
| US8361879B2 (en) | Stress-inducing structures, methods, and materials | |
| JP3634320B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
| US7906381B2 (en) | Method for integrating silicon-on-nothing devices with standard CMOS devices | |
| US8877606B2 (en) | Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation | |
| US20100237432A1 (en) | Semiconductor device and method for fabricating the same | |
| US20070187774A1 (en) | Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure | |
| JP2004221556A (ja) | Cmosトランジスタを製作するためのゲート・パターン形成用の3層ハードマスク | |
| KR20060129037A (ko) | 반도체 제조 동안 sti 디봇 형성 감소 방법 | |
| US6501135B1 (en) | Germanium-on-insulator (GOI) device | |
| US6433400B1 (en) | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | |
| US20120235245A1 (en) | Superior integrity of high-k metal gate stacks by reducing sti divots by depositing a fill material after sti formation | |
| US9911820B2 (en) | Method for fabrication of a field-effect with reduced stray capacitance | |
| JP2009099815A (ja) | 半導体装置の製造方法 | |
| JP2001203350A (ja) | 半導体装置及び半導体装置の製造方法 | |
| KR20020002783A (ko) | 반도체소자의 소자분리방법 | |
| CN102420163A (zh) | 一种隔离结构及制造方法、以及具有该结构的半导体器件 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20110321 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20140723 Comment text: Request for Examination of Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20150807 Patent event code: PE09021S01D |
|
| AMND | Amendment | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20160325 Patent event code: PE09021S01D |
|
| AMND | Amendment | ||
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20160818 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20160325 Comment text: Notification of reason for refusal Patent event code: PE06011S01I Patent event date: 20150807 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |
|
| AMND | Amendment | ||
| PX0901 | Re-examination |
Patent event code: PX09011S01I Patent event date: 20160818 Comment text: Decision to Refuse Application Patent event code: PX09012R01I Patent event date: 20160525 Comment text: Amendment to Specification, etc. Patent event code: PX09012R01I Patent event date: 20151106 Comment text: Amendment to Specification, etc. |
|
| PX0701 | Decision of registration after re-examination |
Patent event date: 20161102 Comment text: Decision to Grant Registration Patent event code: PX07013S01D Patent event date: 20161031 Comment text: Amendment to Specification, etc. Patent event code: PX07012R01I Patent event date: 20160818 Comment text: Decision to Refuse Application Patent event code: PX07011S01I Patent event date: 20160525 Comment text: Amendment to Specification, etc. Patent event code: PX07012R01I Patent event date: 20151106 Comment text: Amendment to Specification, etc. Patent event code: PX07012R01I |
|
| X701 | Decision to grant (after re-examination) | ||
| A107 | Divisional application of patent | ||
| PA0104 | Divisional application for international application |
Comment text: Divisional Application for International Patent Patent event code: PA01041R01D Patent event date: 20170123 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20170124 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20170125 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20191129 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20210114 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20220113 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20221227 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20241219 Start annual number: 9 End annual number: 9 |