KR101596454B1 - Ｓｏｉ 기판의 제작 방법 - Google Patents

Ｓｏｉ 기판의 제작 방법 Download PDF

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Publication number
KR101596454B1
KR101596454B1 KR1020090008279A KR20090008279A KR101596454B1 KR 101596454 B1 KR101596454 B1 KR 101596454B1 KR 1020090008279 A KR1020090008279 A KR 1020090008279A KR 20090008279 A KR20090008279 A KR 20090008279A KR 101596454 B1 KR101596454 B1 KR 101596454B1
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South Korea
Prior art keywords
single crystal
semiconductor substrate
insulating film
crystal semiconductor
halogen
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Expired - Fee Related
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KR1020090008279A
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English (en)
Korean (ko)
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KR20090085533A (ko
Inventor
히데토 오누마
순페이 야마자키
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
KR1020090008279A 2008-02-04 2009-02-03 Ｓｏｉ 기판의 제작 방법 Expired - Fee Related KR101596454B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008024608 2008-02-04
JPJP-P-2008-024608 2008-02-04

Publications (2)

Publication Number Publication Date
KR20090085533A KR20090085533A (ko) 2009-08-07
KR101596454B1 true KR101596454B1 (ko) 2016-02-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090008279A Expired - Fee Related KR101596454B1 (ko) 2008-02-04 2009-02-03 Ｓｏｉ 기판의 제작 방법

Country Status (3)

Country Link
US (1) US7858495B2 (https=)
JP (1) JP2009212503A (https=)
KR (1) KR101596454B1 (https=)

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JP2009141093A (ja) 2007-12-06 2009-06-25 Toshiba Corp 発光素子及び発光素子の製造方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US20110147817A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Austria Ag Semiconductor component having an oxide layer
SG173283A1 (en) * 2010-01-26 2011-08-29 Semiconductor Energy Lab Method for manufacturing soi substrate
WO2011132529A1 (en) * 2010-04-23 2011-10-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
EP2615645A1 (en) * 2012-01-10 2013-07-17 Innovation & Infinity Global Corp. Composite poly-silicon substrate and solar cell having the same
KR102031174B1 (ko) * 2012-11-16 2019-10-11 삼성전자주식회사 반도체 소자, 반도체 소자의 제조 방법 및 기판 가공 장치
US9589853B2 (en) 2014-02-28 2017-03-07 Lam Research Corporation Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber
CN106252458B (zh) * 2015-06-10 2017-12-12 Lg电子株式会社 制造太阳能电池的方法
US9960275B1 (en) * 2016-10-28 2018-05-01 Applied Materials, Inc. Method of fabricating air-gap spacer for N7/N5 finFET and beyond
SG11201913769RA (en) * 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
TWI796599B (zh) * 2019-09-30 2023-03-21 台灣積體電路製造股份有限公司 絕緣層上半導體（soi）基底、形成絕緣層上半導體基底的方法以及積體電路
US11289330B2 (en) 2019-09-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate and method for forming

Citations (2)

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WO2005055293A1 (ja) 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
WO2007006803A1 (fr) 2005-07-13 2007-01-18 S.O.I.Tec Silicon On Insulator Technologies Procede de diminution de la rugosite d'une couche epaisse d'isolant

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JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH09275216A (ja) * 1996-02-09 1997-10-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
US6566233B2 (en) * 1999-12-24 2003-05-20 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
JP4450126B2 (ja) * 2000-01-21 2010-04-14 日新電機株式会社 シリコン系結晶薄膜の形成方法
JPWO2005022610A1 (ja) * 2003-09-01 2007-11-01 株式会社Sumco 貼り合わせウェーハの製造方法
EP1667218B9 (en) * 2003-09-08 2019-11-20 SUMCO Corporation Soi wafer and its manufacturing method
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
FR2884966B1 (fr) * 2005-04-22 2007-08-17 Soitec Silicon On Insulator Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
JP2007194345A (ja) * 2006-01-18 2007-08-02 Canon Inc はり合わせ基板の製造方法、及びはり合わせ基板の製造装置
US7745309B2 (en) * 2006-08-09 2010-06-29 Applied Materials, Inc. Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
EP2140480A4 (en) * 2007-04-20 2015-04-22 Semiconductor Energy Lab METHOD FOR PRODUCING AN SOI SUBSTRATE AND SEMICONDUCTOR ARRANGEMENT
KR101436116B1 (ko) * 2007-04-27 2014-09-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판 및 그 제조 방법, 및 반도체 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005055293A1 (ja) 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
WO2007006803A1 (fr) 2005-07-13 2007-01-18 S.O.I.Tec Silicon On Insulator Technologies Procede de diminution de la rugosite d'une couche epaisse d'isolant

Also Published As

Publication number Publication date
JP2009212503A (ja) 2009-09-17
KR20090085533A (ko) 2009-08-07
US20090197391A1 (en) 2009-08-06
US7858495B2 (en) 2010-12-28

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