KR101297015B1 - 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지 - Google Patents

리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지 Download PDF

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KR101297015B1
KR101297015B1 KR1020110113649A KR20110113649A KR101297015B1 KR 101297015 B1 KR101297015 B1 KR 101297015B1 KR 1020110113649 A KR1020110113649 A KR 1020110113649A KR 20110113649 A KR20110113649 A KR 20110113649A KR 101297015 B1 KR101297015 B1 KR 101297015B1
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South Korea
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lead frame
package
semiconductor chip
lead
semiconductor package
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KR1020110113649A
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English (en)
Korean (ko)
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KR20130048810A (ko
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세이 헤안 소흐
유엔 지엔 시에우
권용태
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주식회사 네패스
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Priority to KR1020110113649A priority Critical patent/KR101297015B1/ko
Priority to PCT/KR2011/009049 priority patent/WO2013065895A1/fr
Publication of KR20130048810A publication Critical patent/KR20130048810A/ko
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Publication of KR101297015B1 publication Critical patent/KR101297015B1/ko

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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
KR1020110113649A 2011-11-03 2011-11-03 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지 KR101297015B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020110113649A KR101297015B1 (ko) 2011-11-03 2011-11-03 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
PCT/KR2011/009049 WO2013065895A1 (fr) 2011-11-03 2011-11-25 Procédé de fabrication d'un boîtier semi-conducteur de sortie à l'aide d'une grille de connexion et boîtier de semi-conducteur et boîtier sur boîtier pour ce dernier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110113649A KR101297015B1 (ko) 2011-11-03 2011-11-03 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지

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KR20130048810A KR20130048810A (ko) 2013-05-13
KR101297015B1 true KR101297015B1 (ko) 2013-08-14

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