KR101164690B1 - 유기 ａｒｃ를 구비하는 반도체 장치 및 그것을 위한 방법 - Google Patents

유기 ａｒｃ를 구비하는 반도체 장치 및 그것을 위한 방법 Download PDF

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KR101164690B1
KR101164690B1 KR1020067001728A KR20067001728A KR101164690B1 KR 101164690 B1 KR101164690 B1 KR 101164690B1 KR 1020067001728 A KR1020067001728 A KR 1020067001728A KR 20067001728 A KR20067001728 A KR 20067001728A KR 101164690 B1 KR101164690 B1 KR 101164690B1
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South Korea
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layer
semiconductor device
teos
organic arc
organic
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Korean (ko)
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KR20060056346A (ko
Inventor
더글라스 엠. 레베르
마크 디. 홀
커트 에이치. 정커
카일 더블유. 패터슨
탭 앨런 스티븐스
에드워드 케이. 테이스
스리칸테스와라 다크시나-무르티
마릴린 아이린 라이트
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프리스케일 세미컨덕터, 인크.
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/952—Utilizing antireflective layer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020067001728A 2003-07-28 2004-07-13 유기 ａｒｃ를 구비하는 반도체 장치 및 그것을 위한 방법 Expired - Lifetime KR101164690B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/628,668 US6972255B2 (en) 2003-07-28 2003-07-28 Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
US10/628,668 2003-07-28
PCT/US2004/022434 WO2005013320A2 (en) 2003-07-28 2004-07-13 A semiconductor device having an organic anti-reflective coating (arc) and method therefor

Publications (2)

Publication Number Publication Date
KR20060056346A KR20060056346A (ko) 2006-05-24
KR101164690B1 true KR101164690B1 (ko) 2012-07-11

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KR1020067001728A Expired - Lifetime KR101164690B1 (ko) 2003-07-28 2004-07-13 유기 ａｒｃ를 구비하는 반도체 장치 및 그것을 위한 방법

Country Status (7)

Country Link
US (3) US6972255B2 (https=)
EP (1) EP1652225A4 (https=)
JP (1) JP4677407B2 (https=)
KR (1) KR101164690B1 (https=)
CN (1) CN100461350C (https=)
TW (1) TWI348777B (https=)
WO (1) WO2005013320A2 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6972255B2 (en) * 2003-07-28 2005-12-06 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
DE10339988B4 (de) * 2003-08-29 2008-06-12 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer antireflektierenden Schicht
US20060105567A1 (en) * 2004-11-12 2006-05-18 Intel Corporation Method for forming a dual-damascene structure
US7176130B2 (en) * 2004-11-12 2007-02-13 Freescale Semiconductor, Inc. Plasma treatment for surface of semiconductor device
US20070000360A1 (en) * 2005-07-01 2007-01-04 Colarelli Nicholas J Iii Tool for an automobile brake lathe
US7829159B2 (en) * 2005-12-16 2010-11-09 Asm Japan K.K. Method of forming organosilicon oxide film and multilayer resist structure
US7371695B2 (en) * 2006-01-04 2008-05-13 Promos Technologies Pte. Ltd. Use of TEOS oxides in integrated circuit fabrication processes
JP2007311508A (ja) * 2006-05-17 2007-11-29 Nikon Corp 微細パターン形成方法及びデバイス製造方法
JP2008091825A (ja) * 2006-10-05 2008-04-17 Nec Electronics Corp 半導体装置の製造方法
US7737018B2 (en) * 2007-02-06 2010-06-15 Freescale Semiconductor, Inc. Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer
US7727829B2 (en) * 2007-02-06 2010-06-01 Freescale Semiconductor, Inc. Method of forming a semiconductor device having a removable sidewall spacer
US20090104541A1 (en) * 2007-10-23 2009-04-23 Eui Kyoon Kim Plasma surface treatment to prevent pattern collapse in immersion lithography
KR100983724B1 (ko) * 2007-12-20 2010-09-24 주식회사 하이닉스반도체 반도체 소자의 형성 방법
US20090197086A1 (en) * 2008-02-04 2009-08-06 Sudha Rathi Elimination of photoresist material collapse and poisoning in 45-nm feature size using dry or immersion lithography
CN102087993B (zh) * 2009-12-04 2013-01-23 中芯国际集成电路制造(上海)有限公司 沟槽形成方法
CN102867742B (zh) * 2012-09-17 2015-06-24 上海华力微电子有限公司 一种消除形貌变形的等离子刻蚀方法
US9640430B2 (en) 2015-09-17 2017-05-02 Nxp Usa, Inc. Semiconductor device with graphene encapsulated metal and method therefor
US10297445B2 (en) 2016-06-14 2019-05-21 QROMIS, Inc. Engineered substrate structure for power and RF applications
US10510582B2 (en) 2016-06-14 2019-12-17 QROMIS, Inc. Engineered substrate structure
WO2017218536A1 (en) * 2016-06-14 2017-12-21 Quora Technology, Inc. Engineered substrate structure for power and rf applications
CN110660839B (zh) * 2019-11-13 2022-04-29 京东方科技集团股份有限公司 一种显示面板及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002301697A (ja) * 2000-11-27 2002-10-15 Microscan Systems Inc 単結晶シリコンの露光の工程を備える、マイクロメカニカルおよびマイクロオプトメカニカルな構造物を製造するための方法
KR100381885B1 (ko) * 2000-04-27 2003-04-26 엔이씨 일렉트로닉스 코포레이션 미세 게이트 전극을 구비한 반도체 장치의 제조 방법

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153691A (en) * 1989-06-21 1992-10-06 Xicor, Inc. Apparatus for a dual thickness floating gate memory cell
US5976992A (en) 1993-09-27 1999-11-02 Kabushiki Kaisha Toshiba Method of supplying excited oxygen
US5545588A (en) * 1995-05-05 1996-08-13 Taiwan Semiconductor Manufacturing Company Method of using disposable hard mask for gate critical dimension control
US5635425A (en) 1995-05-25 1997-06-03 Industrial Technology Research Institute In-situ N2 plasma treatment for PE TEOS oxide deposition
US5536681A (en) 1995-06-23 1996-07-16 Taiwan Semiconductor Manufacturing Company PE-OX/ozone-TEOS gap filling capability by selective N2 treatment on PE-OX
US5759746A (en) * 1996-05-24 1998-06-02 Kabushiki Kaisha Toshiba Fabrication process using a thin resist
US5880018A (en) 1996-10-07 1999-03-09 Motorola Inc. Method for manufacturing a low dielectric constant inter-level integrated circuit structure
CN1107342C (zh) 1997-01-21 2003-04-30 松下电器产业株式会社 图案形成方法
US5807660A (en) 1997-02-03 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Avoid photoresist lifting by post-oxide-dep plasma treatment
US6417167B1 (en) * 1997-02-05 2002-07-09 Kirin Beer Kabushiki Kaisha Lyophilized compositions containing shingoglycolipid and process for preparing them
US6428894B1 (en) 1997-06-04 2002-08-06 International Business Machines Corporation Tunable and removable plasma deposited antireflective coatings
US6211078B1 (en) * 1997-08-18 2001-04-03 Micron Technology, Inc. Method of improving resist adhesion for use in patterning conductive layers
US6133613A (en) * 1998-02-03 2000-10-17 Vanguard International Semiconductor Corporation Anti-reflection oxynitride film for tungsten-silicide substrates
WO1999050894A1 (en) * 1998-03-27 1999-10-07 Advanced Micro Devices, Inc. Thin oxide film for augmenting anti-reflectivity and eliminating resist footing
US6143666A (en) 1998-03-30 2000-11-07 Vanguard International Seminconductor Company Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
US6316167B1 (en) 2000-01-10 2001-11-13 International Business Machines Corporation Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof
US6093973A (en) * 1998-09-30 2000-07-25 Advanced Micro Devices, Inc. Hard mask for metal patterning
US6187687B1 (en) * 1998-11-05 2001-02-13 Advanced Micro Devices, Inc. Minimization of line width variation in photolithography
WO2000031782A1 (en) 1998-11-25 2000-06-02 Advanced Micro Devices, Inc. Silane-based oxide anti-reflective coating for patterning of metal features in semiconductor manufacturing
US6159863A (en) * 1999-01-22 2000-12-12 Advanced Micro Devices, Inc. Insitu hardmask and metal etch in a single etcher
US6423385B1 (en) 1999-02-25 2002-07-23 Hitachi, Ltd. Liquid crystal display devices
US6503818B1 (en) 1999-04-02 2003-01-07 Taiwan Semiconductor Manufacturing Company Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material
KR100307629B1 (ko) * 1999-04-30 2001-09-26 윤종용 하이드로 카본계의 가스를 이용한 반사방지막의 형성 및 적용방법
US6423384B1 (en) 1999-06-25 2002-07-23 Applied Materials, Inc. HDP-CVD deposition of low dielectric constant amorphous carbon film
US6306771B1 (en) 1999-08-27 2001-10-23 Integrated Device Technology, Inc. Process for preventing the formation of ring defects
US6197687B1 (en) * 1999-09-13 2001-03-06 Advanced Micro Devices, Inc. Method of patterning field dielectric regions in a semiconductor device
JP2001085407A (ja) * 1999-09-13 2001-03-30 Hitachi Ltd 半導体集積回路装置の製造方法および製造装置
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
JP5121090B2 (ja) * 2000-02-17 2013-01-16 アプライド マテリアルズ インコーポレイテッド アモルファスカーボン層の堆積方法
US6420097B1 (en) * 2000-05-02 2002-07-16 Advanced Micro Devices, Inc. Hardmask trim process
JP2002194547A (ja) * 2000-06-08 2002-07-10 Applied Materials Inc アモルファスカーボン層の堆積方法
US6417084B1 (en) 2000-07-20 2002-07-09 Advanced Micro Devices, Inc. T-gate formation using a modified conventional poly process
KR100504546B1 (ko) 2000-07-24 2005-08-01 주식회사 하이닉스반도체 반도체 소자의 제조방법
US6656830B1 (en) 2001-02-07 2003-12-02 Advanced Micro Devices, Inc. Dual damascene with silicon carbide middle etch stop layer/ARC
US6423364B1 (en) * 2001-02-28 2002-07-23 Protein Technologies International, Inc. Functional food ingredient
US6716571B2 (en) 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
JP4014891B2 (ja) * 2001-03-29 2007-11-28 株式会社東芝 半導体装置の製造方法
TW567575B (en) 2001-03-29 2003-12-21 Toshiba Corp Fabrication method of semiconductor device and semiconductor device
JP2003077900A (ja) * 2001-09-06 2003-03-14 Hitachi Ltd 半導体装置の製造方法
JP3877997B2 (ja) * 2001-11-05 2007-02-07 プロモス テクノロジーズ インコーポレイテッド ダイナミックランダムアクセスメモリセルを形成する方法
US6548423B1 (en) 2002-01-16 2003-04-15 Advanced Micro Devices, Inc. Multilayer anti-reflective coating process for integrated circuit fabrication
US6541397B1 (en) * 2002-03-29 2003-04-01 Applied Materials, Inc. Removable amorphous carbon CMP stop
US6764949B2 (en) 2002-07-31 2004-07-20 Advanced Micro Devices, Inc. Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
US6900002B1 (en) * 2002-11-19 2005-05-31 Advanced Micro Devices, Inc. Antireflective bi-layer hardmask including a densified amorphous carbon layer
US6894342B1 (en) 2003-06-12 2005-05-17 Spansion Llc Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control
US6972255B2 (en) 2003-07-28 2005-12-06 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381885B1 (ko) * 2000-04-27 2003-04-26 엔이씨 일렉트로닉스 코포레이션 미세 게이트 전극을 구비한 반도체 장치의 제조 방법
JP2002301697A (ja) * 2000-11-27 2002-10-15 Microscan Systems Inc 単結晶シリコンの露光の工程を備える、マイクロメカニカルおよびマイクロオプトメカニカルな構造物を製造するための方法

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JP2007500443A (ja) 2007-01-11
EP1652225A2 (en) 2006-05-03
KR20060056346A (ko) 2006-05-24
US20050026338A1 (en) 2005-02-03
WO2005013320A2 (en) 2005-02-10
US8039389B2 (en) 2011-10-18
JP4677407B2 (ja) 2011-04-27
US20070141770A1 (en) 2007-06-21
US6972255B2 (en) 2005-12-06
TWI348777B (en) 2011-09-11
CN100461350C (zh) 2009-02-11
TW200520274A (en) 2005-06-16
EP1652225A4 (en) 2009-05-13
US20050181596A1 (en) 2005-08-18
US7199429B2 (en) 2007-04-03
WO2005013320A3 (en) 2005-04-07
CN1809916A (zh) 2006-07-26

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