CN1809916A - 具有有机抗反射涂层(arc)的半导体器件及其制造方法 - Google Patents

具有有机抗反射涂层(arc)的半导体器件及其制造方法 Download PDF

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CN1809916A
CN1809916A CNA2004800173895A CN200480017389A CN1809916A CN 1809916 A CN1809916 A CN 1809916A CN A2004800173895 A CNA2004800173895 A CN A2004800173895A CN 200480017389 A CN200480017389 A CN 200480017389A CN 1809916 A CN1809916 A CN 1809916A
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arc
composition
resist
teos
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CN100461350C (zh
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道格拉斯·M.·雷博
马克·D.·霍尔
库尔特·H.·琼克
凯勒·W.·帕特森
塔布·阿伦·斯蒂芬斯
爱德华·K.·泰斯
戴克什纳-墨西·斯瑞卡特斯瓦拉
马里琳·艾琳·赖特
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NXP USA Inc
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Abstract

在制造半导体器件过程中，要被刻蚀的位于导体层(16)上的构图叠层具有用于构图其下面的四乙基原硅酸盐(TEOS)层(20)的构图抗蚀剂层(22)。在较传统温度低的温度下沉积所述TEOS层(20)。低温TEOS层(20)位于导体层(16)上面的有机抗反射涂层(ARC)(18)之上。低温TEOS层(20)提供有机ARC层(18)和抗蚀剂层(22)之间的粘结，具有低缺陷，作为硬模操作，并且用作(与有机ARC(18)结合)有助于降低不希望的发射的相移层。

Description

具有有机抗反射涂层(ARC) 的半导体器件及其制造方法
技术领域
本发明涉及半导体器件，尤其是使用有机抗反射层(ARC)的半导体器件。
背景技术
在半导体制造领域具有多层，它们需要用于薄膜堆叠刻蚀的构图的保护层。用于这种构图刻蚀的两种已知的技术是无机抗反射涂层(ARC)硬模和旋压有机底抗反射涂层(BARC)。无机ARC硬模构图方案对于一些应用存在困难，因为在硬模刻蚀中需要保护硬模的抗蚀剂数量设定了对抗蚀剂厚度的限制。这种限制可以阻止使用提供更高分辨率的更薄的抗蚀剂膜的使用。尽管旋压BARC相对更容易使用，通常在化学成分方面它如此类似于抗蚀剂和由此产生的刻蚀性能以致于它也需要更厚的抗蚀剂。为了避开这些问题，使用无定形碳薄膜的方案已经被提出。在半导体制造领域已经尝试这种膜，却发现具有相对较高的缺陷密度，每平方厘米的缺陷大于3.0。
这样需要一种具有高分辨率和低缺陷的改进的掩模叠层。
附图说明
借助于实例描述了本发明，以及本发明不受到附图的限制，其中相同的标号表示相同的元件，附图中：
图1是根据本发明的一个实施例的半导体器件的横截面；
图2是图1的半导体器件在随后的制造阶段中的横截面；
图3是图2的半导体器件在随后的制造阶段中的横截面；
图4是图3的半导体器件在随后的制造阶段中的横截面；
图5是图4的半导体器件在随后的制造阶段中的横截面；
图6是图5的半导体器件在随后的制造阶段中的横截面；和
图7是图6的半导体器件在随后的制造阶段中的横截面；
本领域的技术人员理解，附图中元件的图示是为了简洁而清晰并且未必按比例绘制。例如，图中一些元件的尺寸可以相对于其它元件夸大以有利于增加对本发明实施例的理解。
具体实施方式
一方面，位于将要被刻蚀的导电材料上面的图案叠层具有构图的抗蚀剂层，该抗蚀剂层用于使下面的四乙基原硅酸盐(TEOS)层形成图案。在相比传统工艺更低的温度下沉积TEOS层。低温TEOS层位于有机抗反射层(ARC)上面，ARC层位于导体层上面。低温TEOS层为有机ARC层和抗蚀剂层提供了粘结，具有低缺陷，作为硬模，且用作相移层，此相移层与有机ARC层结合有助于降低不希望的反射。随着为193nm光刻术设计的抗蚀剂的引入使得粘结的问题变得越来越困难。下面的描述提供了对本发明的优选实施例连同其它替代解决方案更完善的解释。
图1显示了半导体器件10，它包括半导体衬底12、位于衬底12上的绝缘层14、位于绝缘层16上的导电材料层16、位于导电材料层16上的有机ARC层18、位于有机ARC层18上的TEOS层20和构图的抗蚀剂层22。在此例中使构图的抗蚀剂层22形成图案是为了定位MOS晶体管的栅。TEOS层20是氧化物层，优选地在300℃使用TEOS制造。利用Applied Materials Centura 5200DxZ沉积工具并使用TEOS、氧气和氦气在5.5Torr下沉积一有效的TEOS层。
TEOS的流速是840毫克/分(mgm)，氧气的流速为840sccm，和氦气流速为560sccm。功率设定为高频时510瓦和低频时110瓦。此设备和这些设置是示例性的，可以不同于此。有意使温度低于400℃的常规TEOS的沉积温度。温度优选地低于350℃。温度还应当大于250℃。几乎肯定的是其它的设备会在稍微不同的条件下运行和通过试验确定这些参数的设置。在此例中，衬底12为硅，绝缘层14为大约15的氧化硅，导电材料层16为大约1000的多晶硅，有机ARC层为采用本领域技术人员知晓的等离子增强化学气相沉积(PECVD)法沉积的氢化无定形碳膜，厚度为500，构图的抗蚀剂层22的厚度为2500。厚1500的较薄的抗蚀剂层可能是优选的。另一方面，1500厚的多晶硅可能是优选的。而且如果代替多晶硅使用金属，厚度优选地小于1000。
图2示出了为形成减薄的抗蚀剂24横向减薄构图的抗蚀剂层22后的半导体器件10。横向减薄是为了减小图案的宽度。与可获得的光刻设备的曝光技术相比，这是获得更小的几何形状的技术。例如在本例中，通过暴露0.1μm(100nm)实现构图的抗蚀剂层22。减薄后，减薄的抗蚀剂层的宽度为大约50nm，厚度减小到大约1500。此减薄操作最小限度地影响TEOS层20。
图3示出了TEOS层20被刻蚀后的半导体器件10，TEOS层20的刻蚀采用减薄的抗蚀剂层24作为掩模以形成位于减薄的抗蚀剂层28下面的TEOS层26。
图4示出了有机ARC层18被刻蚀后的半导体器件10，有机ARC层的刻蚀采用减薄的抗蚀剂层28和TEOS部分26作为掩模以形成ARC部分30。采用活性离子刻蚀方法刻蚀ARC部分30。此刻蚀为各向异性刻蚀，其在去除ARC层18的暴露部分后变为各向同性。各向同性的效果带来底切所述TEOS部分26之下的ARC层18以留下位于TEOS部分26下的ARC部分30。此技术进一步减小了将由导电材料层16形成的最终层的宽度。此技术为本领域技术人员知晓。
图5示出了导电材料层16被刻蚀后的半导体器件10，导电材料层16的刻蚀采用ARC部分30作为掩模以保留多晶硅的栅导体34和ARC部分36，由于暴露在用于刻蚀导电材料层16的刻蚀剂下，此ARC部分36小于ARC部分30。栅导体34可以是不同于多晶硅的材料，如金属。正被考虑的金属包括氮硅化钽、氮化钛和钨，但不限于此。进一步，金属栅可以是多层的组合物，除一种或多种金属层外，其中一层甚至可以包括多晶硅。
图6示出了为保留位于栅导体34下的栅电介质层38而去除ARC部分36和在图5中所暴露的绝缘层14的部分后的半导体器件10。采用去除抗蚀剂层的传统的工艺实现ARC部分36的去除。尽管没有图5中所示的抗蚀剂层，可以存在一些残存的抗蚀剂和所保留下的刻蚀反应剂，它们通常采用灰化工艺去除。该灰化工艺也对反应去除用于有机ARC层18的材料有效。湿法净化的结合使用，如piranha和SC1的结合使用，也是传统的工艺，该工艺与灰化工艺结合必然除去所有的ARC层18的材料。这样，没有去除ARC部分36所需要的额外的去除步骤。
图7示出了在侧壁40形成和源极42与漏极44的注入后作为完整的晶体管的半导体器件10，栅导体形成在栅电介质上后以传统的方式完成源极42和漏极44的注入。这样，在栅形成后的晶体管的形成中使用低温TEOS不会引起任何部寻常或额外的步骤。
使用低温TEOS是有利的，因为它基本上消除了抗蚀剂毒化，抗蚀剂的毒化使得抗蚀剂在将要去除的区域不能显影。毒化通常来源于抗蚀剂中的氮，其中和了抗蚀剂中的酸。因为TEOS没有氮，因此没有氮毒化抗蚀剂。低温TEOS的另一个好处是抗蚀剂很好地与它粘结。这与传统的400℃的TEOS形成对照，抗蚀剂确实倾向于与传统的400℃TEOS分层，尤其对于为193nm光刻法设计的抗蚀剂。低温TEOS也保持了与下面的有机ARC层的良好的粘结。另一个优点是TEOS(193nm处的n和k)的光学性能，与有机ARC结合，提供了有效的抗反射性能。另一个优点是如果发生不正确的抗蚀剂构图后容易进行光刻重写，在不正确的抗蚀剂构图中抗蚀剂需要被去除和重新施加。在此情况下，TEOS不需要被除去。当去除抗蚀剂时，在抗蚀剂层正下方被刻蚀的薄膜也将不得不被除去和重写。在此情况下TEOS层不必被除去和载施加。进一步，在重写过程中它保护有机ARC层。
上述TEOS方案的替代方案是使用有机硅烷和氧化剂在TEOS层20的位置形成位于ARC18和抗蚀剂层22之间的层。有机硅烷和氧化剂应当是无氮的。至少TEOS是优选的，因为其化学试剂并不昂贵而且工具实用性更好。TEOS也是非常稳定的薄膜。这种稳定性也许难以匹配。为此目的常用的有机硅烷是三甲硅烷。常用的氧化剂或者为纯氧或为二氧化碳。
TEOS方案的另一个替代方案是与富硅氧氮化物(SRON)和富含硅的氧化物(SRO)结合使用氮。一种情况下结合物会是代替TEOS层20的复合物层。氮化硅层会在有机ARC层上，SRON或SRO层会位于抗蚀剂和氮化硅层之间。在提供必需的粘结和低缺陷方面这是有效的。另一种情况下，结合物会被有机ARC分隔。氮化硅层会位于导电材料层16和ARC层18之间。SRON或SRO层会位于ARC层18和抗蚀剂层之间。在提供充分的粘结和缺陷方面这是有效的。结合氮化硅使用SRO或SRON的这两种替代方案相比TEOS的方案都更为复杂并且提供了更难与优选的工艺结合为一体。
在前述的说明中，参照特定实施例对本发明进行描述。但是，本领域技术人员理解，在不脱离下面的权利要求书所阐明的本发明的保护范围的情况下可以进行各种修正和改变。例如，有机ARC可以不必是无定形形态。因此，说明和附图应该被视为示例性的而非限定性的，和所有的这些改动都包含在本发明的保护范围内。
参照特定的实施例本发明的好处、其它的优点和问题的解决方案都已在上面进行了描述。但是，益处、优点、解决方案和可能引起任何益处、优点、解决问题的方案存在或变得显著的任何因素不应被解释为任一或所有权利要求的重要的、所需的、或基本的技术特征或元素。如这里所用，术语“包括”、“包含”或任何其它的其变体意欲覆盖非穷举的包含，这样包含一列元素的工艺、方法、物品或装置不仅包含这些元素，也可以包含未特别列出的或这些工艺、方法、物品或装置固有的其它的元素。

Claims (27)

1、一种用于形成半导体器件的方法，包括：
提供半导体衬底；
在所述半导体衬底上形成绝缘层；
在所述绝缘层上形成导体层；
在所述导体层上形成有机抗反射涂层(ARC)；
在所述有机抗反射涂层上沉积四乙基原硅酸盐(TEOS)层；
在所述TEOS层上沉积抗蚀剂层；和
构图所述抗蚀剂层以形成构图的抗蚀剂结构。
2、如权利要求1的方法，其特征在于所述有机ARC层包括无定形碳。
3、如权利要求1的方法，其特征在于沉积所述有机ARC层使其厚度在大约300到700之间。
4、如权利要求1的方法，其特征在于在大约250℃到350℃的范围内使所述TEOS层形成在有机ARC层上。
5、如权利要求1的方法，其特征在于在大约350℃或更低的温度使所述TEOS层形成在有机ARC层上。
6、如权利要求1的方法，其特征在于所述TEOS层具有大约200到大约300之间的厚度。
7、如权利要求1的方法，进一步包括横向修整构图的抗蚀剂结构以降低构图的抗蚀剂结构的横向尺寸。
8、如权利要求7的方法，进一步包括从构图的抗蚀剂结构周围去除至少部分的TEOS层。
9、如权利要求8的方法，进一步包括从构图的抗蚀剂结构周围去除至少部分有机ARC层以制造构图叠层。
10、如权利要求9的方法，进一步包括从构图叠层周围去除导体层以在构图叠层下面制造栅电极。
11、如权利要求10的方法，进一步包括去除构图叠层。
12、如权利要求1的方法，其特征在于使用248nm或更小的波长的光进行构图。
13、如权利要求1的方法，其特征在于导体层包括多晶硅。
14、如权利要求13的方法，进一步包括：
在栅电极上形成侧壁间隔件；和
将源极/漏极区扩散进衬底中。
15、一种半导体器件，包括：
半导体衬底；
形成在所述半导体衬底上的绝缘层；
形成在所述绝缘层上的导体层；
形成在所述导体层上的有机抗反射(ARC)层；
形成在所述有机抗反射(ARC)层上的四乙基原硅酸盐(TEOS)层；和
形成在所述TEOS层上的构图的抗蚀剂层。
16、如权利要求15的半导体器件，其特征在于所述有机抗反射(ARC)层包括无定形碳。
17、如权利要求15的半导体器件，其特征在于所述有机抗反射(ARC)层被沉积为具有大约300到700之间的厚度。
18、如权利要求15的半导体器件，其特征在于所述TEOS层在大约250℃到350℃的范围内形成在所述有机抗反射(ARC)层上。
19、如权利要求15的半导体器件，其特征在于所述TEOS层在大约350℃或更低的温度内形成在所述有机抗反射(ARC)层上。
20、如权利要求15的半导体器件，其特征在于TEOS层具有200到300之间的厚度。
21、如权利要求15的半导体器件，其特征在于构图的抗蚀剂层用于形成金属-氧化物半导体晶体管的栅电极。
22、如权利要求15的半导体器件，其特征在于所述导体层包括多晶硅。
23、一种用于形成半导体器件的方法，包括：
提供半导体衬底；
在所述半导体衬底上形成绝缘层；
在所述绝缘层上形成导体层；
在所述导体层上形成有机抗反射涂层(ARC)；
使用有机硅烷前体在所述有机ARC层上沉积硅氧化物帽层；
在所述帽层上沉积抗蚀剂层；和
构图所述抗蚀剂层以形成构图的抗蚀剂结构。
24、一种用于形成半导体器件的方法，包括：
提供半导体衬底；
在所述半导体衬底上形成绝缘层；
在所述绝缘层上形成导体层；
在所述导体层上形成化学计量的氮化硅层；
在所述化学计量的氮化硅层上形成有机抗反射涂层(ARC)；
在所述有机ARC层上形成富含硅的氧化物层；
在所述富含硅的氧化物层上沉积抗蚀剂层；和
构图所述抗蚀剂层以形成构图的抗蚀剂结构。
25、如权利要求24的方法，其特征在于富含硅的氧化物层包括至少微量氮。
26、一种用于形成半导体器件的方法，包括：
提供半导体衬底；
在所述半导体衬底上形成绝缘层；
在所述绝缘层上形成导体层；
在所述导体层上形成有机反射涂层(ARC)层；
在所述导体层上形成化学计量的氮化硅层；
在所述化学计量的氮化硅层上形成富含硅的氧化物层；
在所述化学计量的氮化硅层上沉积抗蚀剂层；和
构图所述抗蚀剂层以形成构图的抗蚀剂结构。
27、如权利要求26的方法，其特征在于富含硅的氧化物层包括至少微量的氮。
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US7199429B2 (en) 2007-04-03
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US20050181596A1 (en) 2005-08-18
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