KR101113533B1 - 기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법 - Google Patents

기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법 Download PDF

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KR101113533B1
KR101113533B1 KR1020087024646A KR20087024646A KR101113533B1 KR 101113533 B1 KR101113533 B1 KR 101113533B1 KR 1020087024646 A KR1020087024646 A KR 1020087024646A KR 20087024646 A KR20087024646 A KR 20087024646A KR 101113533 B1 KR101113533 B1 KR 101113533B1
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South Korea
Prior art keywords
substrate
region
delete delete
regions
energy
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KR1020087024646A
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English (en)
Korean (ko)
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KR20080104183A (ko
Inventor
아브힐라쉬 마유어
마크 얌
아지트 발라크리쉬나
폴 카레이
딘 제닝스
스티븐 모파트
윌리엄 샤퍼
알렉산더 엔. 러너
티모시 엔. 토마스
아론 무이어 헌터
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어플라이드 머티어리얼스, 인코포레이티드
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Priority claimed from US11/459,852 external-priority patent/US20070221640A1/en
Application filed by 어플라이드 머티어리얼스, 인코포레이티드 filed Critical 어플라이드 머티어리얼스, 인코포레이티드
Publication of KR20080104183A publication Critical patent/KR20080104183A/ko
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Publication of KR101113533B1 publication Critical patent/KR101113533B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020087024646A 2006-03-08 2007-02-23 기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법 KR101113533B1 (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US78074506P 2006-03-08 2006-03-08
US60/780,745 2006-03-08
US11/459,852 2006-07-25
US11/459,856 2006-07-25
US11/459,852 US20070221640A1 (en) 2006-03-08 2006-07-25 Apparatus for thermal processing structures formed on a substrate
US11/459,847 2006-07-25
US11/459,847 US7569463B2 (en) 2006-03-08 2006-07-25 Method of thermal processing structures formed on a substrate
US11/459,856 US20070212859A1 (en) 2006-03-08 2006-07-25 Method of thermal processing structures formed on a substrate
PCT/US2007/062672 WO2007103643A2 (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020107024018A Division KR101323222B1 (ko) 2006-03-08 2007-02-23 기판상에 형성되는 구조체의 열적 프로세싱을 위한 장치 및 방법

Publications (2)

Publication Number Publication Date
KR20080104183A KR20080104183A (ko) 2008-12-01
KR101113533B1 true KR101113533B1 (ko) 2012-02-29

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KR1020087024646A KR101113533B1 (ko) 2006-03-08 2007-02-23 기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법
KR1020107024018A KR101323222B1 (ko) 2006-03-08 2007-02-23 기판상에 형성되는 구조체의 열적 프로세싱을 위한 장치 및 방법

Family Applications After (1)

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KR1020107024018A KR101323222B1 (ko) 2006-03-08 2007-02-23 기판상에 형성되는 구조체의 열적 프로세싱을 위한 장치 및 방법

Country Status (4)

Country Link
EP (1) EP1992013A2 (ja)
JP (1) JP5558006B2 (ja)
KR (2) KR101113533B1 (ja)
WO (1) WO2007103643A2 (ja)

Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
US9498845B2 (en) 2007-11-08 2016-11-22 Applied Materials, Inc. Pulse train annealing method and apparatus
US20090120924A1 (en) * 2007-11-08 2009-05-14 Stephen Moffatt Pulse train annealing method and apparatus
US9012315B2 (en) * 2013-08-09 2015-04-21 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
KR102216675B1 (ko) * 2014-06-12 2021-02-18 삼성디스플레이 주식회사 디스플레이 패널의 리페어 장치 및 디스플레이 패널의 리페어 방법
EP3611757A1 (en) * 2018-08-16 2020-02-19 Laser Systems & Solutions of Europe Method for forming a doped region on a semiconductor material

Citations (1)

* Cited by examiner, † Cited by third party
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KR20040047967A (ko) * 2001-10-25 2004-06-05 어드밴스드 마이크로 디바이시즈, 인코포레이티드 저-온 포스트-도펀트 활성화 공정

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KR20040047967A (ko) * 2001-10-25 2004-06-05 어드밴스드 마이크로 디바이시즈, 인코포레이티드 저-온 포스트-도펀트 활성화 공정

Also Published As

Publication number Publication date
JP5558006B2 (ja) 2014-07-23
WO2007103643A2 (en) 2007-09-13
KR20100133454A (ko) 2010-12-21
KR101323222B1 (ko) 2013-10-30
WO2007103643A3 (en) 2008-05-08
WO2007103643B1 (en) 2008-06-26
EP1992013A2 (en) 2008-11-19
KR20080104183A (ko) 2008-12-01
JP2009529245A (ja) 2009-08-13

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