KR101076062B1 - 오프셋 집적 회로 패키지-온-패키지 적층 시스템 - Google Patents
오프셋 집적 회로 패키지-온-패키지 적층 시스템 Download PDFInfo
- Publication number
- KR101076062B1 KR101076062B1 KR1020060043994A KR20060043994A KR101076062B1 KR 101076062 B1 KR101076062 B1 KR 101076062B1 KR 1020060043994 A KR1020060043994 A KR 1020060043994A KR 20060043994 A KR20060043994 A KR 20060043994A KR 101076062 B1 KR101076062 B1 KR 101076062B1
- Authority
- KR
- South Korea
- Prior art keywords
- package
- offset
- base
- substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Amplifiers (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US59488405P | 2005-05-16 | 2005-05-16 | |
| US60/594,884 | 2005-05-16 | ||
| US11/383,403 US7518224B2 (en) | 2005-05-16 | 2006-05-15 | Offset integrated circuit package-on-package stacking system |
| US11/383,403 | 2006-05-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20060118363A KR20060118363A (ko) | 2006-11-23 |
| KR101076062B1 true KR101076062B1 (ko) | 2011-10-21 |
Family
ID=38038592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020060043994A Active KR101076062B1 (ko) | 2005-05-16 | 2006-05-16 | 오프셋 집적 회로 패키지-온-패키지 적층 시스템 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7518224B2 (https=) |
| JP (1) | JP4402074B2 (https=) |
| KR (1) | KR101076062B1 (https=) |
| TW (1) | TWI334639B (https=) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090004171A (ko) * | 2007-07-06 | 2009-01-12 | 삼성전자주식회사 | 반도체 패키지 |
| US7872340B2 (en) * | 2007-08-31 | 2011-01-18 | Stats Chippac Ltd. | Integrated circuit package system employing an offset stacked configuration |
| US7812435B2 (en) * | 2007-08-31 | 2010-10-12 | Stats Chippac Ltd. | Integrated circuit package-in-package system with side-by-side and offset stacking |
| US8536692B2 (en) * | 2007-12-12 | 2013-09-17 | Stats Chippac Ltd. | Mountable integrated circuit package system with mountable integrated circuit die |
| US8084849B2 (en) * | 2007-12-12 | 2011-12-27 | Stats Chippac Ltd. | Integrated circuit package system with offset stacking |
| US7781261B2 (en) * | 2007-12-12 | 2010-08-24 | Stats Chippac Ltd. | Integrated circuit package system with offset stacking and anti-flash structure |
| US7985628B2 (en) * | 2007-12-12 | 2011-07-26 | Stats Chippac Ltd. | Integrated circuit package system with interconnect lock |
| JP5543071B2 (ja) * | 2008-01-21 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置およびこれを有する半導体モジュール |
| US8067828B2 (en) * | 2008-03-11 | 2011-11-29 | Stats Chippac Ltd. | System for solder ball inner stacking module connection |
| US20090243069A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with redistribution |
| US9293385B2 (en) * | 2008-07-30 | 2016-03-22 | Stats Chippac Ltd. | RDL patterning with package on package system |
| US7785925B2 (en) * | 2008-12-19 | 2010-08-31 | Stats Chippac Ltd. | Integrated circuit packaging system with package stacking and method of manufacture thereof |
| US7968995B2 (en) * | 2009-06-11 | 2011-06-28 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
| KR20120032293A (ko) * | 2010-09-28 | 2012-04-05 | 삼성전자주식회사 | 반도체 패키지 |
| US8508045B2 (en) * | 2011-03-03 | 2013-08-13 | Broadcom Corporation | Package 3D interconnection and method of making same |
| US10163877B2 (en) * | 2011-11-07 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | System in package process flow |
| KR102021077B1 (ko) * | 2013-01-24 | 2019-09-11 | 삼성전자주식회사 | 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법 |
| JP6370920B2 (ja) * | 2014-04-30 | 2018-08-08 | インテル コーポレイション | 成形コンパウンドを有する集積回路アセンブリ |
| US9871007B2 (en) * | 2015-09-25 | 2018-01-16 | Intel Corporation | Packaged integrated circuit device with cantilever structure |
| US10418312B2 (en) | 2015-10-29 | 2019-09-17 | Intel Corporation | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages |
| US10631410B2 (en) | 2016-09-24 | 2020-04-21 | Apple Inc. | Stacked printed circuit board packages |
| US11508663B2 (en) * | 2018-02-02 | 2022-11-22 | Marvell Israel (M.I.S.L) Ltd. | PCB module on package |
| WO2020250162A1 (en) | 2019-06-10 | 2020-12-17 | Marvell Israel (M.I.S.L) Ltd. | Ic package with top-side memory module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044362A (ja) | 1999-07-27 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置の実装構造および実装方法 |
| KR100546359B1 (ko) | 2003-07-31 | 2006-01-26 | 삼성전자주식회사 | 동일 평면상에 횡 배치된 기능부 및 실장부를 구비하는 반도체 칩 패키지 및 그 적층 모듈 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5579207A (en) * | 1994-10-20 | 1996-11-26 | Hughes Electronics | Three-dimensional integrated circuit stacking |
| US5907903A (en) * | 1996-05-24 | 1999-06-01 | International Business Machines Corporation | Multi-layer-multi-chip pyramid and circuit board structure and method of forming same |
| US5748452A (en) * | 1996-07-23 | 1998-05-05 | International Business Machines Corporation | Multi-electronic device package |
| US5986209A (en) * | 1997-07-09 | 1999-11-16 | Micron Technology, Inc. | Package stack via bottom leaded plastic (BLP) packaging |
| JP2000208698A (ja) * | 1999-01-18 | 2000-07-28 | Toshiba Corp | 半導体装置 |
| US6207474B1 (en) * | 1998-03-09 | 2001-03-27 | Micron Technology, Inc. | Method of forming a stack of packaged memory die and resulting apparatus |
| US5854507A (en) * | 1998-07-21 | 1998-12-29 | Hewlett-Packard Company | Multiple chip assembly |
| JP3767246B2 (ja) * | 1999-05-26 | 2006-04-19 | 富士通株式会社 | 複合モジュール及びプリント回路基板ユニット |
| JP3798597B2 (ja) * | 1999-11-30 | 2006-07-19 | 富士通株式会社 | 半導体装置 |
| US6605875B2 (en) * | 1999-12-30 | 2003-08-12 | Intel Corporation | Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size |
| JP2001267473A (ja) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
| US6731009B1 (en) * | 2000-03-20 | 2004-05-04 | Cypress Semiconductor Corporation | Multi-die assembly |
| US6518659B1 (en) * | 2000-05-08 | 2003-02-11 | Amkor Technology, Inc. | Stackable package having a cavity and a lid for an electronic device |
| US6667544B1 (en) * | 2000-06-30 | 2003-12-23 | Amkor Technology, Inc. | Stackable package having clips for fastening package and tool for opening clips |
| US7423336B2 (en) * | 2002-04-08 | 2008-09-09 | Micron Technology, Inc. | Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices |
| JP4601892B2 (ja) * | 2002-07-04 | 2010-12-22 | ラムバス・インコーポレーテッド | 半導体装置および半導体チップのバンプ製造方法 |
| US20040021230A1 (en) * | 2002-08-05 | 2004-02-05 | Macronix International Co., Ltd. | Ultra thin stacking packaging device |
| JP2004071947A (ja) * | 2002-08-08 | 2004-03-04 | Renesas Technology Corp | 半導体装置 |
| KR100480437B1 (ko) * | 2002-10-24 | 2005-04-07 | 삼성전자주식회사 | 반도체 칩 패키지 적층 모듈 |
| US6798057B2 (en) * | 2002-11-05 | 2004-09-28 | Micron Technology, Inc. | Thin stacked ball-grid array package |
| JP4110992B2 (ja) * | 2003-02-07 | 2008-07-02 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
| JP4408636B2 (ja) * | 2003-02-28 | 2010-02-03 | 三洋電機株式会社 | 回路装置およびその製造方法 |
| TW576549U (en) * | 2003-04-04 | 2004-02-11 | Advanced Semiconductor Eng | Multi-chip package combining wire-bonding and flip-chip configuration |
| JP3951966B2 (ja) * | 2003-05-30 | 2007-08-01 | セイコーエプソン株式会社 | 半導体装置 |
| US7095104B2 (en) * | 2003-11-21 | 2006-08-22 | International Business Machines Corporation | Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same |
| US7091581B1 (en) * | 2004-06-14 | 2006-08-15 | Asat Limited | Integrated circuit package and process for fabricating the same |
| JP2006186136A (ja) * | 2004-12-28 | 2006-07-13 | Toshiba Corp | 両面部品実装回路基板及びその製造方法 |
| US7312519B2 (en) * | 2006-01-12 | 2007-12-25 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
| US7420269B2 (en) * | 2006-04-18 | 2008-09-02 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
| US7535086B2 (en) * | 2006-08-03 | 2009-05-19 | Stats Chippac Ltd. | Integrated circuit package-on-package stacking system |
| US7772683B2 (en) * | 2006-12-09 | 2010-08-10 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
| US7635913B2 (en) * | 2006-12-09 | 2009-12-22 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
-
2006
- 2006-05-15 US US11/383,403 patent/US7518224B2/en active Active
- 2006-05-16 JP JP2006136747A patent/JP4402074B2/ja active Active
- 2006-05-16 KR KR1020060043994A patent/KR101076062B1/ko active Active
- 2006-05-16 TW TW095117221A patent/TWI334639B/zh active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044362A (ja) | 1999-07-27 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置の実装構造および実装方法 |
| KR100546359B1 (ko) | 2003-07-31 | 2006-01-26 | 삼성전자주식회사 | 동일 평면상에 횡 배치된 기능부 및 실장부를 구비하는 반도체 칩 패키지 및 그 적층 모듈 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI334639B (en) | 2010-12-11 |
| JP4402074B2 (ja) | 2010-01-20 |
| US7518224B2 (en) | 2009-04-14 |
| JP2006324665A (ja) | 2006-11-30 |
| TW200703599A (en) | 2007-01-16 |
| US20070108581A1 (en) | 2007-05-17 |
| KR20060118363A (ko) | 2006-11-23 |
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