KR101076062B1 - 오프셋 집적 회로 패키지-온-패키지 적층 시스템 - Google Patents

오프셋 집적 회로 패키지-온-패키지 적층 시스템 Download PDF

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Publication number
KR101076062B1
KR101076062B1 KR1020060043994A KR20060043994A KR101076062B1 KR 101076062 B1 KR101076062 B1 KR 101076062B1 KR 1020060043994 A KR1020060043994 A KR 1020060043994A KR 20060043994 A KR20060043994 A KR 20060043994A KR 101076062 B1 KR101076062 B1 KR 101076062B1
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South Korea
Prior art keywords
package
offset
base
substrate
integrated circuit
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KR1020060043994A
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English (en)
Korean (ko)
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KR20060118363A (ko
Inventor
심일권
한병준
쵸승관
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스태츠 칩팩 엘티디
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Application granted granted Critical
Publication of KR101076062B1 publication Critical patent/KR101076062B1/ko
Assigned to 주식회사 한국씨티은행 reassignment 주식회사 한국씨티은행 근질권설정등록 Assignors: 스태츠 칩팩 피티이. 엘티디.
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Amplifiers (AREA)
KR1020060043994A 2005-05-16 2006-05-16 오프셋 집적 회로 패키지-온-패키지 적층 시스템 Active KR101076062B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US59488405P 2005-05-16 2005-05-16
US60/594,884 2005-05-16
US11/383,403 US7518224B2 (en) 2005-05-16 2006-05-15 Offset integrated circuit package-on-package stacking system
US11/383,403 2006-05-15

Publications (2)

Publication Number Publication Date
KR20060118363A KR20060118363A (ko) 2006-11-23
KR101076062B1 true KR101076062B1 (ko) 2011-10-21

Family

ID=38038592

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060043994A Active KR101076062B1 (ko) 2005-05-16 2006-05-16 오프셋 집적 회로 패키지-온-패키지 적층 시스템

Country Status (4)

Country Link
US (1) US7518224B2 (https=)
JP (1) JP4402074B2 (https=)
KR (1) KR101076062B1 (https=)
TW (1) TWI334639B (https=)

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KR20090004171A (ko) * 2007-07-06 2009-01-12 삼성전자주식회사 반도체 패키지
US7872340B2 (en) * 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
US7812435B2 (en) * 2007-08-31 2010-10-12 Stats Chippac Ltd. Integrated circuit package-in-package system with side-by-side and offset stacking
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
JP5543071B2 (ja) * 2008-01-21 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置およびこれを有する半導体モジュール
US8067828B2 (en) * 2008-03-11 2011-11-29 Stats Chippac Ltd. System for solder ball inner stacking module connection
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US7968995B2 (en) * 2009-06-11 2011-06-28 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
KR20120032293A (ko) * 2010-09-28 2012-04-05 삼성전자주식회사 반도체 패키지
US8508045B2 (en) * 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
KR102021077B1 (ko) * 2013-01-24 2019-09-11 삼성전자주식회사 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법
JP6370920B2 (ja) * 2014-04-30 2018-08-08 インテル コーポレイション 成形コンパウンドを有する集積回路アセンブリ
US9871007B2 (en) * 2015-09-25 2018-01-16 Intel Corporation Packaged integrated circuit device with cantilever structure
US10418312B2 (en) 2015-10-29 2019-09-17 Intel Corporation Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US10631410B2 (en) 2016-09-24 2020-04-21 Apple Inc. Stacked printed circuit board packages
US11508663B2 (en) * 2018-02-02 2022-11-22 Marvell Israel (M.I.S.L) Ltd. PCB module on package
WO2020250162A1 (en) 2019-06-10 2020-12-17 Marvell Israel (M.I.S.L) Ltd. Ic package with top-side memory module

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KR100546359B1 (ko) 2003-07-31 2006-01-26 삼성전자주식회사 동일 평면상에 횡 배치된 기능부 및 실장부를 구비하는 반도체 칩 패키지 및 그 적층 모듈

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KR100546359B1 (ko) 2003-07-31 2006-01-26 삼성전자주식회사 동일 평면상에 횡 배치된 기능부 및 실장부를 구비하는 반도체 칩 패키지 및 그 적층 모듈

Also Published As

Publication number Publication date
TWI334639B (en) 2010-12-11
JP4402074B2 (ja) 2010-01-20
US7518224B2 (en) 2009-04-14
JP2006324665A (ja) 2006-11-30
TW200703599A (en) 2007-01-16
US20070108581A1 (en) 2007-05-17
KR20060118363A (ko) 2006-11-23

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