KR101013302B1 - 측면 및 상부 게이트가 형성된 판독 트랜지스터를 가진듀얼 포트 게인 셀 - Google Patents

측면 및 상부 게이트가 형성된 판독 트랜지스터를 가진듀얼 포트 게인 셀 Download PDF

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Publication number
KR101013302B1
KR101013302B1 KR1020087004060A KR20087004060A KR101013302B1 KR 101013302 B1 KR101013302 B1 KR 101013302B1 KR 1020087004060 A KR1020087004060 A KR 1020087004060A KR 20087004060 A KR20087004060 A KR 20087004060A KR 101013302 B1 KR101013302 B1 KR 101013302B1
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South Korea
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gate
forming
read
oxide
node
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KR1020087004060A
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English (en)
Korean (ko)
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KR20080036202A (ko
Inventor
잭 만델만
강구오 쳉
라마찬드라 디바카루니
칼 라덴스
겡 왕
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

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  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
KR1020087004060A 2005-08-24 2006-06-27 측면 및 상부 게이트가 형성된 판독 트랜지스터를 가진듀얼 포트 게인 셀 Expired - Fee Related KR101013302B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/161,962 2005-08-24
US11/161,962 US7459743B2 (en) 2005-08-24 2005-08-24 Dual port gain cell with side and top gated read transistor

Publications (2)

Publication Number Publication Date
KR20080036202A KR20080036202A (ko) 2008-04-25
KR101013302B1 true KR101013302B1 (ko) 2011-02-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087004060A Expired - Fee Related KR101013302B1 (ko) 2005-08-24 2006-06-27 측면 및 상부 게이트가 형성된 판독 트랜지스터를 가진듀얼 포트 게인 셀

Country Status (7)

Country Link
US (2) US7459743B2 (enExample)
EP (1) EP1938378B1 (enExample)
JP (1) JP5102767B2 (enExample)
KR (1) KR101013302B1 (enExample)
CN (1) CN101248529B (enExample)
TW (1) TWI413983B (enExample)
WO (1) WO2007023011A2 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8283441B2 (en) 2006-10-31 2012-10-09 University Of Toledo Na+K+-ATPase-specific peptide inhibitors/activators of SRC and SRC family kinases
JP4524699B2 (ja) * 2007-10-17 2010-08-18 ソニー株式会社 表示装置
US20120302630A1 (en) 2009-09-16 2012-11-29 Chinese Academy Of Medical Sciences Na/K-ATPase Ligands, Ouabain Antagonists, Assays and Uses Thereof
KR101788521B1 (ko) 2009-10-30 2017-10-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
IN2012DN05057A (enExample) * 2009-12-28 2015-10-09 Semiconductor Energy Lab
WO2011088210A1 (en) 2010-01-13 2011-07-21 The University Of Toledo Materials and methods related to sodium/potassium adenosine triphosphatase and src
WO2011145738A1 (en) 2010-05-20 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving semiconductor device
US8792284B2 (en) * 2010-08-06 2014-07-29 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor memory device
US8743590B2 (en) * 2011-04-08 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device using the same
US9111634B2 (en) 2012-07-13 2015-08-18 Freescale Semiconductor, Inc. Methods and structures for multiport memory devices
KR20140092537A (ko) 2013-01-16 2014-07-24 삼성전자주식회사 메모리 셀 및 이를 포함하는 메모리 장치
JP6516978B2 (ja) 2013-07-17 2019-05-22 株式会社半導体エネルギー研究所 半導体装置
WO2015047233A1 (en) * 2013-09-25 2015-04-02 Intel Corporation Methods of forming buried vertical capacitors and structures formed thereby
KR102168652B1 (ko) 2013-12-16 2020-10-23 삼성전자주식회사 감지 증폭기, 그것을 포함하는 반도체 메모리 장치 및 그것의 읽기 방법
WO2017111798A1 (en) * 2015-12-23 2017-06-29 Intel Corporation High retention time memory element with dual gate devices
CN110291585B (zh) * 2017-03-22 2024-07-05 英特尔公司 采用自对准的顶栅薄膜晶体管的嵌入式存储器
US11222690B2 (en) * 2018-12-26 2022-01-11 Micron Technology, Inc. Vertical 3D single word line gain cell with shared read/write bit line
WO2024060021A1 (zh) * 2022-09-20 2024-03-28 华为技术有限公司 一种三维存储阵列、存储器及电子设备
CN118678660A (zh) * 2023-03-17 2024-09-20 华为技术有限公司 三维存储阵列、存储器及电子设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001230329A (ja) 2000-02-16 2001-08-24 Sony Corp 半導体記憶装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370557A (ja) * 1986-09-12 1988-03-30 Nec Corp 半導体メモリセル
US4763181A (en) 1986-12-08 1988-08-09 Motorola, Inc. High density non-charge-sensing DRAM cell
JPH01307256A (ja) * 1988-06-06 1989-12-12 Hitachi Ltd 半導体記憶装置
JP2918307B2 (ja) * 1990-08-07 1999-07-12 沖電気工業株式会社 半導体記憶素子
JP3227917B2 (ja) 1993-07-26 2001-11-12 ソニー株式会社 増幅型ｄｒａｍ用メモリセルおよびその製造方法
JPH08250673A (ja) * 1995-03-15 1996-09-27 Nec Corp 半導体装置
EP0766312B1 (de) * 1995-09-26 2002-01-16 Infineon Technologies AG Selbstverstärkende DRAM-Speicherzellenanordnung
US5732014A (en) 1997-02-20 1998-03-24 Micron Technology, Inc. Merged transistor structure for gain memory cell
TW425718B (en) * 1997-06-11 2001-03-11 Siemens Ag Vertical transistor
DE19752968C1 (de) * 1997-11-28 1999-06-24 Siemens Ag Speicherzellenanordnung und Verfahren zu deren Herstellung
JP2001093988A (ja) * 1999-07-22 2001-04-06 Sony Corp 半導体記憶装置
JP2002118240A (ja) * 2000-10-05 2002-04-19 Toshiba Corp 半導体記憶装置および半導体記憶装置の製造方法
DE10220584B3 (de) * 2002-05-08 2004-01-08 Infineon Technologies Ag Dynamische Speicherzelle und Verfahren zum Herstellen derselben
US6750097B2 (en) * 2002-07-30 2004-06-15 International Business Machines Corporation Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby
DE10248722A1 (de) * 2002-10-18 2004-05-06 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Kondensator und Herstellungsverfahren
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US6964897B2 (en) * 2003-06-09 2005-11-15 International Business Machines Corporation SOI trench capacitor cell incorporating a low-leakage floating body array transistor
US7232719B2 (en) * 2005-03-28 2007-06-19 Promos Technologies Inc. Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate
US20070045698A1 (en) * 2005-08-31 2007-03-01 International Business Machines Corporation Semiconductor structures with body contacts and fabrication methods thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001230329A (ja) 2000-02-16 2001-08-24 Sony Corp 半導体記憶装置

Also Published As

Publication number Publication date
US7459743B2 (en) 2008-12-02
US20090047756A1 (en) 2009-02-19
JP5102767B2 (ja) 2012-12-19
TWI413983B (zh) 2013-11-01
CN101248529B (zh) 2010-05-19
EP1938378B1 (en) 2013-03-20
WO2007023011A2 (en) 2007-03-01
WO2007023011A3 (en) 2007-06-21
JP2009506526A (ja) 2009-02-12
US20070047293A1 (en) 2007-03-01
CN101248529A (zh) 2008-08-20
US7790530B2 (en) 2010-09-07
EP1938378A2 (en) 2008-07-02
KR20080036202A (ko) 2008-04-25
TW200725617A (en) 2007-07-01
WO2007023011B1 (en) 2007-07-12

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