KR101007932B1 - 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법 - Google Patents

패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법 Download PDF

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KR101007932B1
KR101007932B1 KR1020080072576A KR20080072576A KR101007932B1 KR 101007932 B1 KR101007932 B1 KR 101007932B1 KR 1020080072576 A KR1020080072576 A KR 1020080072576A KR 20080072576 A KR20080072576 A KR 20080072576A KR 101007932 B1 KR101007932 B1 KR 101007932B1
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South Korea
Prior art keywords
pattern
thermal
substrate
deformation
template
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KR1020080072576A
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English (en)
Korean (ko)
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KR20100011382A (ko
Inventor
엄기상
임정호
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세크론 주식회사
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Priority to KR1020080072576A priority Critical patent/KR101007932B1/ko
Priority to PCT/KR2009/001898 priority patent/WO2010011017A1/fr
Priority to TW098112285A priority patent/TWI396244B/zh
Publication of KR20100011382A publication Critical patent/KR20100011382A/ko
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Publication of KR101007932B1 publication Critical patent/KR101007932B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
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    • H01L2924/01019—Potassium [K]
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    • H01L2924/01033—Arsenic [As]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
KR1020080072576A 2008-07-25 2008-07-25 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법 KR101007932B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020080072576A KR101007932B1 (ko) 2008-07-25 2008-07-25 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법
PCT/KR2009/001898 WO2010011017A1 (fr) 2008-07-25 2009-04-14 Procédé de détermination d’une position de motif et d’une position de cavité, et procédé de formation d’un bossage de soudure l’utilisant
TW098112285A TWI396244B (zh) 2008-07-25 2009-04-14 決定圖案位置和模穴位置的方法，以及應用其之形成錫塊之方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080072576A KR101007932B1 (ko) 2008-07-25 2008-07-25 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법

Publications (2)

Publication Number Publication Date
KR20100011382A KR20100011382A (ko) 2010-02-03
KR101007932B1 true KR101007932B1 (ko) 2011-01-14

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Application Number Title Priority Date Filing Date
KR1020080072576A KR101007932B1 (ko) 2008-07-25 2008-07-25 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법

Country Status (3)

Country Link
KR (1) KR101007932B1 (fr)
TW (1) TWI396244B (fr)
WO (1) WO2010011017A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010068289A (ko) * 2000-01-04 2001-07-23 박종섭 솔더 조인트 신뢰성을 향상시킨 비지에이 반도체 패키지및 그 제조 방법
KR20050053751A (ko) * 2002-10-11 2005-06-08 테세라, 인코포레이티드 다중-칩 패키지들을 위한 컴포넌트, 방법 및 어셈블리
US20060286716A1 (en) 2002-12-18 2006-12-21 K-Tec Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4243117B2 (ja) * 2002-08-27 2009-03-25 新光電気工業株式会社 半導体パッケージとその製造方法および半導体装置
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
JP2006049569A (ja) * 2004-08-04 2006-02-16 Sharp Corp スタック型半導体装置パッケージおよびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010068289A (ko) * 2000-01-04 2001-07-23 박종섭 솔더 조인트 신뢰성을 향상시킨 비지에이 반도체 패키지및 그 제조 방법
KR20050053751A (ko) * 2002-10-11 2005-06-08 테세라, 인코포레이티드 다중-칩 패키지들을 위한 컴포넌트, 방법 및 어셈블리
US20060286716A1 (en) 2002-12-18 2006-12-21 K-Tec Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package

Also Published As

Publication number Publication date
TWI396244B (zh) 2013-05-11
KR20100011382A (ko) 2010-02-03
TW201005844A (en) 2010-02-01
WO2010011017A1 (fr) 2010-01-28

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