WO2010011017A1 - Procédé de détermination d’une position de motif et d’une position de cavité, et procédé de formation d’un bossage de soudure l’utilisant - Google Patents

Procédé de détermination d’une position de motif et d’une position de cavité, et procédé de formation d’un bossage de soudure l’utilisant Download PDF

Info

Publication number
WO2010011017A1
WO2010011017A1 PCT/KR2009/001898 KR2009001898W WO2010011017A1 WO 2010011017 A1 WO2010011017 A1 WO 2010011017A1 KR 2009001898 W KR2009001898 W KR 2009001898W WO 2010011017 A1 WO2010011017 A1 WO 2010011017A1
Authority
WO
WIPO (PCT)
Prior art keywords
thermal expansion
substrate
template
pattern
ratio
Prior art date
Application number
PCT/KR2009/001898
Other languages
English (en)
Inventor
Ki-Sang Eum
Jung-Ho Leem
Original Assignee
Secron Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Secron Co., Ltd. filed Critical Secron Co., Ltd.
Publication of WO2010011017A1 publication Critical patent/WO2010011017A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • Example embodiments relate to a method of determining a pattern position and a cavity position, and a method of forming a solder bump using the same. More particularly, example embodiments relate to a method of determining positions of patterns that are formed on respective substrates having different thermal expansion coefficients (TECs) by using thermal expansion ratios of the substrates, a method of determining positions of cavities of a template corresponding to the patterns by using the above method, and a method of forming solder bumps on a substrate by using the above method.
  • TECs thermal expansion coefficients
  • Micro-electronic packaging technology now typically includes using a solder bump in place of a wire bonding for an electric junction between conductive members.
  • Various processes using the solder bump have been suggested, such as an electroplating process, a solder paste printing process, an evaporation and de-watering process, and a direct bonding process of solder balls.
  • C4NP controlled collapse chip connection new process
  • a plurality of sphere-shaped solder bumps is formed in the cavities of a template and is bonded to the bump pad of a wafer by a thermo-compression method.
  • the bump pad is electrically connected to metal wirings of a semiconductor chip and an under-bump metallurgy (UBM) pad is formed on the bump pad.
  • UBM pad is interposed between the solder bump and the bump pad and improves the adhesion between the solder bump and the bump pad.
  • a plurality of semiconductor chips adhered to the solder bump is separated into individual by a dicing process, and the separated individual is bonded to a substrate by a thermo compression process and an underfill process, to thereby fabricate a flip chip.
  • a melted solder is injected into cavities of the template and is solidified into sphere-shaped solid balls in the cavities of the template. Then, the cavities of the template are aligned with the bump pad on the substrate and the combination of the template and the substrate including the bump pad are heated. As a result of the heat provided to the combination, the sphere-shaped solder bumps are transferred onto the bump pad of the substrate, and thus the solder bumps are formed on the bump pad of the substrate.
  • a thermal expansion coefficient (TEC) of the template is generally different from that of the substrate, and thus thermal expansion of the template is usually different from that of the substrate when the combination of the template and the substrate is heated during the formation of the solder bumps on the bump pad. Therefore, the solder bumps may not be correctly arranged on the bump pad. For that reason, the TEC of the template should be substantially the same as or at least greater than 70% of the TEC of the substrate so as to avoid misalignments of solder bumps on the bump pad. That is, the difference of the TEC between the template and the substrate should be less than about 30%.
  • the above TEC condition leads to significant limitations on the selection of materials for the template and the substrate.
  • Example embodiments provide a method of determining the position of a pattern irrespective of the thermal expansion coefficient (TEC) of a substrate on which the pattern is formed.
  • TEC thermal expansion coefficient
  • Example embodiments also provide a method of determining a position of the cavity of a template irrespective of the TEC of the template.
  • Example embodiments also provide a method of forming a solder bump on a substrate in accordance with correct cavities of a template irrespective of the TEC of the template.
  • a method of determining a pattern position on a substrate A first thermal expansion ratio ( ⁇ l 1 ) may be obtained with respect to a first substrate on which a first pattern is formed.
  • the first substrate has a first TEC and the first thermal expansion ratio denotes a ratio of an amount of thermal expansion per unit length of the first substrate with respect to temperature variation of the first substrate.
  • a second thermal expansion ratio ( ⁇ l 2 ) may be obtained with respect to a second substrate on which a second pattern is formed correspondently to the first pattern.
  • the second substrate has a second TEC different from the first TEC and the second thermal expansion ratio denotes a ratio of an amount of thermal expansion per unit length of the second substrate with respect to temperature variation of the second substrate.
  • a second original position (L 21 ), which indicates a position of the second pattern prior to a thermal expansion of the second substrate, may be determined by using the first and second thermal expansion ratios ( ⁇ l 1 and ⁇ l 2 ) and a first original position L 11 which indicates a position of the first pattern prior to a thermal expansion of the first substrate.
  • the second original position (L 21 ) is determined by the following expression (1):
  • the second original position (L 21 ) may be determined as follows:
  • the first original position L 11 of the first pattern may be determined and a first deformed position L 12 , which indicates a position of the first pattern after a thermal expansion of the first substrate, may be determined by the following expression (2).
  • a second deformed position L 22 which indicates a position of the second pattern aftera thermal expansion of the second substrate, may be determined by the following expression (3).
  • a method of determining a cavity position on a template A first thermal expansion ratio ( ⁇ l 1 ) may be obtained with respect to a wafer on which a pattern is formed.
  • the wafer has a first TEC and the first thermal expansion ratio denotes a ratio of an amount of thermal expansion per unit length of the wafer with respect to temperature variation of the wafer.
  • a second thermal expansion ratio ( ⁇ l 2 ) may be obtained with respect to a template on which a cavity is formed correspondently to the pattern on the wafer.
  • the template has a second TEC different from the first TEC and the second thermal expansion ratio denotes a ratio of an amount of thermal expansion per unit length of the template with respect to temperature variation of the template.
  • a second original position (Z c ), which indicates a position of the cavity prior to a thermal expansion of the template, may be determined by using the first and second thermal expansion ratios ( ⁇ l 1 and ⁇ l 2 ) and a first original position (Z w ), which indicates a position of the pattern on the wafer prior to a thermal expansion of the wafer.
  • the second original position (Z c ) is determined by the following expression (4):
  • a substrate having a bump pad thereon and having a first thermal expansion ratio may be prepared.
  • the substrate has a first TEC and the first thermal expansion ratio denotes a ratio of an amount of thermal expansion per unit length of the substrate with respect to temperature variation of the substrate.
  • a template having a second thermal expansion ratio ( ⁇ l 2 ) may also be prepared simultaneously with the substrate.
  • the template has a second TEC different from the first TECand the second thermal expansion ratio denotes a ratio of an amount of thermal expansion per unit length of the template with respect to temperature variation of the template.
  • a cavity may be formed on the template correspondently to the bump pad and the position of the cavity may be determined by using the first thermal expansion ratio ( ⁇ l 1 ) and the second thermal expansion ratio ( ⁇ l 2 ).
  • a melted solder may be supplied into the cavity and a solder ball may be formed in the cavity by reflowing the template.
  • the substrate may be aligned with the template such that the bump pad makes contact with the solder ball and the substrate and the template may be heated to thereby transcribe the solder ball onto the bump pad.
  • the position of the cavity is determined by the following expression (5).
  • Z c denotes the position of the cavity prior to a thermal expansion of the template and Z w indicates a position of the pattern on the wafer prior to a thermal expansion of the wafer).
  • an original position of a second pattern on a second substrate prior to thermal expansion of the second substrate may be obtained irrespective of the difference of the TEC between first and second substrates.
  • no material limitations may be imposed on the selection of the wafer and the template, and thus various materials may be used for the wafer and the template without any limitations on the TECs of the selected materials.
  • misalignments may be minimized when aligning the first and second substrates with each other.
  • FIGS. 1 to 6 represent non-limiting, example embodiments as described herein.
  • FIG. 1 is a flowchart showing processing steps for a method ofdetermining the positions of patterns that are formed on different substrates in accordance with an example embodimentof the present invention
  • FIG. 2 is a flowchart showing processing steps for a method of determining the positions of cavities of templates in accordance with an example embodiment of the present invention.
  • FIGS. 3 to 6 are cross-sectional views illustrating processing steps for a method of forming a solder bump on a substrate in accordance with an example embodiment of the present invention.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below”or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below”can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
  • FIG. 1 is a flowchart showing processing steps for a method of determining the positions of patterns that are formed on different substrates in accordance with an example embodiment of the present invention.
  • a first thermal expansion ratio ( ⁇ l 1 ) may be obtained with respect to a first substrate on which a first pattern may be formed (step S110).
  • the first thermal expansion ratio ( ⁇ l 1 ) denotes a ratio of an amount of thermal expansion per unit length of the first substrate with respect to temperature variation of the first substrate, and thus indicates a unit thermal expansion of the first substrate with respect to a unit temperature variation.
  • the first thermal expansion ratio ( ⁇ l 1 ) indicates a unit expanded length of the first substrate along a longitudinal direction thereof with respect to the temperature variation between a first temperature and a second temperature.
  • the first and second temperatures may be varied in accordance with process conditions and various environmental conditions.
  • the first substrate may include a semiconductor substrate on which various semiconductor circuit devices may be formed and the first pattern may include a contact pad that is electrically connected to the circuit devices on the first substrate.
  • the contact pad may include a bump pad on which a plurality of solder bumps is formed and a plurality of the first patterns may be formed on the first substrate.
  • any other substrates known to one of ordinary skill in the art may also be allowed as the first substrate only if the first pattern may be formed on the first substrate.
  • a glass substrate for a flat panel display device may also be used as the first substrate.
  • the first substrate may have various modifications in view of shape, volume, relative positions, etc, as would be known to one of ordinary skill in the art.
  • a second thermal expansion ratio ( ⁇ l 2 ) may be obtained with respect to a second substrate on which a second pattern may be formed (step S120).
  • the second thermal expansion ratio ( ⁇ l 2 ) denotes a ratio of an amount of thermal expansion per unit length of the second substrate with respect to temperature variation of the second substrate, and thus indicates a unit thermal expansion of the second substrate with respect to a unit temperature variation.
  • the second thermal expansion ratio ( ⁇ l 2 ) indicates a unit expanded length of the second substrate along a longitudinal direction thereof with respect to the temperature variation between a first temperature and a second temperature.
  • the first and second temperatures may be varied in accordance with process conditions and various environmental conditions.
  • a first thermal expansion coefficient (TEC) of the first substrate may be different from a second TEC of the second substrate.
  • the second TEC may be greater than the first TEC and further the difference between the first and second TECs need not be less than about 30%.
  • the first TEC may be about 3.210-6 and the second TEC may be about 4.510-6and the difference between the first and second TECs may be about 40% with respect to the first substrate. Substantially, no limitations may be imposed on the difference between the first and second TECs.
  • the second pattern may be respectively arranged to the first pattern at the second temperature.
  • the first and second substrates may be aligned with each other at the second temperature in such a manner that the first and second patterns may face each other when a process is performed at the second temperature.
  • a second original position (L 21 ) of the second pattern may be determined by using the first and second thermal expansion ratios ( ⁇ l 1 , ⁇ l 2 ) (step S130). Since the first and second patterns may face each other, the second original position (L 21 ) of the second pattern may correspond to a first original position (L 11 ) of the first pattern.
  • the first original position (L 11 ) may be firstly determined prior to the second original position (L 21 ) (step S131), and then a first deformed position (L 12 ) of the first pattern may be determined by using the first original position (L 11 ) and the first thermal expansion ratio ( ⁇ l 1 ) as is indicated by the following expression (2).
  • the first and second substrates may be heated to a second temperature, and thus the first and second substrates may be thermally expanded on the basis of the first thermal expansion ratio ( ⁇ l 1 ). Since the first pattern needs to be aligned with the second pattern, the first deformed position (L 12 ) of the first pattern may be necessarily the same as a second deformed position (L 22 ) of the second pattern. Therefore, a second original position (L 21 ) of the second pattern may be determined by using the above requirement that the first deformed position (L 12 ) may be substantially the same as the second deformed position (L 22 ) as follows.
  • the second deformed position (L 22 ) of the second pattern may be determined as the following expression (3).
  • the following expression (4) may be induced from expressions (2) and (3).
  • the second original position (L 21 ) may be determined by the following expression (1).
  • the first and second substrates may have different TECs of which the difference may be greater than about 30%
  • the second original position of the second pattern on the second substrate may be accurately determined by using the first and second thermal expansion ratios of the first and second substrates and the first original position of the first pattern on the first substrate. Accordingly, the second original position may be easily determined from the first original position irrespective of the difference range between the first and second TECs.
  • no material limitations may be imposed on the selection of the first and second substrates, and thus various materials may be used for the first and second substrates without any limitations on the TECs of the selected materials.
  • the first TEC of the first substrate was about 3.210-6/C, and a latitudinal length, a longitudinal length and the thickness of the first substrate was about 25 mm, about 300 mm and about 10 mm, respectively.
  • a plurality of the first patterns was arranged on the first substrate along a longitudinal direction thereof at a gap distance of about 15 mm between the first patterns.
  • Each of the first patterns had a width of about 5 mm in the longitudinal direction of the first substrate and a pattern length of about 10 mm in a latitudinal direction of the first substrate, and the first patterns were arranged on the first substrate in such a manner that a lead pattern of the first patterns was spaced apart from a latitudinal edge of the first substrate by a distance of about 10 mm and an end pattern of the first patterns was spaced apart from the other latitudinal edge of the first substrate by a distance of about 5 mm.
  • the first original positions L 11 of each of the first patterns were 10 mm, 30 mm, 50 mm, 70 mm, 90 mm, 110 mm, 130 mm, 150 mm, 170mm, 190 mm, 210 mm, 210 mm, 230 mm, 250 mm, 270 mm and 290 mm, respectively, along the longitudinal direction of the first substrate.
  • the second TEC of the first substrate was about 4.510-6/C, and a latitudinal length, a longitudinal length and a thickness of the first substrate was about 25 mm, about 300 mm and about 10 mm, respectively. Accordingly, the second TEC was about 140% of the first TEC.
  • the first and second substrates were heated to a second temperature of about 250C from a first temperature of about 25C, i.e., room temperature.
  • the first thermal expansion ratio ( ⁇ l 1 ) was measured to be about 0.000104 with respect to the latitudinal length of the first substrate, and the second thermal expansion ratio ( ⁇ l 2 ) was measured to be about 0.000074 with respect to the latitudinal length of the second substrate.
  • the second original positions of the second patterns were calculated in accordance with the above expression (1).
  • Table 1 shows the second original positions of the second patterns calculated from the expression (1) which indicate theoretically expected original positions of each of the second patterns before the second patterns were heated.
  • the second patterns were substantially formed on the second substrate at each of the second original positions L 21 shown in Table 1, respectively.
  • a base line of the second original positions was also a latitudinal edge of the second substrate, such that the first original positions of the first pattern on the first substrate and the second patterns were also arranged on the second substrate along a longitudinal direction thereof.
  • the first substrate including the first patterns and the second substrate including the second patterns were heated to the second temperature from the first temperature, and thus the first and second patterns were thermally deformed in accordance with the TECs of the first and second substrates, respectively.
  • the amount of thermal expansion of the first and second substrates was measured, respectively, and the first and second deformed positions L 11 and L 22 of the first and second patterns were measured as listed in the following Table 2 and Table 3.
  • the position difference between the first and second patterns after the thermal expansion was less than about 6 m. Therefore, when an allowable error range for aligning the first and second substrates was set to be about 10 m, the above first and second patterns having a deformed error range of a maximum of about 6 m were determined to be allowable.
  • the second original position of the second pattern on the second substrate may be determined irrespective of each TEC of the first and second substrates. Therefore, no material limitations may be imposed on the selection of the first and second substrates, and thus various materials may be used for the first and second substrates without any limitations on the TECs of the selected materials. In addition, alignment errors between the first and second patterns after the thermal expansion may be minimized to thereby improve the reliability of the process.
  • FIG. 2 is a flowchart showing processing steps for a method of determining the positions of cavities of templates in accordance with an example embodiment of the present invention.
  • a first thermal expansion ratio ( ⁇ l 1 ) may be obtained with respect to a wafer on which a pattern may be formed (step S210).
  • the first thermal expansionratio ( ⁇ l 1 ) denotes a ratio of an amount of thermal expansion per unit length of the wafer with respect to temperature variation of the wafer, and thus indicates a unit thermal expansion of the wafer with respect to a unit temperature variation.
  • the first thermal expansion ratio ( ⁇ l 1 ) indicates a unit expanded length of the wafer along an edge line of a flat zone thereof with respect to the temperature variation between a first temperature and a second temperature.
  • the first and second temperatures may be varied in accordance with process conditions and various environmental conditions.
  • the pattern may include a contact pad that is electrically connected to the circuit devices on the wafer.
  • the contact pad may include a bump pad on which a plurality of solder bumps is formed and a plurality of the patterns may be formed on the wafer.
  • a second thermal expansion ratio ( ⁇ l 2 ) may be obtained with respect to a template including a cavity (step S220).
  • the second thermal expansion ratio ( ⁇ l 2 ) denotes a ratio of an amount of thermal expansion per unit length of the template with respect to temperature variation of the template, and thus indicates a unit thermal expansion of the template with respect to a unit temperature variation.
  • the second thermal expansion ratio ( ⁇ l 2 ) indicates a unit expanded length of the template along a longitudinal direction thereof with respect to the temperature variation between a first temperature and a second temperature.
  • the first and second temperatures may be varied in accordance with process conditions and various environmental conditions.
  • a first TEC of the wafer may be different from a second TEC of the template.
  • the second TEC may be greater than the first TEC and further the difference between the first and second TECs need not be less than about 30%.
  • the first TEC may be about 3.2x10-6 and the second TEC may be about 4.5x10-6 and the difference between the first and second TECs may be about 40% with respect to the wafer. Substantially, no limitations may be imposed on the difference between the first and second TECs.
  • the cavity of the template may be respectively arranged to the pattern of the wafer at the second temperature.
  • the wafer and the template may be aligned with each other in such a manner that the pattern faces the cavity when a process is performed at the second temperature.
  • a second original position (Z c ) of the cavity may be determined by using the first and second thermal expansion ratios ( ⁇ l 1 , ⁇ l 2 ) (step S230). Since the cavity of the template may face the pattern of the wafer, the second original position (Z c ) of the cavity may correspond to a first original position (Z w ) of the wafer and may be determined by the following expression (5).
  • the second original position (Z c ) of the cavity may be determined in the same method of determining the second original position L 21 of the second pattern, which is described with reference to FIG. 1, and thus any other detailed descriptions on the method of determining the second original position (Z c ) of the cavity will be omitted.
  • the second original position of the cavity on the template may be accurately determined by using the first and second thermal expansion ratios of the wafer and the template and the first original position of the pattern on the wafer. Accordingly, the original position of the cavity may be easily determined from the original position of the pattern irrespective of the difference range between the first and second TECs. As a result, no material limitations may be imposed on the selection of the wafer and the template, and thus various materials may be used for the wafer and the template without any limitations on the TECs of the selected materials.
  • FIGS. 3 to 6 are cross-sectional views illustrating processing steps for a method of forming a solder bump on a substrate in accordance with an example embodiment of the present invention.
  • a bump pad 25 may be formed on a substrate 20.
  • the substrate 20 may have a first thermal expansion ratio ( ⁇ l 1 ) denoting a ratio of an amount of thermal expansion per unit length of the substrate 20 with respect to temperature variation of the substrate 20.
  • a plurality of the bump pads 25 may be formed on the substrate 20 in accordance with process conditions and environmental conditions, and thus a first original position Z w , which denotes an original position of the bump pad 25 before the substrate 20 is heated, may be willingly varied in accordance with process conditions and environmental conditions.
  • the bump pad 25 may be positioned correspondently to a cavity of a template, which may be described hereinafter.
  • An under-bump metallurgy (UBM) pad (not shown) may be further formed on the bump pad 25, to thereby improve adhesion between the bump pad 25 and the solder bump.
  • An aligning mark (not shown) may be further formed on the substrate 20 so as to improve aligning accuracy between the template and substrate 20.
  • a template 10 including a cavity may be prepared in relation with the substrate 20.
  • the template 10 may have a second TEC while the substrate 20 may have a first TEC different from the second TEC.
  • the template 10 may have a second thermal expansion ratio ( ⁇ l 2 ) denoting a ratio of an amount of thermal expansion per unit length of the template 10 with respect to temperature variation of the template 10.
  • the template 10 may include glass substrate comprising silicon oxide such as borosilicate glass (BSG), phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG).
  • the template may be formed into a square-shaped plate.
  • a cavity 11 may be formed on a surface of the template 10 and a melted solder 12 may be supplied into the cavity of the template 10.
  • a second original position Z c which denotes an original position of the cavity 11 before the template 10 is heated, may be determined by using the first and second thermal expansion ratios ( ⁇ l 1 , ⁇ l 2 ). Since the cavity 11 of the template 10 may face the solder bump 25 of the substrate 20, the second original position (Z c ) of the cavity may correspond to the first original position (Z w ) of the solder bump 25 and may be determined by the following expression (6).
  • the cavity 11 of the template 10 may be formed by a wet etching process using an etching mask pattern.
  • the etching mask pattern may be formed on the template 11 to thereby partially expose a surface of the template corresponding to the cavity 11.
  • the exposed portion of the template 11 may be partially removed by a wet etching process using an aqueous hydrogen fluoride (HF) solution as an etchant to thereby form the cavity 11 on the surface of the template 11.
  • HF aqueous hydrogen fluoride
  • the mask pattern may be formed by a photolithography process using a photoresist pattern and may comprise polysilicon and silicon nitride.
  • the melted solder 12 may be supplied into the cavity of the template 11.
  • the melted solder 12 may be injected into the cavity 11 through an injection nozzle and may be solidified into the solder ball 13 in FIG. 5 by a reflow process.
  • the melted solder 12 in the cavity 11 of the template 10 may be solidified into a solid solder when the cavity 11 is completely filled with the melted solder 12 because the temperature of the template 10 may be sufficiently lower than the melting point of the solder.
  • the solid solder in the cavity 11 may be re-melted into a liquid state by heating the template 10 at a reflow temperature and then may be re-solidified into a spherical solder ball 13 due to surface tension.
  • the substrate 20 including the bump pad 25 may be aligned with the template including the solder ball 13 in the cavity of the template 10. Then, the template 10 and the substrate 20 may be heated to a high temperature in such a manner that the solder ball 13 may be transcribed onto the bump pad 25 to thereby form the solder bump on the substrate 20.
  • the wafer and the template may have different TECs of which the difference may be greater than about 30%
  • the original position of the cavity on the template may be accurately determined by using the first and second thermal expansion ratios of the wafer and the template and the original position of the pattern on the wafer. Accordingly, the original position of the cavity may easily be determined from the original position of the pattern irrespective of the difference range between the first and second TECs.
  • no material limitations may be imposed on the selection of the wafer and the template, and thus various materials may be used for the wafer and the template without any limitations on the TECs of the selected materials.
  • an original position of a second pattern on a second substrate prior to thermal expansion of the second substrate may be obtained irrespective of the difference of a TEC between first and second substrates.
  • no material limitations may be imposed on the selection of a wafer and a template, and thus various materials may be used for the wafer and the template without any limitations on the TECs of the selected materials.
  • alignment errors may be minimized when aligning the first and second substrates with each other.
  • the present invention may be applied to an alignment process of two patterns formed on respective two substrates of which the TECs are different from each other at a high temperature. For example, the present invention may be efficiently applied for a process for forming a solder bump on a semiconductor substrate using a template.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Dans un procédé de détermination d’une position de motif sur un substrat, un premier coefficient de dilatation thermique est obtenu par rapport à un premier substrat. Le premier coefficient de dilatation thermique désigne un rapport d’une quantité de dilatation thermique du premier substrat à une variation de la température. Un second coefficient de dilatation thermique est obtenu par rapport à un second substrat. Le second substrat présente un coefficient de dilatation thermique (TEC) différent de celui du premier substrat et le second coefficient de dilatation thermique désigne un rapport d’une quantité de dilatation thermique du second substrat à une variation de la température. Une seconde position d’origine indiquant une position du second motif avant une dilatation thermique est déterminée à l’aide des premier et second coefficients de dilatation thermique et d’une première position d’origine indiquant une position du premier motif avant une dilatation thermique. En conséquence, les premier et second motifs peuvent être alignés dans la même position.
PCT/KR2009/001898 2008-07-25 2009-04-14 Procédé de détermination d’une position de motif et d’une position de cavité, et procédé de formation d’un bossage de soudure l’utilisant WO2010011017A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020080072576A KR101007932B1 (ko) 2008-07-25 2008-07-25 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법
KR10-2008-0072576 2008-07-25

Publications (1)

Publication Number Publication Date
WO2010011017A1 true WO2010011017A1 (fr) 2010-01-28

Family

ID=41570455

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2009/001898 WO2010011017A1 (fr) 2008-07-25 2009-04-14 Procédé de détermination d’une position de motif et d’une position de cavité, et procédé de formation d’un bossage de soudure l’utilisant

Country Status (3)

Country Link
KR (1) KR101007932B1 (fr)
TW (1) TWI396244B (fr)
WO (1) WO2010011017A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010068289A (ko) * 2000-01-04 2001-07-23 박종섭 솔더 조인트 신뢰성을 향상시킨 비지에이 반도체 패키지및 그 제조 방법
KR20050053751A (ko) * 2002-10-11 2005-06-08 테세라, 인코포레이티드 다중-칩 패키지들을 위한 컴포넌트, 방법 및 어셈블리
US20060286716A1 (en) * 2002-12-18 2006-12-21 K-Tec Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4243117B2 (ja) * 2002-08-27 2009-03-25 新光電気工業株式会社 半導体パッケージとその製造方法および半導体装置
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
JP2006049569A (ja) * 2004-08-04 2006-02-16 Sharp Corp スタック型半導体装置パッケージおよびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010068289A (ko) * 2000-01-04 2001-07-23 박종섭 솔더 조인트 신뢰성을 향상시킨 비지에이 반도체 패키지및 그 제조 방법
KR20050053751A (ko) * 2002-10-11 2005-06-08 테세라, 인코포레이티드 다중-칩 패키지들을 위한 컴포넌트, 방법 및 어셈블리
US20060286716A1 (en) * 2002-12-18 2006-12-21 K-Tec Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package

Also Published As

Publication number Publication date
KR101007932B1 (ko) 2011-01-14
TWI396244B (zh) 2013-05-11
KR20100011382A (ko) 2010-02-03
TW201005844A (en) 2010-02-01

Similar Documents

Publication Publication Date Title
US6409073B1 (en) Method for transfering solder to a device and/or testing the device
US7473998B2 (en) Method for forming bump protective collars on a bumped wafer
US8158508B2 (en) Structure and manufacturing method of a chip scale package
US5219117A (en) Method of transferring solder balls onto a semiconductor device
EP0506859B1 (fr) Technique d'interconnexion pour puces electroniques a protuberances utilisant des materiaux polymeres electroconducteurs et des materiaux dielectriques
TW554453B (en) Semiconductor device and method of manufacturing the same
TWI243428B (en) Methods for fabricating pad redistribution layer and copper pad redistribution layer
US20080258305A1 (en) Low fabrication cost, fine pitch and high reliability solder bump
TW571405B (en) Semiconductor device and process for producing the same
Mukai et al. Planar multilevel interconnection technology employing a polyimide
TWI224377B (en) Wafer level chip scale packaging structure and method of fabrication the same
TW201205735A (en) Semiconductor device and method for manufacturing the same
US6312974B1 (en) Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated
JP4739292B2 (ja) イメージセンサのウエハレベルチップスケールパッケージ及びその製造方法
US6890795B1 (en) Wafer level super stretch solder
WO2010011017A1 (fr) Procédé de détermination d’une position de motif et d’une position de cavité, et procédé de formation d’un bossage de soudure l’utilisant
TW200540505A (en) Integrated circuit having a strengthened passivation structure
US20090039140A1 (en) Solder Mold With Venting Channels
TW582077B (en) Flip-chip substrate and the flip-chip bonding process thereof
US20050035453A1 (en) Bump transfer fixture
JPH0357617B2 (fr)
EP0448713B1 (fr) Dispositif a semi-conducteurs
WO2016182395A1 (fr) Conditionnement de capteur et son procédé de fabrication
US6960518B1 (en) Buildup substrate pad pre-solder bump manufacturing
JP2003258014A (ja) 半導体表面上に金属バンプを形成する方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09800498

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09800498

Country of ref document: EP

Kind code of ref document: A1