KR100981041B1 - 반도체 가공방법 - Google Patents

반도체 가공방법 Download PDF

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Publication number
KR100981041B1
KR100981041B1 KR1020080080484A KR20080080484A KR100981041B1 KR 100981041 B1 KR100981041 B1 KR 100981041B1 KR 1020080080484 A KR1020080080484 A KR 1020080080484A KR 20080080484 A KR20080080484 A KR 20080080484A KR 100981041 B1 KR100981041 B1 KR 100981041B1
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KR
South Korea
Prior art keywords
plasma
resist
film
gas
processing
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Expired - Fee Related
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KR1020080080484A
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English (en)
Korean (ko)
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KR20100003148A (ko
Inventor
데츠오 오노
고 사이토
Original Assignee
가부시키가이샤 히다치 하이테크놀로지즈
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Publication of KR20100003148A publication Critical patent/KR20100003148A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
KR1020080080484A 2008-06-30 2008-08-18 반도체 가공방법 Expired - Fee Related KR100981041B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2008-00170629 2008-06-30
JP2008170629A JP5547878B2 (ja) 2008-06-30 2008-06-30 半導体加工方法

Publications (2)

Publication Number Publication Date
KR20100003148A KR20100003148A (ko) 2010-01-07
KR100981041B1 true KR100981041B1 (ko) 2010-09-08

Family

ID=41447974

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080080484A Expired - Fee Related KR100981041B1 (ko) 2008-06-30 2008-08-18 반도체 가공방법

Country Status (4)

Country Link
US (1) US8440513B2 (enExample)
JP (1) JP5547878B2 (enExample)
KR (1) KR100981041B1 (enExample)
TW (1) TWI485771B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5250476B2 (ja) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ ドライエッチング方法
US9318345B2 (en) * 2011-10-05 2016-04-19 Globalfoundries Inc. Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach
JP6002411B2 (ja) * 2012-03-28 2016-10-05 芝浦メカトロニクス株式会社 Ｅｕｖマスク製造方法およびｅｕｖマスク製造装置
US8853081B2 (en) * 2012-12-27 2014-10-07 Intermolecular, Inc. High dose ion-implanted photoresist removal using organic solvent and transition metal mixtures
JP2014212310A (ja) * 2013-04-02 2014-11-13 東京エレクトロン株式会社 半導体デバイスの製造方法及び製造装置
JP7033912B2 (ja) * 2017-12-22 2022-03-11 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置及び基板処理方法
WO2025182676A1 (ja) * 2024-03-01 2025-09-04 東京エレクトロン株式会社 ナノピラーの形成方法及びドライエッチング装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110775A (ja) * 1999-08-05 2001-04-20 Axcelis Technologies Inc フォトレジスト／エッチング後の残留物を取り除くためのプラズマストリッピング処理方法
KR20070078923A (ko) * 2006-01-31 2007-08-03 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3563446B2 (ja) * 1993-07-16 2004-09-08 富士通株式会社 半導体装置の製造方法
JPH1168095A (ja) * 1997-08-11 1999-03-09 Fujitsu Ltd 半導体装置の製造方法
US5962346A (en) * 1997-12-29 1999-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fluorine-doped silicate glass hard mask to improve metal line etching profile
US6593244B1 (en) * 2000-09-11 2003-07-15 Applied Materials Inc. Process for etching conductors at high etch rates
JP4142664B2 (ja) * 2001-03-12 2008-09-03 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6951823B2 (en) * 2001-05-14 2005-10-04 Axcelis Technologies, Inc. Plasma ashing process
US6762130B2 (en) * 2002-05-31 2004-07-13 Texas Instruments Incorporated Method of photolithographically forming extremely narrow transistor gate elements
US20050020856A1 (en) * 2003-07-24 2005-01-27 The Regents Of The University Of Califorinia Process for production of acetyl anhydrides and optionally acetic acid from methane and carbon dioxide
US7799685B2 (en) * 2003-10-13 2010-09-21 Mattson Technology, Inc. System and method for removal of photoresist in transistor fabrication for integrated circuit manufacturing
JP2005268312A (ja) * 2004-03-16 2005-09-29 Semiconductor Leading Edge Technologies Inc レジスト除去方法及びそれを用いて製造した半導体装置
CN102610481B (zh) * 2004-09-01 2016-04-13 朗姆研究公司 用于增加光阻移除率之装置及等离子体灰化方法
US7319074B2 (en) * 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US20070037101A1 (en) * 2005-08-15 2007-02-15 Fujitsu Limited Manufacture method for micro structure
JP4854245B2 (ja) * 2005-09-22 2012-01-18 東京エレクトロン株式会社 半導体装置の製造方法
US7642195B2 (en) * 2005-09-26 2010-01-05 Applied Materials, Inc. Hydrogen treatment to improve photoresist adhesion and rework consistency
JP4598639B2 (ja) * 2005-09-27 2010-12-15 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7381651B2 (en) * 2006-03-22 2008-06-03 Axcelis Technologies, Inc. Processes for monitoring the levels of oxygen and/or nitrogen species in a substantially oxygen and nitrogen-free plasma ashing process
US7691754B2 (en) * 2006-10-18 2010-04-06 United Microelectronics Corp. Method for removing photoresist layer and method of forming opening
US7704888B2 (en) * 2007-01-23 2010-04-27 Globalfoundries Inc. Methods for removing photoresist from semiconductor structures having high-k dielectric material layers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110775A (ja) * 1999-08-05 2001-04-20 Axcelis Technologies Inc フォトレジスト／エッチング後の残留物を取り除くためのプラズマストリッピング処理方法
KR20070078923A (ko) * 2006-01-31 2007-08-03 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법

Also Published As

Publication number Publication date
JP5547878B2 (ja) 2014-07-16
US8440513B2 (en) 2013-05-14
US20090325388A1 (en) 2009-12-31
TWI485771B (zh) 2015-05-21
TW201001535A (en) 2010-01-01
JP2010010573A (ja) 2010-01-14
KR20100003148A (ko) 2010-01-07

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