KR100968461B1 - 메모리 모듈 및 데이터 입출력 시스템 - Google Patents

메모리 모듈 및 데이터 입출력 시스템 Download PDF

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Publication number
KR100968461B1
KR100968461B1 KR1020080124267A KR20080124267A KR100968461B1 KR 100968461 B1 KR100968461 B1 KR 100968461B1 KR 1020080124267 A KR1020080124267 A KR 1020080124267A KR 20080124267 A KR20080124267 A KR 20080124267A KR 100968461 B1 KR100968461 B1 KR 100968461B1
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KR
South Korea
Prior art keywords
data
output
control signal
memory chip
data output
Prior art date
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Expired - Fee Related
Application number
KR1020080124267A
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English (en)
Korean (ko)
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KR20100065759A (ko
Inventor
김경훈
윤상식
Original Assignee
주식회사 하이닉스반도체
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Publication date
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Priority to KR1020080124267A priority Critical patent/KR100968461B1/ko
Priority to US12/483,328 priority patent/US7894231B2/en
Priority to JP2009171515A priority patent/JP2010134904A/ja
Publication of KR20100065759A publication Critical patent/KR20100065759A/ko
Application granted granted Critical
Publication of KR100968461B1 publication Critical patent/KR100968461B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
KR1020080124267A 2008-12-08 2008-12-08 메모리 모듈 및 데이터 입출력 시스템 Expired - Fee Related KR100968461B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020080124267A KR100968461B1 (ko) 2008-12-08 2008-12-08 메모리 모듈 및 데이터 입출력 시스템
US12/483,328 US7894231B2 (en) 2008-12-08 2009-06-12 Memory module and data input/output system
JP2009171515A JP2010134904A (ja) 2008-12-08 2009-07-22 メモリモジュール及びデータ入出力システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080124267A KR100968461B1 (ko) 2008-12-08 2008-12-08 메모리 모듈 및 데이터 입출력 시스템

Publications (2)

Publication Number Publication Date
KR20100065759A KR20100065759A (ko) 2010-06-17
KR100968461B1 true KR100968461B1 (ko) 2010-07-07

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Family Applications (1)

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KR1020080124267A Expired - Fee Related KR100968461B1 (ko) 2008-12-08 2008-12-08 메모리 모듈 및 데이터 입출력 시스템

Country Status (3)

Country Link
US (1) US7894231B2 (enExample)
JP (1) JP2010134904A (enExample)
KR (1) KR100968461B1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100968458B1 (ko) * 2008-10-14 2010-07-07 주식회사 하이닉스반도체 반도체 메모리 장치
JP5710992B2 (ja) 2011-01-28 2015-04-30 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
JP2013114415A (ja) * 2011-11-28 2013-06-10 Elpida Memory Inc メモリモジュール
US9070572B2 (en) 2012-11-15 2015-06-30 Samsung Electronics Co., Ltd. Memory module and memory system
US10901734B2 (en) 2019-03-01 2021-01-26 Micron Technology, Inc. Memory mapping using commands to transfer data and/or perform logic operations

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100842403B1 (ko) 2007-03-08 2008-07-01 삼성전자주식회사 메모리 모듈 및 메모리 모듈 시스템

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
JPH10302470A (ja) 1997-04-28 1998-11-13 Nec Corp 半導体記憶装置
JP3249805B2 (ja) * 2000-01-01 2002-01-21 株式会社日立製作所 半導体装置
US7078793B2 (en) * 2003-08-29 2006-07-18 Infineon Technologies Ag Semiconductor memory module
DE102005053625B4 (de) * 2005-11-10 2007-10-25 Infineon Technologies Ag Speichermodul mit einer Mehrzahl von Speicherbausteinen
US7471538B2 (en) * 2006-03-30 2008-12-30 Micron Technology, Inc. Memory module, system and method of making same
JP5087886B2 (ja) * 2006-08-18 2012-12-05 富士通株式会社 メモリ制御装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100842403B1 (ko) 2007-03-08 2008-07-01 삼성전자주식회사 메모리 모듈 및 메모리 모듈 시스템

Also Published As

Publication number Publication date
JP2010134904A (ja) 2010-06-17
KR20100065759A (ko) 2010-06-17
US20100142244A1 (en) 2010-06-10
US7894231B2 (en) 2011-02-22

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