JP2010134904A - メモリモジュール及びデータ入出力システム - Google Patents

メモリモジュール及びデータ入出力システム Download PDF

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Publication number
JP2010134904A
JP2010134904A JP2009171515A JP2009171515A JP2010134904A JP 2010134904 A JP2010134904 A JP 2010134904A JP 2009171515 A JP2009171515 A JP 2009171515A JP 2009171515 A JP2009171515 A JP 2009171515A JP 2010134904 A JP2010134904 A JP 2010134904A
Authority
JP
Japan
Prior art keywords
data
control signal
memory chip
output
data output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009171515A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010134904A5 (enExample
Inventor
Kyung Hoon Kim
敬 ▲員力▼ 金
Sang-Sic Yoon
相 植 尹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2010134904A publication Critical patent/JP2010134904A/ja
Publication of JP2010134904A5 publication Critical patent/JP2010134904A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2009171515A 2008-12-08 2009-07-22 メモリモジュール及びデータ入出力システム Pending JP2010134904A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080124267A KR100968461B1 (ko) 2008-12-08 2008-12-08 메모리 모듈 및 데이터 입출력 시스템

Publications (2)

Publication Number Publication Date
JP2010134904A true JP2010134904A (ja) 2010-06-17
JP2010134904A5 JP2010134904A5 (enExample) 2012-09-06

Family

ID=42230874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009171515A Pending JP2010134904A (ja) 2008-12-08 2009-07-22 メモリモジュール及びデータ入出力システム

Country Status (3)

Country Link
US (1) US7894231B2 (enExample)
JP (1) JP2010134904A (enExample)
KR (1) KR100968461B1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9378775B2 (en) 2011-01-28 2016-06-28 Ps4 Luxco S.A.R.L. Semiconductor device including plural chips stacked to each other

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100968458B1 (ko) * 2008-10-14 2010-07-07 주식회사 하이닉스반도체 반도체 메모리 장치
JP2013114415A (ja) * 2011-11-28 2013-06-10 Elpida Memory Inc メモリモジュール
US9070572B2 (en) 2012-11-15 2015-06-30 Samsung Electronics Co., Ltd. Memory module and memory system
US10901734B2 (en) 2019-03-01 2021-01-26 Micron Technology, Inc. Memory mapping using commands to transfer data and/or perform logic operations

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349229A (ja) * 2000-01-01 2000-12-15 Hitachi Ltd 半導体装置
JP2008046989A (ja) * 2006-08-18 2008-02-28 Fujitsu Ltd メモリ制御装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
JPH10302470A (ja) 1997-04-28 1998-11-13 Nec Corp 半導体記憶装置
US7078793B2 (en) * 2003-08-29 2006-07-18 Infineon Technologies Ag Semiconductor memory module
DE102005053625B4 (de) * 2005-11-10 2007-10-25 Infineon Technologies Ag Speichermodul mit einer Mehrzahl von Speicherbausteinen
US7471538B2 (en) * 2006-03-30 2008-12-30 Micron Technology, Inc. Memory module, system and method of making same
KR100842403B1 (ko) 2007-03-08 2008-07-01 삼성전자주식회사 메모리 모듈 및 메모리 모듈 시스템

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349229A (ja) * 2000-01-01 2000-12-15 Hitachi Ltd 半導体装置
JP2008046989A (ja) * 2006-08-18 2008-02-28 Fujitsu Ltd メモリ制御装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9378775B2 (en) 2011-01-28 2016-06-28 Ps4 Luxco S.A.R.L. Semiconductor device including plural chips stacked to each other

Also Published As

Publication number Publication date
KR100968461B1 (ko) 2010-07-07
KR20100065759A (ko) 2010-06-17
US20100142244A1 (en) 2010-06-10
US7894231B2 (en) 2011-02-22

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