KR100959604B1 - 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법 - Google Patents

웨이퍼 레벨 반도체 패키지 및 이의 제조 방법 Download PDF

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Publication number
KR100959604B1
KR100959604B1 KR1020080021983A KR20080021983A KR100959604B1 KR 100959604 B1 KR100959604 B1 KR 100959604B1 KR 1020080021983 A KR1020080021983 A KR 1020080021983A KR 20080021983 A KR20080021983 A KR 20080021983A KR 100959604 B1 KR100959604 B1 KR 100959604B1
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KR
South Korea
Prior art keywords
redistribution
semiconductor chips
insulating film
carrier substrate
insulating layer
Prior art date
Application number
KR1020080021983A
Other languages
English (en)
Korean (ko)
Other versions
KR20090096902A (ko
Inventor
서민석
양승택
이승현
김종훈
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080021983A priority Critical patent/KR100959604B1/ko
Priority to US12/261,112 priority patent/US8018043B2/en
Priority to CN200810185288.9A priority patent/CN101533812B/zh
Publication of KR20090096902A publication Critical patent/KR20090096902A/ko
Application granted granted Critical
Publication of KR100959604B1 publication Critical patent/KR100959604B1/ko
Priority to US13/197,249 priority patent/US20110287584A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR1020080021983A 2008-03-10 2008-03-10 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법 KR100959604B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020080021983A KR100959604B1 (ko) 2008-03-10 2008-03-10 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법
US12/261,112 US8018043B2 (en) 2008-03-10 2008-10-30 Semiconductor package having side walls and method for manufacturing the same
CN200810185288.9A CN101533812B (zh) 2008-03-10 2008-12-24 具有侧壁的半导体封装及其制造方法
US13/197,249 US20110287584A1 (en) 2008-03-10 2011-08-03 Semiconductor package having side walls and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080021983A KR100959604B1 (ko) 2008-03-10 2008-03-10 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법

Publications (2)

Publication Number Publication Date
KR20090096902A KR20090096902A (ko) 2009-09-15
KR100959604B1 true KR100959604B1 (ko) 2010-05-27

Family

ID=41104317

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080021983A KR100959604B1 (ko) 2008-03-10 2008-03-10 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법

Country Status (2)

Country Link
KR (1) KR100959604B1 (zh)
CN (1) CN101533812B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101848066B1 (ko) * 2011-08-11 2018-04-11 에스케이하이닉스 주식회사 임베디드 패키지 및 그 제조방법
US20140001622A1 (en) * 2012-06-27 2014-01-02 Infineon Technologies Ag Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages
JP2014072494A (ja) * 2012-10-01 2014-04-21 Toshiba Corp 半導体装置及びその製造方法
US9041207B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Method to increase I/O density and reduce layer counts in BBUL packages
CN104201114A (zh) * 2014-08-26 2014-12-10 江阴长电先进封装有限公司 一种侧壁绝缘保护的芯片封装方法及其封装结构
KR102398663B1 (ko) * 2015-07-09 2022-05-16 삼성전자주식회사 칩 패드, 재배선 테스트 패드 및 재배선 접속 패드를 포함하는 반도체 칩
CN105140191B (zh) * 2015-09-17 2019-03-01 中芯长电半导体（江阴）有限公司 一种封装结构及再分布引线层的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040030560A (ko) * 2002-02-04 2004-04-09 가시오게산키 가부시키가이샤 반도체 장치 및 그 제조방법
JP2004165189A (ja) 2002-11-08 2004-06-10 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
US6791195B2 (en) 2000-04-24 2004-09-14 Nec Electronics Corporation Semiconductor device and manufacturing method of the same
KR100618892B1 (ko) * 2005-04-13 2006-09-01 삼성전자주식회사 와이어 본딩을 통해 팬 아웃 구조를 달성하는 반도체패키지

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
JP3929966B2 (ja) * 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
US7675157B2 (en) * 2006-01-30 2010-03-09 Marvell World Trade Ltd. Thermal enhanced package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791195B2 (en) 2000-04-24 2004-09-14 Nec Electronics Corporation Semiconductor device and manufacturing method of the same
KR20040030560A (ko) * 2002-02-04 2004-04-09 가시오게산키 가부시키가이샤 반도체 장치 및 그 제조방법
JP2004165189A (ja) 2002-11-08 2004-06-10 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
KR100618892B1 (ko) * 2005-04-13 2006-09-01 삼성전자주식회사 와이어 본딩을 통해 팬 아웃 구조를 달성하는 반도체패키지

Also Published As

Publication number Publication date
CN101533812A (zh) 2009-09-16
CN101533812B (zh) 2014-04-09
KR20090096902A (ko) 2009-09-15

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