KR100940951B1 - 밸런싱된 부하 메모리 및 동작 방법 - Google Patents

밸런싱된 부하 메모리 및 동작 방법 Download PDF

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Publication number
KR100940951B1
KR100940951B1 KR1020047021346A KR20047021346A KR100940951B1 KR 100940951 B1 KR100940951 B1 KR 100940951B1 KR 1020047021346 A KR1020047021346 A KR 1020047021346A KR 20047021346 A KR20047021346 A KR 20047021346A KR 100940951 B1 KR100940951 B1 KR 100940951B1
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South Korea
Prior art keywords
array
sub
data
sense amplifier
transistor
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Expired - Fee Related
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KR1020047021346A
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English (en)
Korean (ko)
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KR20050013648A (ko
Inventor
키트라 케이. 서브라마니안
브래들리 제이. 가르니
요셉 제이. 나하스
할버트 에스. 린
토마스 더블유. 안드레
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에버스핀 테크놀러지스, 인크.
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Publication of KR20050013648A publication Critical patent/KR20050013648A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
KR1020047021346A 2002-06-28 2003-04-24 밸런싱된 부하 메모리 및 동작 방법 Expired - Fee Related KR100940951B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/184,720 2002-06-28
US10/184,720 US6711068B2 (en) 2002-06-28 2002-06-28 Balanced load memory and method of operation
PCT/US2003/013007 WO2004003919A1 (en) 2002-06-28 2003-04-24 Balanced load memory and method of operation

Publications (2)

Publication Number Publication Date
KR20050013648A KR20050013648A (ko) 2005-02-04
KR100940951B1 true KR100940951B1 (ko) 2010-02-05

Family

ID=29779429

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020047021346A Expired - Fee Related KR100940951B1 (ko) 2002-06-28 2003-04-24 밸런싱된 부하 메모리 및 동작 방법

Country Status (8)

Country Link
US (1) US6711068B2 (enExample)
EP (1) EP1518243A1 (enExample)
JP (1) JP4368793B2 (enExample)
KR (1) KR100940951B1 (enExample)
CN (1) CN1666289B (enExample)
AU (1) AU2003225175A1 (enExample)
TW (1) TWI303439B (enExample)
WO (1) WO2004003919A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6795336B2 (en) * 2001-12-07 2004-09-21 Hynix Semiconductor Inc. Magnetic random access memory
US6917552B2 (en) * 2002-03-05 2005-07-12 Renesas Technology Corporation Semiconductor device using high-speed sense amplifier
US7251160B2 (en) * 2005-03-16 2007-07-31 Sandisk Corporation Non-volatile memory and method with power-saving read and program-verify operations
US7362604B2 (en) * 2005-07-11 2008-04-22 Sandisk 3D Llc Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements
US7345907B2 (en) * 2005-07-11 2008-03-18 Sandisk 3D Llc Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements
US7321507B2 (en) * 2005-11-21 2008-01-22 Magic Technologies, Inc. Reference cell scheme for MRAM
JP4901204B2 (ja) * 2005-12-13 2012-03-21 株式会社東芝 半導体集積回路装置
CN1988032B (zh) * 2005-12-23 2011-06-22 财团法人工业技术研究院 存储器的负载平衡架构
US20070247939A1 (en) * 2006-04-21 2007-10-25 Nahas Joseph J Mram array with reference cell row and methof of operation
US8279704B2 (en) * 2006-07-31 2012-10-02 Sandisk 3D Llc Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US7542338B2 (en) * 2006-07-31 2009-06-02 Sandisk 3D Llc Method for reading a multi-level passive element memory cell array
US7542337B2 (en) * 2006-07-31 2009-06-02 Sandisk 3D Llc Apparatus for reading a multi-level passive element memory cell array
US7787282B2 (en) * 2008-03-21 2010-08-31 Micron Technology, Inc. Sensing resistance variable memory
JP5100530B2 (ja) * 2008-06-23 2012-12-19 株式会社東芝 抵抗変化型メモリ
US8233309B2 (en) * 2009-10-26 2012-07-31 Sandisk 3D Llc Non-volatile memory array architecture incorporating 1T-1R near 4F2 memory cell
JP5359804B2 (ja) * 2009-11-16 2013-12-04 ソニー株式会社 不揮発性半導体メモリデバイス
US8331166B2 (en) 2011-02-28 2012-12-11 Infineon Techn. AG Method and system for reading from memory cells in a memory device
US8498169B2 (en) 2011-09-02 2013-07-30 Qualcomm Incorporated Code-based differential charging of bit lines of a sense amplifier
US10108377B2 (en) * 2015-11-13 2018-10-23 Western Digital Technologies, Inc. Storage processing unit arrays and methods of use

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764581A (en) * 1997-03-04 1998-06-09 Advanced Micro Devices Inc. Dynamic ram with two-transistor cell
US6269040B1 (en) * 2000-06-26 2001-07-31 International Business Machines Corporation Interconnection network for connecting memory cells to sense amplifiers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713797A (en) 1985-11-25 1987-12-15 Motorola Inc. Current mirror sense amplifier for a non-volatile memory
GB9423032D0 (en) * 1994-11-15 1995-01-04 Sgs Thomson Microelectronics Bit line sensing in a memory array
KR0164391B1 (ko) * 1995-06-29 1999-02-18 김광호 고속동작을 위한 회로 배치 구조를 가지는 반도체 메모리 장치
JP3169858B2 (ja) * 1997-06-20 2001-05-28 日本電気アイシーマイコンシステム株式会社 多値型半導体記憶装置
US6191989B1 (en) 2000-03-07 2001-02-20 International Business Machines Corporation Current sensing amplifier
ITMI20011150A1 (it) * 2001-05-30 2002-11-30 St Microelectronics Srl Multiplatore di colonna per memorie a semiconduttore

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764581A (en) * 1997-03-04 1998-06-09 Advanced Micro Devices Inc. Dynamic ram with two-transistor cell
US6269040B1 (en) * 2000-06-26 2001-07-31 International Business Machines Corporation Interconnection network for connecting memory cells to sense amplifiers

Also Published As

Publication number Publication date
KR20050013648A (ko) 2005-02-04
WO2004003919A1 (en) 2004-01-08
TWI303439B (en) 2008-11-21
CN1666289A (zh) 2005-09-07
EP1518243A1 (en) 2005-03-30
AU2003225175A1 (en) 2004-01-19
TW200409137A (en) 2004-06-01
CN1666289B (zh) 2010-04-28
US6711068B2 (en) 2004-03-23
JP4368793B2 (ja) 2009-11-18
US20040001361A1 (en) 2004-01-01
JP2005531875A (ja) 2005-10-20

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