KR100878734B1 - Simox 웨이퍼의 제조 방법 - Google Patents
Simox 웨이퍼의 제조 방법 Download PDFInfo
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- KR100878734B1 KR100878734B1 KR1020070029763A KR20070029763A KR100878734B1 KR 100878734 B1 KR100878734 B1 KR 100878734B1 KR 1020070029763 A KR1020070029763 A KR 1020070029763A KR 20070029763 A KR20070029763 A KR 20070029763A KR 100878734 B1 KR100878734 B1 KR 100878734B1
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- Prior art keywords
- thickness
- soi film
- soi
- cleaning
- etching
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 48
- 238000005530 etching Methods 0.000 claims abstract description 33
- 238000004140 cleaning Methods 0.000 claims abstract description 32
- 238000000137 annealing Methods 0.000 claims abstract description 30
- 239000001301 oxygen Substances 0.000 claims abstract description 26
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 26
- -1 oxygen ions Chemical class 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 235000012431 wafers Nutrition 0.000 abstract description 25
- 239000010408 film Substances 0.000 description 64
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 18
- 239000000243 solution Substances 0.000 description 14
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000012298 atmosphere Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (6)
- Si 기판의 표면에 산소 이온들을 주입하고 그 후 고온 어닐링 (annealing) 을 수행하는 것에 의해서 SIMOX 웨이퍼를 제조하는 방법으로서,목표 SOI 막 두께보다 5~20nm 만큼 두꺼운 두께를 가진 SOI 막을 사전에 형성하는 단계;고온 어닐링 단계 이후에, 산화막을 분리하고 상기 SOI 막의 두께를 측정하는 단계; 및세정 단계와 별도로 행해지는 에칭 단계에서 상기 SOI 막의 두께의 최종 조정을 수행하는 단계를 포함하는, SIMOX 웨이퍼의 제조 방법.
- Si 기판의 표면에 산소 이온들을 주입하고 그 후 고온 어닐링 (annealing) 을 수행하는 것에 의해서 SIMOX 웨이퍼를 제조하는 방법으로서,목표 SOI 막 두께보다 5~20nm 만큼 두꺼운 두께를 가진 SOI 막을 사전에 형성하는 단계;고온 어닐링 단계 이후에, 산화막을 분리하고 상기 SOI 막의 두께를 측정하는 단계; 및세정 단계와 동시에 행해지는 에칭 단계에서 상기 SOI 막의 두께의 최종 조정을 수행하는 단계를 포함하는, SIMOX 웨이퍼의 제조 방법.
- 제 1 항에 있어서,상기 세정 단계는 배치 (batch) 세정이며,상기 어닐링 단계 직후의 SOI 막 두께가 측정되고, 최적의 에칭 시간 또는 에칭을 포함한 세정 시간이 상기 SOI 막 두께를 조정하기 위해서 매 어닐링 배치마다 설정되는, SIMOX 웨이퍼의 제조 방법.
- 제 1 항에 있어서,상기 세정 단계는 시트-피드 (sheet-feed) 세정이며,상기 어닐링 단계 직후의 SOI 막 두께가 매 웨이퍼마다 측정되고, 최적의 에칭 시간 또는 에칭을 포함한 세정 시간이 상기 SOI 막 두께를 조정하기 위해서 매 웨이퍼마다 설정되는, SIMOX 웨이퍼의 제조 방법.
- 제 1 항에 있어서,상기 에칭 단계에서 사용된 처리 용액은 SC-1 계 용액 또는 HF+O3 계 용액인, SIMOX 웨이퍼의 제조 방법.
- 제 2 항에 있어서,상기 에칭 단계와 동시에 수행되는 상기 세정 단계에서 사용된 처리 용액은 SC-1 계 용액 또는 HF+O3 계 용액인, SIMOX 웨이퍼의 제조 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006085429A JP2007266059A (ja) | 2006-03-27 | 2006-03-27 | Simoxウェーハの製造方法 |
JPJP-P-2006-00085429 | 2006-03-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20070096969A KR20070096969A (ko) | 2007-10-02 |
KR100878734B1 true KR100878734B1 (ko) | 2009-01-14 |
Family
ID=38197591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070029763A KR100878734B1 (ko) | 2006-03-27 | 2007-03-27 | Simox 웨이퍼의 제조 방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20070224778A1 (ko) |
EP (1) | EP1840956A1 (ko) |
JP (1) | JP2007266059A (ko) |
KR (1) | KR100878734B1 (ko) |
SG (2) | SG155985A1 (ko) |
TW (1) | TW200802695A (ko) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5374805B2 (ja) * | 2006-03-27 | 2013-12-25 | 株式会社Sumco | Simoxウェーハの製造方法 |
JP5320954B2 (ja) * | 2008-10-03 | 2013-10-23 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP2010153809A (ja) * | 2008-11-26 | 2010-07-08 | Sumco Corp | シリコンウェーハの表面に形成された所定の膜厚を有する層の膜厚分布を均一化する処理方法及びシリコンウェーハの厚み分布を均一化する処理方法 |
JP6152829B2 (ja) * | 2014-06-17 | 2017-06-28 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP6086105B2 (ja) | 2014-09-24 | 2017-03-01 | 信越半導体株式会社 | Soiウェーハの製造方法 |
CN104701225B (zh) * | 2015-03-30 | 2017-08-22 | 上海华力微电子有限公司 | 一种基于模型的离子析出缺陷改善方法 |
US10658474B2 (en) | 2018-08-14 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming thin semiconductor-on-insulator (SOI) substrates |
US20230154761A1 (en) | 2020-05-26 | 2023-05-18 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi wafer |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040100954A (ko) * | 2003-05-21 | 2004-12-02 | 캐논 가부시끼가이샤 | 기판제조방법 및 기판처리장치 |
Family Cites Families (8)
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---|---|---|---|---|
JP2752799B2 (ja) * | 1991-03-27 | 1998-05-18 | 三菱マテリアル株式会社 | Soi基板の製造方法 |
US5930643A (en) * | 1997-12-22 | 1999-07-27 | International Business Machines Corporation | Defect induced buried oxide (DIBOX) for throughput SOI |
JP3762144B2 (ja) * | 1998-06-18 | 2006-04-05 | キヤノン株式会社 | Soi基板の作製方法 |
JP2000082679A (ja) * | 1998-07-08 | 2000-03-21 | Canon Inc | 半導体基板とその作製方法 |
JP2003289051A (ja) * | 1998-09-10 | 2003-10-10 | Nippon Steel Corp | Simox基板およびその製造方法 |
JP2001168308A (ja) * | 1999-09-30 | 2001-06-22 | Canon Inc | シリコン薄膜の製造方法、soi基板の作製方法及び半導体装置 |
WO2001067510A1 (en) * | 2000-03-10 | 2001-09-13 | Nippon Steel Corporation | Simox substrate and method for production thereof |
JP2004349493A (ja) * | 2003-05-22 | 2004-12-09 | Canon Inc | 膜厚調整装置及びsoi基板の製造方法 |
-
2006
- 2006-03-27 JP JP2006085429A patent/JP2007266059A/ja active Pending
-
2007
- 2007-03-27 US US11/729,219 patent/US20070224778A1/en not_active Abandoned
- 2007-03-27 SG SG200906423-9A patent/SG155985A1/en unknown
- 2007-03-27 SG SG200702276-7A patent/SG136101A1/en unknown
- 2007-03-27 TW TW096110635A patent/TW200802695A/zh unknown
- 2007-03-27 KR KR1020070029763A patent/KR100878734B1/ko active IP Right Grant
- 2007-03-27 EP EP07006288A patent/EP1840956A1/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040100954A (ko) * | 2003-05-21 | 2004-12-02 | 캐논 가부시끼가이샤 | 기판제조방법 및 기판처리장치 |
Also Published As
Publication number | Publication date |
---|---|
KR20070096969A (ko) | 2007-10-02 |
SG136101A1 (en) | 2007-10-29 |
JP2007266059A (ja) | 2007-10-11 |
TW200802695A (en) | 2008-01-01 |
EP1840956A1 (en) | 2007-10-03 |
US20070224778A1 (en) | 2007-09-27 |
SG155985A1 (en) | 2009-10-29 |
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