KR100865473B1 - 반도체 패키지 제조용 몰딩 장치 - Google Patents
반도체 패키지 제조용 몰딩 장치 Download PDFInfo
- Publication number
- KR100865473B1 KR100865473B1 KR1020070076128A KR20070076128A KR100865473B1 KR 100865473 B1 KR100865473 B1 KR 100865473B1 KR 1020070076128 A KR1020070076128 A KR 1020070076128A KR 20070076128 A KR20070076128 A KR 20070076128A KR 100865473 B1 KR100865473 B1 KR 100865473B1
- Authority
- KR
- South Korea
- Prior art keywords
- chase
- cavity
- package
- molding apparatus
- semiconductor package
- Prior art date
Links
- 238000000465 moulding Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 25
- 239000011347 resin Substances 0.000 description 14
- 229920005989 resin Polymers 0.000 description 14
- 238000011010 flushing procedure Methods 0.000 description 4
- 230000004927 fusion Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
Claims (7)
- 다수의 제1캐비티가 저면에 등간격을 이루며 형성된 상부 체이스와;상기 상부 체이스의 제1캐비티와 상하로 일치되는 위치에 다수의 제2캐비티가 관통 형성된 중간 체이스와;상면이 평평한 면으로 형성된 하부 체이스와;상기 하부 체이스의 상면에 깔리되, 그 위쪽에 배치되는 중간 체이스의 제2캐비티를 가리면서 깔리게 되는 필름;을 포함하여 구성된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
- 청구항 1에 있어서, 상기 제1캐비티는 상부 체이스의 저면에서 그 양쪽에 스트립 단위를 이루며 대칭 배열된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
- 청구항 1 또는 청구항 2에 있어서, 상기 상부 체이스의 중간부분에는 그 길이방향을 따라 등간격을 이루며 제1클램핑용 홀이 관통 형성된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
- 청구항 1에 있어서, 상기 제2캐비티는 중간 체이스의 전체 면적에서 그 양쪽에 스트립 단위를 이루며 대칭 배열된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
- 청구항 1 또는 청구항 4에 있어서, 상기 중간 체이스의 중간부분에는 그 길이방향을 따라 등간격을 이루며 제2클램핑용 홀이 관통 형성된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
- 청구항 1에 있어서, 상기 하부 체이스에는 상기 필름을 흡착 고정시킬 수 있는 복수개의 진공홀이 더 형성된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
- 청구항 1 또는 청구항 6에 있어서, 상기 하부 체이스의 중간부분에는 그 길이방향을 따라 등간격을 이루며 제3클램핑용 홀이 관통 형성된 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장치.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070076128A KR100865473B1 (ko) | 2007-07-30 | 2007-07-30 | 반도체 패키지 제조용 몰딩 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020070076128A KR100865473B1 (ko) | 2007-07-30 | 2007-07-30 | 반도체 패키지 제조용 몰딩 장치 |
Publications (1)
Publication Number | Publication Date |
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KR100865473B1 true KR100865473B1 (ko) | 2008-10-28 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020070076128A KR100865473B1 (ko) | 2007-07-30 | 2007-07-30 | 반도체 패키지 제조용 몰딩 장치 |
Country Status (1)
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KR (1) | KR100865473B1 (ko) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000252310A (ja) | 1999-03-03 | 2000-09-14 | Hitachi Ltd | モールド方法および装置ならびにそれを用いた半導体装置の製造方法 |
KR20010019852A (ko) * | 1999-08-31 | 2001-03-15 | 윤종용 | 반도체 칩 몰딩 설비 |
JP2002113752A (ja) | 2000-10-06 | 2002-04-16 | Nec Semiconductors Kyushu Ltd | 樹脂封止金型 |
KR20050017207A (ko) * | 2003-08-11 | 2005-02-22 | 삼성전자주식회사 | 자동 몰딩 장치 |
-
2007
- 2007-07-30 KR KR1020070076128A patent/KR100865473B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000252310A (ja) | 1999-03-03 | 2000-09-14 | Hitachi Ltd | モールド方法および装置ならびにそれを用いた半導体装置の製造方法 |
KR20010019852A (ko) * | 1999-08-31 | 2001-03-15 | 윤종용 | 반도체 칩 몰딩 설비 |
JP2002113752A (ja) | 2000-10-06 | 2002-04-16 | Nec Semiconductors Kyushu Ltd | 樹脂封止金型 |
KR20050017207A (ko) * | 2003-08-11 | 2005-02-22 | 삼성전자주식회사 | 자동 몰딩 장치 |
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