KR100769557B1 - 데이터 처리 시스템 및 데이터 처리 유닛 - Google Patents

데이터 처리 시스템 및 데이터 처리 유닛 Download PDF

Info

Publication number
KR100769557B1
KR100769557B1 KR1020017009221A KR20017009221A KR100769557B1 KR 100769557 B1 KR100769557 B1 KR 100769557B1 KR 1020017009221 A KR1020017009221 A KR 1020017009221A KR 20017009221 A KR20017009221 A KR 20017009221A KR 100769557 B1 KR100769557 B1 KR 100769557B1
Authority
KR
South Korea
Prior art keywords
data processing
processing unit
memory
power mode
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020017009221A
Other languages
English (en)
Korean (ko)
Other versions
KR20020007294A (ko
Inventor
에몬스마르틴제이엘
Original Assignee
엔엑스피 비 브이
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엔엑스피 비 브이 filed Critical 엔엑스피 비 브이
Publication of KR20020007294A publication Critical patent/KR20020007294A/ko
Application granted granted Critical
Publication of KR100769557B1 publication Critical patent/KR100769557B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3265Power saving in display device
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3275Power saving in memory, e.g. RAM, cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1028Power efficiency
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/021Power management, e.g. power saving
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Power Sources (AREA)
KR1020017009221A 1999-11-24 2000-11-15 데이터 처리 시스템 및 데이터 처리 유닛 Expired - Fee Related KR100769557B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99203936 1999-11-24
EP99203936.2 1999-11-24

Publications (2)

Publication Number Publication Date
KR20020007294A KR20020007294A (ko) 2002-01-26
KR100769557B1 true KR100769557B1 (ko) 2007-10-23

Family

ID=8240902

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017009221A Expired - Fee Related KR100769557B1 (ko) 1999-11-24 2000-11-15 데이터 처리 시스템 및 데이터 처리 유닛

Country Status (6)

Country Link
US (1) US6963987B1 (enExample)
EP (1) EP1157370B1 (enExample)
JP (1) JP2003515831A (enExample)
KR (1) KR100769557B1 (enExample)
CN (1) CN1188795C (enExample)
WO (1) WO2001039164A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7230933B2 (en) * 2002-04-17 2007-06-12 Microsoft Corporation Reducing idle power consumption in a networked battery operated device
JP4180834B2 (ja) 2002-05-01 2008-11-12 富士通株式会社 情報処理装置および情報処理プログラム
US7457970B2 (en) * 2002-10-11 2008-11-25 Koninklijke Philips Electronics N.V. VLIW processor with power saving
TWI242970B (en) * 2004-04-02 2005-11-01 Htc Corp Frame refreshing method and handheld electronic device using the method
DE102005016830A1 (de) * 2004-04-14 2005-11-03 Denso Corp., Kariya Halbleitervorrichtung und Verfahren zu ihrer Herstellung
EP1626328A1 (en) * 2004-08-13 2006-02-15 Dialog Semiconductor GmbH Power saving during idle loop
EP1640966B1 (en) * 2004-09-23 2012-09-19 HTC Corporation Frame refresh method and circuit
US7222253B2 (en) * 2004-12-28 2007-05-22 Intel Corporation Dynamic power control for reducing voltage level of graphics controller component of memory controller based on its degree of idleness
US7373537B2 (en) * 2005-06-28 2008-05-13 Intel Corporation Response to wake event while a system is in reduced power consumption state
US7873788B1 (en) 2005-11-15 2011-01-18 Oracle America, Inc. Re-fetching cache memory having coherent re-fetching
US7934054B1 (en) 2005-11-15 2011-04-26 Oracle America, Inc. Re-fetching cache memory enabling alternative operational modes
US7516274B2 (en) 2005-11-15 2009-04-07 Sun Microsystems, Inc. Power conservation via DRAM access reduction
US7958312B2 (en) 2005-11-15 2011-06-07 Oracle America, Inc. Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
EP1958071B1 (en) * 2005-11-15 2012-03-07 Oracle America, Inc. Power conservation via dram access
CN101356511B (zh) * 2005-11-15 2012-01-11 太阳微系统有限公司 通过dram存取的功率转换
US7899990B2 (en) 2005-11-15 2011-03-01 Oracle America, Inc. Power conservation via DRAM access
US7536511B2 (en) * 2006-07-07 2009-05-19 Advanced Micro Devices, Inc. CPU mode-based cache allocation for image data
KR101330121B1 (ko) 2006-10-30 2013-11-26 삼성전자주식회사 컴퓨터시스템 및 그 제어방법
US8041848B2 (en) 2008-08-04 2011-10-18 Apple Inc. Media processing method and device
US9128842B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Apparatus and method for reducing the flushing time of a cache

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5809314A (en) * 1994-12-23 1998-09-15 Intel Corporation Method of monitoring system bus traffic by a CPU operating with reduced power

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405318A3 (en) * 1989-06-20 1991-11-27 Nec Corporation Microprocessor having cash bypass signal terminal
GB2260631B (en) * 1991-10-17 1995-06-28 Intel Corp Microprocessor 2X core design
US5450549A (en) * 1992-04-09 1995-09-12 International Business Machines Corporation Multi-channel image array buffer and switching network
KR940004434A (ko) * 1992-08-25 1994-03-15 윌리엄 이. 힐러 스마트 다이나믹 랜덤 억세스 메모리 및 그 처리방법
US5638530A (en) * 1993-04-20 1997-06-10 Texas Instruments Incorporated Direct memory access scheme using memory with an integrated processor having communication with external devices
WO1995015528A1 (en) * 1993-11-30 1995-06-08 Vlsi Technology, Inc. A reallocatable memory subsystem enabling transparent transfer of memory function during upgrade
US5632038A (en) * 1994-02-22 1997-05-20 Dell Usa, L.P. Secondary cache system for portable computer
FI100280B (fi) * 1994-10-07 1997-10-31 Nokia Mobile Phones Ltd Menetelmä tehonkulutuksen minimoimiseksi tietokonelaitteessa
US5530932A (en) * 1994-12-23 1996-06-25 Intel Corporation Cache coherent multiprocessing computer system with reduced power operating features
US5768628A (en) * 1995-04-14 1998-06-16 Nvidia Corporation Method for providing high quality audio by storing wave tables in system memory and having a DMA controller on the sound card for transferring the wave tables
US5845139A (en) * 1995-06-07 1998-12-01 Advanced Micro Devices, Inc. System for providing a host computer with access to a memory on a PCMCIA card in a power down mode
US5963721A (en) * 1995-12-29 1999-10-05 Texas Instruments Incorporated Microprocessor system with capability for asynchronous bus transactions
US5907330A (en) * 1996-12-18 1999-05-25 Intel Corporation Reducing power consumption and bus bandwidth requirements in cellular phones and PDAS by using a compressed display cache
EP0855718A1 (en) * 1997-01-28 1998-07-29 Hewlett-Packard Company Memory low power mode control
US6185704B1 (en) * 1997-04-11 2001-02-06 Texas Instruments Incorporated System signaling schemes for processor and memory module
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
US6052133A (en) 1997-06-27 2000-04-18 S3 Incorporated Multi-function controller and method for a computer graphics display system
JPH11161385A (ja) * 1997-11-28 1999-06-18 Toshiba Corp コンピュータシステムおよびそのシステムステート制御方法
US6134609A (en) * 1998-03-31 2000-10-17 Micron Electronics, Inc. Method for using computer system memory as a modem data buffer by transferring modem I/O data directly to system controller and transferring corresponding system controller data directly to main memory
US6105141A (en) * 1998-06-04 2000-08-15 Apple Computer, Inc. Method and apparatus for power management of an external cache of a computer system
US6347294B1 (en) * 1998-09-22 2002-02-12 International Business Machines Corporation Upgradeable highly integrated embedded CPU system
US6381636B1 (en) * 1999-03-10 2002-04-30 International Business Machines Corporation Data processing system and method for permitting a server to remotely access a powered-off client computer system's asset information
US6523128B1 (en) * 1999-08-31 2003-02-18 Intel Corporation Controlling power for a sleeping state of a computer to prevent overloading of the stand-by power rails by selectively asserting a control signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5809314A (en) * 1994-12-23 1998-09-15 Intel Corporation Method of monitoring system bus traffic by a CPU operating with reduced power

Also Published As

Publication number Publication date
EP1157370A1 (en) 2001-11-28
CN1188795C (zh) 2005-02-09
EP1157370B1 (en) 2014-09-03
WO2001039164A1 (en) 2001-05-31
US6963987B1 (en) 2005-11-08
JP2003515831A (ja) 2003-05-07
CN1344403A (zh) 2002-04-10
KR20020007294A (ko) 2002-01-26

Similar Documents

Publication Publication Date Title
KR100769557B1 (ko) 데이터 처리 시스템 및 데이터 처리 유닛
US6631474B1 (en) System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching
KR100326277B1 (ko) 컴퓨터시스템에있어전력소모를독립적으로감소시키는방법
US7120806B1 (en) Method for setting a power operating mode transition interval of a disk drive in a mobile device based on application category
US10539997B2 (en) Ultra-low-power design memory power reduction scheme
EP0871178A2 (en) Integrated circuit having standby control for memory
US20080313482A1 (en) Power Partitioning Memory Banks
KR20110038036A (ko) 슬리프 프로세서
US5515539A (en) Apparatus and method for reducing power consumption by peripheral devices after downloading a program therefrom
JPH10254587A (ja) コンピュータシステム
EP1510908B1 (en) Processor resource power management
JP2004046324A (ja) 待機モード付情報処理装置およびその待機モード開始方法と待機モード解除方法
JP2004127040A (ja) 情報処理装置、制御方法、プログラム、及び記録媒体
US12013780B2 (en) Multi-partition memory sharing with multiple components
US6851012B2 (en) Information processing system, information processing method and readable-by-computer recording medium
US20230004400A1 (en) System and method for providing system level sleep state power savings
JP2001043098A (ja) オペレーティングシステムおよび仮想計算機システム
US6212609B1 (en) Alternate access mechanism for saving and restoring state of read-only register
WO2005069148A2 (en) Memory management method and related system
KR100727493B1 (ko) 휴대용 디지털 오디오/비디오 재생 장치
CN113986001B (zh) 芯片及控制方法
JPH07160574A (ja) 情報処理装置
US20200319896A1 (en) Dual wakeup interrupt controllers
JPH0793061A (ja) 情報処理装置
CN120762520B (zh) 一种上下电控制系统、方法及存储介质

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
AMND Amendment
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

AMND Amendment
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

St.27 status event code: A-3-3-V10-V11-apl-PJ0201

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

AMND Amendment
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PB0901 Examination by re-examination before a trial

St.27 status event code: A-6-3-E10-E12-rex-PB0901

J501 Disposition of invalidation of trial
PJ0501 Disposition of invalidation of trial

St.27 status event code: A-3-3-V10-V13-apl-PJ0501

B701 Decision to grant
PB0701 Decision of registration after re-examination before a trial

St.27 status event code: A-3-4-F10-F13-rex-PB0701

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

G170 Re-publication after modification of scope of protection [patent]
PG1701 Publication of correction

St.27 status event code: A-5-5-P10-P19-oth-PG1701

Patent document republication publication date: 20080416

Republication note text: Request for Correction Notice (Document Request)

Gazette number: 1007695570000

Gazette reference publication date: 20071023

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20121008

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20131004

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20141009

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20151018

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20151018

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000