KR100747127B1 - 경로 예측 실패시 조회를 지시하도록 비예측 경로들로부터부분적인 태그들을 제공하는 캐쉬 - Google Patents
경로 예측 실패시 조회를 지시하도록 비예측 경로들로부터부분적인 태그들을 제공하는 캐쉬 Download PDFInfo
- Publication number
- KR100747127B1 KR100747127B1 KR1020027008672A KR20027008672A KR100747127B1 KR 100747127 B1 KR100747127 B1 KR 100747127B1 KR 1020027008672 A KR1020027008672 A KR 1020027008672A KR 20027008672 A KR20027008672 A KR 20027008672A KR 100747127 B1 KR100747127 B1 KR 100747127B1
- Authority
- KR
- South Korea
- Prior art keywords
- path
- tag
- address
- partial
- hit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
- G06F9/3832—Value prediction for operands; operand history buffers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/608—Details relating to cache mapping
- G06F2212/6082—Way prediction in set-associative cache
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/476,577 US6687789B1 (en) | 2000-01-03 | 2000-01-03 | Cache which provides partial tags from non-predicted ways to direct search if way prediction misses |
| US09/476,577 | 2000-01-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020067596A KR20020067596A (ko) | 2002-08-22 |
| KR100747127B1 true KR100747127B1 (ko) | 2007-08-09 |
Family
ID=23892412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020027008672A Expired - Fee Related KR100747127B1 (ko) | 2000-01-03 | 2000-08-08 | 경로 예측 실패시 조회를 지시하도록 비예측 경로들로부터부분적인 태그들을 제공하는 캐쉬 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6687789B1 (enExample) |
| EP (1) | EP1244970B1 (enExample) |
| JP (1) | JP2003519835A (enExample) |
| KR (1) | KR100747127B1 (enExample) |
| CN (1) | CN1208726C (enExample) |
| DE (1) | DE60003235T2 (enExample) |
| WO (1) | WO2001050272A1 (enExample) |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4027620B2 (ja) * | 2001-06-20 | 2007-12-26 | 富士通株式会社 | 分岐予測装置、プロセッサ、及び分岐予測方法 |
| US6944713B2 (en) * | 2002-06-18 | 2005-09-13 | Intel Corporation | Low power set associative cache |
| US20040054867A1 (en) * | 2002-09-13 | 2004-03-18 | Paulus Stravers | Translation lookaside buffer |
| US6973557B2 (en) * | 2003-02-04 | 2005-12-06 | Sun Microsystems, Inc. | Apparatus and method for dual access to a banked and pipelined data cache memory unit |
| US20040181626A1 (en) * | 2003-03-13 | 2004-09-16 | Pickett James K. | Partial linearly tagged cache memory system |
| TWI246658B (en) * | 2003-04-25 | 2006-01-01 | Ip First Llc | Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status |
| US20040243767A1 (en) * | 2003-06-02 | 2004-12-02 | Cierniak Michal J. | Method and apparatus for prefetching based upon type identifier tags |
| US7117290B2 (en) * | 2003-09-03 | 2006-10-03 | Advanced Micro Devices, Inc. | MicroTLB and micro tag for reducing power in a processor |
| US20050050278A1 (en) * | 2003-09-03 | 2005-03-03 | Advanced Micro Devices, Inc. | Low power way-predicted cache |
| US7085894B2 (en) * | 2003-09-11 | 2006-08-01 | International Business Machines Corporation | Selectively accepting cache content |
| US6961276B2 (en) * | 2003-09-17 | 2005-11-01 | International Business Machines Corporation | Random access memory having an adaptable latency |
| US7669009B2 (en) * | 2004-09-23 | 2010-02-23 | Intel Corporation | Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches |
| KR100688503B1 (ko) * | 2004-11-02 | 2007-03-02 | 삼성전자주식회사 | 브랜치 목적 어드레스를 이용하여 캐쉬 웨이를 예측하는프로세서 및 그 방법 |
| US7707387B2 (en) | 2005-06-01 | 2010-04-27 | Microsoft Corporation | Conditional execution via content addressable memory and parallel computing execution model |
| US7793040B2 (en) * | 2005-06-01 | 2010-09-07 | Microsoft Corporation | Content addressable memory architecture |
| US20060277352A1 (en) * | 2005-06-07 | 2006-12-07 | Fong Pong | Method and system for supporting large caches with split and canonicalization tags |
| US20060274787A1 (en) * | 2005-06-07 | 2006-12-07 | Fong Pong | Adaptive cache design for MPT/MTT tables and TCP context |
| US9946547B2 (en) | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
| US7594079B2 (en) * | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
| JP5326314B2 (ja) | 2008-03-21 | 2013-10-30 | 富士通株式会社 | プロセサおよび情報処理装置 |
| US20100332762A1 (en) * | 2009-06-30 | 2010-12-30 | Moga Adrian C | Directory cache allocation based on snoop response information |
| US8904111B2 (en) | 2009-10-20 | 2014-12-02 | The University Of Electro-Communications | Cache memory with CAM and SRAM sub-tags and generation control |
| US8392665B2 (en) | 2010-09-25 | 2013-03-05 | Intel Corporation | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines |
| CN102193875B (zh) * | 2011-04-26 | 2013-08-14 | 北京工业大学 | 多核下基于Cache划分的自适应路预测算法 |
| US20120297256A1 (en) * | 2011-05-20 | 2012-11-22 | Qualcomm Incorporated | Large Ram Cache |
| US8458447B2 (en) * | 2011-06-17 | 2013-06-04 | Freescale Semiconductor, Inc. | Branch target buffer addressing in a data processor |
| US9460016B2 (en) | 2014-06-16 | 2016-10-04 | Analog Devices Global Hamilton | Cache way prediction |
| KR102354990B1 (ko) * | 2014-09-17 | 2022-01-24 | 삼성전자주식회사 | 캐시 메모리 시스템 및 그 동작방법 |
| US9846648B2 (en) | 2015-05-11 | 2017-12-19 | Intel Corporation | Create page locality in cache controller cache allocation |
| GB2553102B (en) * | 2016-08-19 | 2020-05-20 | Advanced Risc Mach Ltd | A memory unit and method of operation of a memory unit to handle operation requests |
| US10324850B2 (en) | 2016-11-11 | 2019-06-18 | Microsoft Technology Licensing, Llc | Serial lookup of tag ways |
| GB2560336B (en) * | 2017-03-07 | 2020-05-06 | Imagination Tech Ltd | Address generators for verifying integrated circuit hardware designs for cache memory |
| US10565122B2 (en) | 2017-05-30 | 2020-02-18 | Microsoft Technology Licensing, Llc | Serial tag lookup with way-prediction |
| US10545875B2 (en) | 2017-12-27 | 2020-01-28 | Advanced Micro Devices, Inc. | Tag accelerator for low latency DRAM cache |
| US11507174B2 (en) | 2020-02-25 | 2022-11-22 | Qualcomm Incorporated | System physical address size aware cache memory |
| CN111988444B (zh) * | 2020-08-19 | 2022-10-18 | 成都安可信电子股份有限公司 | 一种同步总线快速搜索终端地址搜索方法 |
| US11928472B2 (en) | 2020-09-26 | 2024-03-12 | Intel Corporation | Branch prefetch mechanisms for mitigating frontend branch resteers |
| CN114691542A (zh) * | 2020-12-25 | 2022-07-01 | 瑞昱半导体股份有限公司 | 数据处理装置与其数据存取电路 |
| US12182317B2 (en) | 2021-02-13 | 2024-12-31 | Intel Corporation | Region-based deterministic memory safety |
| US11593001B1 (en) * | 2021-08-02 | 2023-02-28 | Nvidia Corporation | Using per memory bank load caches for reducing power use in a system on a chip |
| US12235791B2 (en) | 2021-08-23 | 2025-02-25 | Intel Corporation | Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0675443A1 (en) * | 1994-03-30 | 1995-10-04 | Digital Equipment Corporation | Apparatus and method for accessing direct mapped cache |
| JPH07334423A (ja) * | 1994-06-07 | 1995-12-22 | Hitachi Ltd | セットアソシアティブ方式のメモリ装置 |
| WO1998020421A1 (en) * | 1996-11-04 | 1998-05-14 | Advanced Micro Devices, Inc. | A way prediction structure |
| US5848428A (en) | 1996-12-19 | 1998-12-08 | Compaq Computer Corporation | Sense amplifier decoding in a memory device to reduce power consumption |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62293596A (ja) * | 1986-06-12 | 1987-12-21 | Matsushita Electric Ind Co Ltd | 連想記憶装置 |
| US4914582A (en) | 1986-06-27 | 1990-04-03 | Hewlett-Packard Company | Cache tag lookaside |
| JPS63163939A (ja) * | 1986-12-26 | 1988-07-07 | Nippon Telegr & Teleph Corp <Ntt> | キヤツシユメモリの制御方法 |
| JPH02156352A (ja) * | 1988-12-09 | 1990-06-15 | Hitachi Ltd | キャッシュメモリ |
| US5235697A (en) | 1990-06-29 | 1993-08-10 | Digital Equipment | Set prediction cache memory system using bits of the main memory address |
| JPH05120135A (ja) * | 1991-10-25 | 1993-05-18 | Oki Electric Ind Co Ltd | キヤツシユ制御方式 |
| US5418922A (en) | 1992-04-30 | 1995-05-23 | International Business Machines Corporation | History table for set prediction for accessing a set associative cache |
| JPH0721785A (ja) * | 1993-06-29 | 1995-01-24 | Kawasaki Steel Corp | 半導体メモリ |
| US5671444A (en) | 1994-02-28 | 1997-09-23 | Intel Corporaiton | Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers |
| US5732242A (en) * | 1995-03-24 | 1998-03-24 | Silicon Graphics, Inc. | Consistently specifying way destinations through prefetching hints |
| JPH08263370A (ja) * | 1995-03-27 | 1996-10-11 | Toshiba Microelectron Corp | キャッシュメモリシステム |
| US5845323A (en) * | 1995-08-31 | 1998-12-01 | Advanced Micro Devices, Inc. | Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time |
| US5893146A (en) | 1995-08-31 | 1999-04-06 | Advanced Micro Design, Inc. | Cache structure having a reduced tag comparison to enable data transfer from said cache |
| US5752069A (en) | 1995-08-31 | 1998-05-12 | Advanced Micro Devices, Inc. | Superscalar microprocessor employing away prediction structure |
| US5802594A (en) | 1995-09-06 | 1998-09-01 | Intel Corporation | Single phase pseudo-static instruction translation look-aside buffer |
| JPH1139216A (ja) * | 1997-07-24 | 1999-02-12 | Hitachi Ltd | 半導体記憶装置及びキャッシュメモリシステム |
| US5956746A (en) * | 1997-08-13 | 1999-09-21 | Intel Corporation | Computer system having tag information in a processor and cache memory |
| US6016545A (en) | 1997-12-16 | 2000-01-18 | Advanced Micro Devices, Inc. | Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor |
-
2000
- 2000-01-03 US US09/476,577 patent/US6687789B1/en not_active Expired - Lifetime
- 2000-08-08 KR KR1020027008672A patent/KR100747127B1/ko not_active Expired - Fee Related
- 2000-08-08 DE DE60003235T patent/DE60003235T2/de not_active Expired - Lifetime
- 2000-08-08 WO PCT/US2000/021756 patent/WO2001050272A1/en not_active Ceased
- 2000-08-08 CN CNB008180385A patent/CN1208726C/zh not_active Expired - Lifetime
- 2000-08-08 EP EP00951019A patent/EP1244970B1/en not_active Expired - Lifetime
- 2000-08-08 JP JP2001550564A patent/JP2003519835A/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0675443A1 (en) * | 1994-03-30 | 1995-10-04 | Digital Equipment Corporation | Apparatus and method for accessing direct mapped cache |
| JPH07334423A (ja) * | 1994-06-07 | 1995-12-22 | Hitachi Ltd | セットアソシアティブ方式のメモリ装置 |
| WO1998020421A1 (en) * | 1996-11-04 | 1998-05-14 | Advanced Micro Devices, Inc. | A way prediction structure |
| US5848428A (en) | 1996-12-19 | 1998-12-08 | Compaq Computer Corporation | Sense amplifier decoding in a memory device to reduce power consumption |
Non-Patent Citations (1)
| Title |
|---|
| KESSLER R E et al. : "inexpensive implementations of set-associativity", computer architecture news, US, association for computing machinery, vol.17, no.3, 1 June 1989, pp.131-139 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003519835A (ja) | 2003-06-24 |
| EP1244970B1 (en) | 2003-06-04 |
| CN1415092A (zh) | 2003-04-30 |
| EP1244970A1 (en) | 2002-10-02 |
| US6687789B1 (en) | 2004-02-03 |
| DE60003235T2 (de) | 2004-04-08 |
| WO2001050272A1 (en) | 2001-07-12 |
| DE60003235D1 (de) | 2003-07-10 |
| CN1208726C (zh) | 2005-06-29 |
| KR20020067596A (ko) | 2002-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100747127B1 (ko) | 경로 예측 실패시 조회를 지시하도록 비예측 경로들로부터부분적인 태그들을 제공하는 캐쉬 | |
| US6502185B1 (en) | Pipeline elements which verify predecode information | |
| US8458408B2 (en) | Cache directed sequential prefetch | |
| US5918245A (en) | Microprocessor having a cache memory system using multi-level cache set prediction | |
| US7117290B2 (en) | MicroTLB and micro tag for reducing power in a processor | |
| US5793941A (en) | On-chip primary cache testing circuit and test method | |
| JP3907809B2 (ja) | 複合分岐予測およびキャッシュ先取りをするマイクロプロセッサ | |
| KR100708010B1 (ko) | 인덱스와 선택적 경로 정합에 기반하여 데이터를 포워딩하는 저장 버퍼 | |
| JP3542021B2 (ja) | セット予測によりセット連想キャッシュの遅延を少なくする方法及び装置 | |
| US6523109B1 (en) | Store queue multimatch detection | |
| US7213126B1 (en) | Method and processor including logic for storing traces within a trace cache | |
| US6481251B1 (en) | Store queue number assignment and tracking | |
| US6321326B1 (en) | Prefetch instruction specifying destination functional unit and read/write access mode | |
| US20050050278A1 (en) | Low power way-predicted cache | |
| KR100586057B1 (ko) | 프리디코드 정보를 저장하기 위해 ecc/패리티 비트들의 이용 | |
| US6721877B1 (en) | Branch predictor that selects between predictions based on stored prediction selector and branch predictor index generation | |
| US6647490B2 (en) | Training line predictor for branch targets | |
| US5737749A (en) | Method and system for dynamically sharing cache capacity in a microprocessor | |
| US6363471B1 (en) | Mechanism for handling 16-bit addressing in a processor | |
| US6704854B1 (en) | Determination of execution resource allocation based on concurrently executable misaligned memory operations | |
| KR20020039689A (ko) | 정렬정보를 캐쉬하는 장치 및 방법 | |
| US11797308B2 (en) | Fetch stage handling of indirect jumps in a processor pipeline | |
| US6546478B1 (en) | Line predictor entry with location pointers and control information for corresponding instructions in a cache line | |
| US5878252A (en) | Microprocessor configured to generate help instructions for performing data cache fills | |
| US6636959B1 (en) | Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| A201 | Request for examination | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| G170 | Re-publication after modification of scope of protection [patent] | ||
| PG1701 | Publication of correction |
St.27 status event code: A-5-5-P10-P19-oth-PG1701 Patent document republication publication date: 20080417 Republication note text: Request for Correction Notice (Document Request) Gazette number: 1007471270000 Gazette reference publication date: 20070809 |
|
| FPAY | Annual fee payment |
Payment date: 20100729 Year of fee payment: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R14-asn-PN2301 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20110802 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20110802 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |